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1 /* Intel PRO/1000 Linux driver |
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2 * Copyright(c) 1999 - 2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * The full GNU General Public License is included in this distribution in |
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14 * the file called "COPYING". |
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15 * |
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16 * Contact Information: |
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17 * Linux NICS <linux.nics@intel.com> |
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18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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20 */ |
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21 |
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22 #ifndef _E1000E_PHY_H_ |
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23 #define _E1000E_PHY_H_ |
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24 |
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25 s32 e1000e_check_downshift(struct e1000_hw *hw); |
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26 s32 e1000_check_polarity_m88(struct e1000_hw *hw); |
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27 s32 e1000_check_polarity_igp(struct e1000_hw *hw); |
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28 s32 e1000_check_polarity_ife(struct e1000_hw *hw); |
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29 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); |
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30 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); |
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31 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); |
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32 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); |
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33 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); |
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34 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); |
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35 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); |
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36 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); |
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37 s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); |
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38 s32 e1000e_get_phy_id(struct e1000_hw *hw); |
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39 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); |
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40 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); |
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41 s32 e1000_get_phy_info_ife(struct e1000_hw *hw); |
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42 s32 e1000e_phy_sw_reset(struct e1000_hw *hw); |
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43 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); |
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44 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); |
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45 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); |
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46 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); |
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47 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
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48 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); |
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49 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); |
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50 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
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51 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); |
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52 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
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53 s32 e1000e_setup_copper_link(struct e1000_hw *hw); |
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54 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); |
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55 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); |
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56 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); |
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57 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); |
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58 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); |
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59 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
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60 u32 usec_interval, bool *success); |
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61 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); |
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62 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); |
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63 s32 e1000e_determine_phy_address(struct e1000_hw *hw); |
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64 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); |
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65 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); |
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66 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); |
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67 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); |
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68 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); |
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69 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); |
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70 void e1000_power_up_phy_copper(struct e1000_hw *hw); |
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71 void e1000_power_down_phy_copper(struct e1000_hw *hw); |
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72 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); |
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73 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); |
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74 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
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75 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
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76 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
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77 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); |
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78 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); |
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79 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); |
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80 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); |
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81 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); |
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82 s32 e1000_check_polarity_82577(struct e1000_hw *hw); |
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83 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); |
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84 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); |
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85 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); |
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86 |
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87 #define E1000_MAX_PHY_ADDR 8 |
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88 |
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89 /* IGP01E1000 Specific Registers */ |
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90 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ |
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91 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ |
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92 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ |
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93 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ |
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94 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ |
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95 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
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96 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ |
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97 #define IGP_PAGE_SHIFT 5 |
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98 #define PHY_REG_MASK 0x1F |
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99 |
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100 /* BM/HV Specific Registers */ |
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101 #define BM_PORT_CTRL_PAGE 769 |
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102 #define BM_WUC_PAGE 800 |
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103 #define BM_WUC_ADDRESS_OPCODE 0x11 |
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104 #define BM_WUC_DATA_OPCODE 0x12 |
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105 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE |
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106 #define BM_WUC_ENABLE_REG 17 |
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107 #define BM_WUC_ENABLE_BIT (1 << 2) |
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108 #define BM_WUC_HOST_WU_BIT (1 << 4) |
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109 #define BM_WUC_ME_WU_BIT (1 << 5) |
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110 |
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111 #define PHY_UPPER_SHIFT 21 |
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112 #define BM_PHY_REG(page, reg) \ |
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113 (((reg) & MAX_PHY_REG_ADDRESS) |\ |
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114 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ |
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115 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) |
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116 #define BM_PHY_REG_PAGE(offset) \ |
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117 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) |
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118 #define BM_PHY_REG_NUM(offset) \ |
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119 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ |
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120 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ |
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121 ~MAX_PHY_REG_ADDRESS))) |
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122 |
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123 #define HV_INTC_FC_PAGE_START 768 |
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124 #define I82578_ADDR_REG 29 |
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125 #define I82577_ADDR_REG 16 |
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126 #define I82577_CFG_REG 22 |
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127 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
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128 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ |
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129 #define I82577_CTRL_REG 23 |
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130 |
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131 /* 82577 specific PHY registers */ |
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132 #define I82577_PHY_CTRL_2 18 |
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133 #define I82577_PHY_LBK_CTRL 19 |
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134 #define I82577_PHY_STATUS_2 26 |
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135 #define I82577_PHY_DIAG_STATUS 31 |
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136 |
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137 /* I82577 PHY Status 2 */ |
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138 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
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139 #define I82577_PHY_STATUS2_MDIX 0x0800 |
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140 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
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141 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
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142 |
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143 /* I82577 PHY Control 2 */ |
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144 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 |
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145 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 |
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146 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 |
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147 |
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148 /* I82577 PHY Diagnostics Status */ |
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149 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC |
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150 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
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151 |
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152 /* BM PHY Copper Specific Control 1 */ |
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153 #define BM_CS_CTRL1 16 |
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154 |
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155 /* BM PHY Copper Specific Status */ |
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156 #define BM_CS_STATUS 17 |
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157 #define BM_CS_STATUS_LINK_UP 0x0400 |
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158 #define BM_CS_STATUS_RESOLVED 0x0800 |
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159 #define BM_CS_STATUS_SPEED_MASK 0xC000 |
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160 #define BM_CS_STATUS_SPEED_1000 0x8000 |
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161 |
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162 /* 82577 Mobile Phy Status Register */ |
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163 #define HV_M_STATUS 26 |
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164 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 |
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165 #define HV_M_STATUS_SPEED_MASK 0x0300 |
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166 #define HV_M_STATUS_SPEED_1000 0x0200 |
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167 #define HV_M_STATUS_SPEED_100 0x0100 |
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168 #define HV_M_STATUS_LINK_UP 0x0040 |
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169 |
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170 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
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171 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
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172 |
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173 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
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174 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ |
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175 |
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176 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
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177 |
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178 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ |
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179 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ |
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180 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ |
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181 |
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182 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
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183 |
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184 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
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185 #define IGP01E1000_PSSR_MDIX 0x0800 |
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186 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 |
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187 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
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188 |
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189 #define IGP02E1000_PHY_CHANNEL_NUM 4 |
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190 #define IGP02E1000_PHY_AGC_A 0x11B1 |
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191 #define IGP02E1000_PHY_AGC_B 0x12B1 |
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192 #define IGP02E1000_PHY_AGC_C 0x14B1 |
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193 #define IGP02E1000_PHY_AGC_D 0x18B1 |
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194 |
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195 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ |
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196 #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
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197 #define IGP02E1000_AGC_RANGE 15 |
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198 |
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199 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF |
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200 |
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201 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 |
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202 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 |
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203 #define E1000_KMRNCTRLSTA_REN 0x00200000 |
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204 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ |
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205 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ |
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206 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ |
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207 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ |
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208 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ |
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209 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ |
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210 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 |
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211 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ |
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212 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ |
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213 |
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214 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 |
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215 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ |
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216 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ |
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217 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ |
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218 |
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219 /* IFE PHY Extended Status Control */ |
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220 #define IFE_PESC_POLARITY_REVERSED 0x0100 |
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221 |
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222 /* IFE PHY Special Control */ |
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223 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 |
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224 #define IFE_PSC_FORCE_POLARITY 0x0020 |
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225 |
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226 /* IFE PHY Special Control and LED Control */ |
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227 #define IFE_PSCL_PROBE_MODE 0x0020 |
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228 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ |
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229 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ |
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230 |
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231 /* IFE PHY MDIX Control */ |
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232 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ |
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233 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ |
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234 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ |
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235 |
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236 #endif |