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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2013 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #include "e1000.h" |
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30 |
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31 /** |
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32 * e1000_raise_eec_clk - Raise EEPROM clock |
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33 * @hw: pointer to the HW structure |
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34 * @eecd: pointer to the EEPROM |
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35 * |
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36 * Enable/Raise the EEPROM clock bit. |
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37 **/ |
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38 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) |
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39 { |
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40 *eecd = *eecd | E1000_EECD_SK; |
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41 ew32(EECD, *eecd); |
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42 e1e_flush(); |
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43 udelay(hw->nvm.delay_usec); |
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44 } |
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45 |
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46 /** |
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47 * e1000_lower_eec_clk - Lower EEPROM clock |
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48 * @hw: pointer to the HW structure |
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49 * @eecd: pointer to the EEPROM |
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50 * |
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51 * Clear/Lower the EEPROM clock bit. |
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52 **/ |
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53 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) |
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54 { |
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55 *eecd = *eecd & ~E1000_EECD_SK; |
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56 ew32(EECD, *eecd); |
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57 e1e_flush(); |
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58 udelay(hw->nvm.delay_usec); |
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59 } |
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60 |
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61 /** |
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62 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM |
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63 * @hw: pointer to the HW structure |
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64 * @data: data to send to the EEPROM |
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65 * @count: number of bits to shift out |
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66 * |
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67 * We need to shift 'count' bits out to the EEPROM. So, the value in the |
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68 * "data" parameter will be shifted out to the EEPROM one bit at a time. |
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69 * In order to do this, "data" must be broken down into bits. |
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70 **/ |
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71 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) |
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72 { |
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73 struct e1000_nvm_info *nvm = &hw->nvm; |
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74 u32 eecd = er32(EECD); |
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75 u32 mask; |
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76 |
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77 mask = 0x01 << (count - 1); |
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78 if (nvm->type == e1000_nvm_eeprom_spi) |
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79 eecd |= E1000_EECD_DO; |
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80 |
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81 do { |
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82 eecd &= ~E1000_EECD_DI; |
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83 |
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84 if (data & mask) |
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85 eecd |= E1000_EECD_DI; |
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86 |
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87 ew32(EECD, eecd); |
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88 e1e_flush(); |
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89 |
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90 udelay(nvm->delay_usec); |
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91 |
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92 e1000_raise_eec_clk(hw, &eecd); |
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93 e1000_lower_eec_clk(hw, &eecd); |
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94 |
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95 mask >>= 1; |
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96 } while (mask); |
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97 |
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98 eecd &= ~E1000_EECD_DI; |
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99 ew32(EECD, eecd); |
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100 } |
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101 |
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102 /** |
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103 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM |
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104 * @hw: pointer to the HW structure |
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105 * @count: number of bits to shift in |
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106 * |
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107 * In order to read a register from the EEPROM, we need to shift 'count' bits |
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108 * in from the EEPROM. Bits are "shifted in" by raising the clock input to |
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109 * the EEPROM (setting the SK bit), and then reading the value of the data out |
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110 * "DO" bit. During this "shifting in" process the data in "DI" bit should |
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111 * always be clear. |
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112 **/ |
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113 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) |
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114 { |
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115 u32 eecd; |
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116 u32 i; |
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117 u16 data; |
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118 |
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119 eecd = er32(EECD); |
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120 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
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121 data = 0; |
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122 |
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123 for (i = 0; i < count; i++) { |
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124 data <<= 1; |
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125 e1000_raise_eec_clk(hw, &eecd); |
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126 |
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127 eecd = er32(EECD); |
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128 |
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129 eecd &= ~E1000_EECD_DI; |
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130 if (eecd & E1000_EECD_DO) |
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131 data |= 1; |
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132 |
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133 e1000_lower_eec_clk(hw, &eecd); |
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134 } |
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135 |
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136 return data; |
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137 } |
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138 |
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139 /** |
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140 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
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141 * @hw: pointer to the HW structure |
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142 * @ee_reg: EEPROM flag for polling |
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143 * |
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144 * Polls the EEPROM status bit for either read or write completion based |
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145 * upon the value of 'ee_reg'. |
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146 **/ |
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147 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) |
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148 { |
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149 u32 attempts = 100000; |
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150 u32 i, reg = 0; |
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151 |
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152 for (i = 0; i < attempts; i++) { |
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153 if (ee_reg == E1000_NVM_POLL_READ) |
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154 reg = er32(EERD); |
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155 else |
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156 reg = er32(EEWR); |
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157 |
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158 if (reg & E1000_NVM_RW_REG_DONE) |
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159 return 0; |
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160 |
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161 udelay(5); |
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162 } |
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163 |
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164 return -E1000_ERR_NVM; |
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165 } |
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166 |
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167 /** |
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168 * e1000e_acquire_nvm - Generic request for access to EEPROM |
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169 * @hw: pointer to the HW structure |
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170 * |
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171 * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
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172 * Return successful if access grant bit set, else clear the request for |
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173 * EEPROM access and return -E1000_ERR_NVM (-1). |
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174 **/ |
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175 s32 e1000e_acquire_nvm(struct e1000_hw *hw) |
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176 { |
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177 u32 eecd = er32(EECD); |
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178 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; |
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179 |
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180 ew32(EECD, eecd | E1000_EECD_REQ); |
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181 eecd = er32(EECD); |
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182 |
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183 while (timeout) { |
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184 if (eecd & E1000_EECD_GNT) |
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185 break; |
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186 udelay(5); |
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187 eecd = er32(EECD); |
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188 timeout--; |
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189 } |
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190 |
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191 if (!timeout) { |
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192 eecd &= ~E1000_EECD_REQ; |
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193 ew32(EECD, eecd); |
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194 e_dbg("Could not acquire NVM grant\n"); |
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195 return -E1000_ERR_NVM; |
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196 } |
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197 |
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198 return 0; |
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199 } |
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200 |
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201 /** |
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202 * e1000_standby_nvm - Return EEPROM to standby state |
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203 * @hw: pointer to the HW structure |
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204 * |
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205 * Return the EEPROM to a standby state. |
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206 **/ |
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207 static void e1000_standby_nvm(struct e1000_hw *hw) |
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208 { |
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209 struct e1000_nvm_info *nvm = &hw->nvm; |
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210 u32 eecd = er32(EECD); |
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211 |
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212 if (nvm->type == e1000_nvm_eeprom_spi) { |
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213 /* Toggle CS to flush commands */ |
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214 eecd |= E1000_EECD_CS; |
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215 ew32(EECD, eecd); |
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216 e1e_flush(); |
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217 udelay(nvm->delay_usec); |
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218 eecd &= ~E1000_EECD_CS; |
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219 ew32(EECD, eecd); |
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220 e1e_flush(); |
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221 udelay(nvm->delay_usec); |
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222 } |
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223 } |
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224 |
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225 /** |
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226 * e1000_stop_nvm - Terminate EEPROM command |
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227 * @hw: pointer to the HW structure |
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228 * |
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229 * Terminates the current command by inverting the EEPROM's chip select pin. |
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230 **/ |
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231 static void e1000_stop_nvm(struct e1000_hw *hw) |
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232 { |
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233 u32 eecd; |
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234 |
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235 eecd = er32(EECD); |
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236 if (hw->nvm.type == e1000_nvm_eeprom_spi) { |
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237 /* Pull CS high */ |
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238 eecd |= E1000_EECD_CS; |
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239 e1000_lower_eec_clk(hw, &eecd); |
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240 } |
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241 } |
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242 |
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243 /** |
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244 * e1000e_release_nvm - Release exclusive access to EEPROM |
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245 * @hw: pointer to the HW structure |
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246 * |
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247 * Stop any current commands to the EEPROM and clear the EEPROM request bit. |
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248 **/ |
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249 void e1000e_release_nvm(struct e1000_hw *hw) |
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250 { |
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251 u32 eecd; |
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252 |
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253 e1000_stop_nvm(hw); |
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254 |
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255 eecd = er32(EECD); |
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256 eecd &= ~E1000_EECD_REQ; |
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257 ew32(EECD, eecd); |
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258 } |
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259 |
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260 /** |
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261 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write |
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262 * @hw: pointer to the HW structure |
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263 * |
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264 * Setups the EEPROM for reading and writing. |
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265 **/ |
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266 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) |
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267 { |
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268 struct e1000_nvm_info *nvm = &hw->nvm; |
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269 u32 eecd = er32(EECD); |
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270 u8 spi_stat_reg; |
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271 |
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272 if (nvm->type == e1000_nvm_eeprom_spi) { |
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273 u16 timeout = NVM_MAX_RETRY_SPI; |
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274 |
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275 /* Clear SK and CS */ |
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276 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
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277 ew32(EECD, eecd); |
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278 e1e_flush(); |
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279 udelay(1); |
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280 |
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281 /* Read "Status Register" repeatedly until the LSB is cleared. |
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282 * The EEPROM will signal that the command has been completed |
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283 * by clearing bit 0 of the internal status register. If it's |
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284 * not cleared within 'timeout', then error out. |
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285 */ |
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286 while (timeout) { |
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287 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, |
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288 hw->nvm.opcode_bits); |
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289 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); |
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290 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) |
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291 break; |
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292 |
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293 udelay(5); |
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294 e1000_standby_nvm(hw); |
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295 timeout--; |
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296 } |
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297 |
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298 if (!timeout) { |
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299 e_dbg("SPI NVM Status error\n"); |
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300 return -E1000_ERR_NVM; |
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301 } |
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302 } |
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303 |
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304 return 0; |
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305 } |
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306 |
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307 /** |
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308 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register |
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309 * @hw: pointer to the HW structure |
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310 * @offset: offset of word in the EEPROM to read |
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311 * @words: number of words to read |
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312 * @data: word read from the EEPROM |
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313 * |
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314 * Reads a 16 bit word from the EEPROM using the EERD register. |
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315 **/ |
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316 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
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317 { |
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318 struct e1000_nvm_info *nvm = &hw->nvm; |
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319 u32 i, eerd = 0; |
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320 s32 ret_val = 0; |
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321 |
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322 /* A check for invalid values: offset too large, too many words, |
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323 * too many words for the offset, and not enough words. |
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324 */ |
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325 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
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326 (words == 0)) { |
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327 e_dbg("nvm parameter(s) out of bounds\n"); |
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328 return -E1000_ERR_NVM; |
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329 } |
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330 |
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331 for (i = 0; i < words; i++) { |
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332 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + |
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333 E1000_NVM_RW_REG_START; |
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334 |
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335 ew32(EERD, eerd); |
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336 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); |
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337 if (ret_val) |
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338 break; |
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339 |
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340 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); |
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341 } |
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342 |
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343 return ret_val; |
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344 } |
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345 |
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346 /** |
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347 * e1000e_write_nvm_spi - Write to EEPROM using SPI |
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348 * @hw: pointer to the HW structure |
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349 * @offset: offset within the EEPROM to be written to |
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350 * @words: number of words to write |
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351 * @data: 16 bit word(s) to be written to the EEPROM |
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352 * |
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353 * Writes data to EEPROM at offset using SPI interface. |
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354 * |
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355 * If e1000e_update_nvm_checksum is not called after this function , the |
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356 * EEPROM will most likely contain an invalid checksum. |
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357 **/ |
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358 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
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359 { |
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360 struct e1000_nvm_info *nvm = &hw->nvm; |
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361 s32 ret_val = -E1000_ERR_NVM; |
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362 u16 widx = 0; |
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363 |
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364 /* A check for invalid values: offset too large, too many words, |
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365 * and not enough words. |
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366 */ |
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367 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
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368 (words == 0)) { |
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369 e_dbg("nvm parameter(s) out of bounds\n"); |
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370 return -E1000_ERR_NVM; |
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371 } |
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372 |
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373 while (widx < words) { |
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374 u8 write_opcode = NVM_WRITE_OPCODE_SPI; |
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375 |
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376 ret_val = nvm->ops.acquire(hw); |
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377 if (ret_val) |
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378 return ret_val; |
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379 |
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380 ret_val = e1000_ready_nvm_eeprom(hw); |
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381 if (ret_val) { |
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382 nvm->ops.release(hw); |
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383 return ret_val; |
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384 } |
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385 |
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386 e1000_standby_nvm(hw); |
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387 |
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388 /* Send the WRITE ENABLE command (8 bit opcode) */ |
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389 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, |
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390 nvm->opcode_bits); |
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391 |
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392 e1000_standby_nvm(hw); |
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393 |
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394 /* Some SPI eeproms use the 8th address bit embedded in the |
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395 * opcode |
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396 */ |
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397 if ((nvm->address_bits == 8) && (offset >= 128)) |
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398 write_opcode |= NVM_A8_OPCODE_SPI; |
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399 |
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400 /* Send the Write command (8-bit opcode + addr) */ |
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401 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); |
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402 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), |
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403 nvm->address_bits); |
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404 |
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405 /* Loop to allow for up to whole page write of eeprom */ |
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406 while (widx < words) { |
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407 u16 word_out = data[widx]; |
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408 word_out = (word_out >> 8) | (word_out << 8); |
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409 e1000_shift_out_eec_bits(hw, word_out, 16); |
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410 widx++; |
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411 |
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412 if ((((offset + widx) * 2) % nvm->page_size) == 0) { |
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413 e1000_standby_nvm(hw); |
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414 break; |
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415 } |
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416 } |
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417 usleep_range(10000, 20000); |
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418 nvm->ops.release(hw); |
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419 } |
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420 |
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421 return ret_val; |
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422 } |
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423 |
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424 /** |
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425 * e1000_read_pba_string_generic - Read device part number |
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426 * @hw: pointer to the HW structure |
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427 * @pba_num: pointer to device part number |
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428 * @pba_num_size: size of part number buffer |
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429 * |
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430 * Reads the product board assembly (PBA) number from the EEPROM and stores |
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431 * the value in pba_num. |
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432 **/ |
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433 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, |
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434 u32 pba_num_size) |
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435 { |
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436 s32 ret_val; |
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437 u16 nvm_data; |
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438 u16 pba_ptr; |
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439 u16 offset; |
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440 u16 length; |
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441 |
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442 if (pba_num == NULL) { |
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443 e_dbg("PBA string buffer was null\n"); |
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444 return -E1000_ERR_INVALID_ARGUMENT; |
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445 } |
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446 |
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447 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); |
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448 if (ret_val) { |
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449 e_dbg("NVM Read Error\n"); |
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450 return ret_val; |
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451 } |
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452 |
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453 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); |
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454 if (ret_val) { |
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455 e_dbg("NVM Read Error\n"); |
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456 return ret_val; |
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457 } |
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458 |
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459 /* if nvm_data is not ptr guard the PBA must be in legacy format which |
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460 * means pba_ptr is actually our second data word for the PBA number |
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461 * and we can decode it into an ascii string |
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462 */ |
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463 if (nvm_data != NVM_PBA_PTR_GUARD) { |
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464 e_dbg("NVM PBA number is not stored as string\n"); |
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465 |
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466 /* make sure callers buffer is big enough to store the PBA */ |
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467 if (pba_num_size < E1000_PBANUM_LENGTH) { |
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468 e_dbg("PBA string buffer too small\n"); |
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469 return E1000_ERR_NO_SPACE; |
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470 } |
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471 |
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472 /* extract hex string from data and pba_ptr */ |
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473 pba_num[0] = (nvm_data >> 12) & 0xF; |
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474 pba_num[1] = (nvm_data >> 8) & 0xF; |
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475 pba_num[2] = (nvm_data >> 4) & 0xF; |
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476 pba_num[3] = nvm_data & 0xF; |
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477 pba_num[4] = (pba_ptr >> 12) & 0xF; |
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478 pba_num[5] = (pba_ptr >> 8) & 0xF; |
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479 pba_num[6] = '-'; |
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480 pba_num[7] = 0; |
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481 pba_num[8] = (pba_ptr >> 4) & 0xF; |
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482 pba_num[9] = pba_ptr & 0xF; |
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483 |
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484 /* put a null character on the end of our string */ |
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485 pba_num[10] = '\0'; |
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486 |
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487 /* switch all the data but the '-' to hex char */ |
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488 for (offset = 0; offset < 10; offset++) { |
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489 if (pba_num[offset] < 0xA) |
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490 pba_num[offset] += '0'; |
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491 else if (pba_num[offset] < 0x10) |
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492 pba_num[offset] += 'A' - 0xA; |
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493 } |
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494 |
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495 return 0; |
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496 } |
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497 |
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498 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); |
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499 if (ret_val) { |
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500 e_dbg("NVM Read Error\n"); |
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501 return ret_val; |
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502 } |
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503 |
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504 if (length == 0xFFFF || length == 0) { |
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505 e_dbg("NVM PBA number section invalid length\n"); |
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506 return -E1000_ERR_NVM_PBA_SECTION; |
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507 } |
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508 /* check if pba_num buffer is big enough */ |
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509 if (pba_num_size < (((u32)length * 2) - 1)) { |
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510 e_dbg("PBA string buffer too small\n"); |
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511 return -E1000_ERR_NO_SPACE; |
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512 } |
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513 |
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514 /* trim pba length from start of string */ |
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515 pba_ptr++; |
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516 length--; |
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517 |
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518 for (offset = 0; offset < length; offset++) { |
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519 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); |
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520 if (ret_val) { |
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521 e_dbg("NVM Read Error\n"); |
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522 return ret_val; |
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523 } |
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524 pba_num[offset * 2] = (u8)(nvm_data >> 8); |
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525 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); |
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526 } |
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527 pba_num[offset * 2] = '\0'; |
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528 |
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529 return 0; |
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530 } |
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531 |
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532 /** |
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533 * e1000_read_mac_addr_generic - Read device MAC address |
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534 * @hw: pointer to the HW structure |
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535 * |
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536 * Reads the device MAC address from the EEPROM and stores the value. |
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537 * Since devices with two ports use the same EEPROM, we increment the |
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538 * last bit in the MAC address for the second port. |
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539 **/ |
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540 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) |
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541 { |
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542 u32 rar_high; |
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543 u32 rar_low; |
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544 u16 i; |
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545 |
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546 rar_high = er32(RAH(0)); |
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547 rar_low = er32(RAL(0)); |
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548 |
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549 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) |
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550 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8)); |
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551 |
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552 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) |
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553 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8)); |
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554 |
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555 for (i = 0; i < ETH_ALEN; i++) |
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556 hw->mac.addr[i] = hw->mac.perm_addr[i]; |
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557 |
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558 return 0; |
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559 } |
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560 |
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561 /** |
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562 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum |
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563 * @hw: pointer to the HW structure |
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564 * |
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565 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
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566 * and then verifies that the sum of the EEPROM is equal to 0xBABA. |
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567 **/ |
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568 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) |
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569 { |
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570 s32 ret_val; |
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571 u16 checksum = 0; |
|
572 u16 i, nvm_data; |
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573 |
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574 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { |
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575 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); |
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576 if (ret_val) { |
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577 e_dbg("NVM Read Error\n"); |
|
578 return ret_val; |
|
579 } |
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580 checksum += nvm_data; |
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581 } |
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582 |
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583 if (checksum != (u16)NVM_SUM) { |
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584 e_dbg("NVM Checksum Invalid\n"); |
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585 return -E1000_ERR_NVM; |
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586 } |
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587 |
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588 return 0; |
|
589 } |
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590 |
|
591 /** |
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592 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum |
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593 * @hw: pointer to the HW structure |
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594 * |
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595 * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
|
596 * up to the checksum. Then calculates the EEPROM checksum and writes the |
|
597 * value to the EEPROM. |
|
598 **/ |
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599 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) |
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600 { |
|
601 s32 ret_val; |
|
602 u16 checksum = 0; |
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603 u16 i, nvm_data; |
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604 |
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605 for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
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606 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); |
|
607 if (ret_val) { |
|
608 e_dbg("NVM Read Error while updating checksum.\n"); |
|
609 return ret_val; |
|
610 } |
|
611 checksum += nvm_data; |
|
612 } |
|
613 checksum = (u16)NVM_SUM - checksum; |
|
614 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); |
|
615 if (ret_val) |
|
616 e_dbg("NVM Write Error while updating checksum.\n"); |
|
617 |
|
618 return ret_val; |
|
619 } |
|
620 |
|
621 /** |
|
622 * e1000e_reload_nvm_generic - Reloads EEPROM |
|
623 * @hw: pointer to the HW structure |
|
624 * |
|
625 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the |
|
626 * extended control register. |
|
627 **/ |
|
628 void e1000e_reload_nvm_generic(struct e1000_hw *hw) |
|
629 { |
|
630 u32 ctrl_ext; |
|
631 |
|
632 usleep_range(10, 20); |
|
633 ctrl_ext = er32(CTRL_EXT); |
|
634 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
635 ew32(CTRL_EXT, ctrl_ext); |
|
636 e1e_flush(); |
|
637 } |