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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2012 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 /* 82562G 10/100 Network Connection |
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30 * 82562G-2 10/100 Network Connection |
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31 * 82562GT 10/100 Network Connection |
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32 * 82562GT-2 10/100 Network Connection |
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33 * 82562V 10/100 Network Connection |
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34 * 82562V-2 10/100 Network Connection |
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35 * 82566DC-2 Gigabit Network Connection |
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36 * 82566DC Gigabit Network Connection |
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37 * 82566DM-2 Gigabit Network Connection |
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38 * 82566DM Gigabit Network Connection |
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39 * 82566MC Gigabit Network Connection |
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40 * 82566MM Gigabit Network Connection |
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41 * 82567LM Gigabit Network Connection |
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42 * 82567LF Gigabit Network Connection |
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43 * 82567V Gigabit Network Connection |
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44 * 82567LM-2 Gigabit Network Connection |
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45 * 82567LF-2 Gigabit Network Connection |
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46 * 82567V-2 Gigabit Network Connection |
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47 * 82567LF-3 Gigabit Network Connection |
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48 * 82567LM-3 Gigabit Network Connection |
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49 * 82567LM-4 Gigabit Network Connection |
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50 * 82577LM Gigabit Network Connection |
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51 * 82577LC Gigabit Network Connection |
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52 * 82578DM Gigabit Network Connection |
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53 * 82578DC Gigabit Network Connection |
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54 * 82579LM Gigabit Network Connection |
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55 * 82579V Gigabit Network Connection |
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56 */ |
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57 |
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58 #include "e1000-3.8-ethercat.h" |
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59 |
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60 #define ICH_FLASH_GFPREG 0x0000 |
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61 #define ICH_FLASH_HSFSTS 0x0004 |
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62 #define ICH_FLASH_HSFCTL 0x0006 |
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63 #define ICH_FLASH_FADDR 0x0008 |
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64 #define ICH_FLASH_FDATA0 0x0010 |
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65 #define ICH_FLASH_PR0 0x0074 |
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66 |
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67 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 |
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68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 |
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69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 |
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70 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
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71 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 |
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72 |
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73 #define ICH_CYCLE_READ 0 |
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74 #define ICH_CYCLE_WRITE 2 |
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75 #define ICH_CYCLE_ERASE 3 |
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76 |
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77 #define FLASH_GFPREG_BASE_MASK 0x1FFF |
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78 #define FLASH_SECTOR_ADDR_SHIFT 12 |
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79 |
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80 #define ICH_FLASH_SEG_SIZE_256 256 |
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81 #define ICH_FLASH_SEG_SIZE_4K 4096 |
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82 #define ICH_FLASH_SEG_SIZE_8K 8192 |
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83 #define ICH_FLASH_SEG_SIZE_64K 65536 |
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84 |
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85 |
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86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ |
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87 /* FW established a valid mode */ |
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88 #define E1000_ICH_FWSM_FW_VALID 0x00008000 |
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89 |
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90 #define E1000_ICH_MNG_IAMT_MODE 0x2 |
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91 |
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92 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ |
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93 (ID_LED_DEF1_OFF2 << 8) | \ |
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94 (ID_LED_DEF1_ON2 << 4) | \ |
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95 (ID_LED_DEF1_DEF2)) |
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96 |
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97 #define E1000_ICH_NVM_SIG_WORD 0x13 |
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98 #define E1000_ICH_NVM_SIG_MASK 0xC000 |
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99 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 |
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100 #define E1000_ICH_NVM_SIG_VALUE 0x80 |
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101 |
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102 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 |
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103 |
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104 #define E1000_FEXTNVM_SW_CONFIG 1 |
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105 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ |
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106 |
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107 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 |
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108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 |
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109 |
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110 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 |
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111 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 |
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112 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 |
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113 |
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114 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL |
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115 |
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116 #define E1000_ICH_RAR_ENTRIES 7 |
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117 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ |
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118 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ |
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119 |
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120 #define PHY_PAGE_SHIFT 5 |
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121 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ |
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122 ((reg) & MAX_PHY_REG_ADDRESS)) |
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123 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ |
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124 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ |
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125 |
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126 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 |
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127 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 |
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128 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 |
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129 |
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130 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
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131 |
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132 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ |
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133 |
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134 /* SMBus Control Phy Register */ |
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135 #define CV_SMB_CTRL PHY_REG(769, 23) |
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136 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 |
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137 |
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138 /* SMBus Address Phy Register */ |
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139 #define HV_SMB_ADDR PHY_REG(768, 26) |
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140 #define HV_SMB_ADDR_MASK 0x007F |
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141 #define HV_SMB_ADDR_PEC_EN 0x0200 |
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142 #define HV_SMB_ADDR_VALID 0x0080 |
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143 #define HV_SMB_ADDR_FREQ_MASK 0x1100 |
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144 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 |
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145 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 |
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146 |
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147 /* PHY Power Management Control */ |
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148 #define HV_PM_CTRL PHY_REG(770, 17) |
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149 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 |
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150 |
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151 /* PHY Low Power Idle Control */ |
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152 #define I82579_LPI_CTRL PHY_REG(772, 20) |
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153 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 |
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154 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 |
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155 |
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156 /* EMI Registers */ |
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157 #define I82579_EMI_ADDR 0x10 |
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158 #define I82579_EMI_DATA 0x11 |
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159 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ |
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160 #define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ |
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161 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ |
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162 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ |
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163 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ |
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164 #define I217_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */ |
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165 |
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166 /* Intel Rapid Start Technology Support */ |
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167 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) |
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168 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 |
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169 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) |
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170 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 |
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171 #define I217_CGFREG PHY_REG(772, 29) |
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172 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 |
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173 #define I217_MEMPWR PHY_REG(772, 26) |
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174 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 |
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175 |
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176 /* Strapping Option Register - RO */ |
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177 #define E1000_STRAP 0x0000C |
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178 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 |
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179 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 |
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180 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 |
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181 #define E1000_STRAP_SMT_FREQ_SHIFT 12 |
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182 |
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183 /* OEM Bits Phy Register */ |
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184 #define HV_OEM_BITS PHY_REG(768, 25) |
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185 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ |
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186 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ |
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187 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ |
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188 |
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189 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ |
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190 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ |
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191 |
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192 /* KMRN Mode Control */ |
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193 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) |
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194 #define HV_KMRN_MDIO_SLOW 0x0400 |
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195 |
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196 /* KMRN FIFO Control and Status */ |
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197 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) |
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198 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 |
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199 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 |
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200 |
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201 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
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202 /* Offset 04h HSFSTS */ |
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203 union ich8_hws_flash_status { |
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204 struct ich8_hsfsts { |
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205 u16 flcdone :1; /* bit 0 Flash Cycle Done */ |
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206 u16 flcerr :1; /* bit 1 Flash Cycle Error */ |
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207 u16 dael :1; /* bit 2 Direct Access error Log */ |
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208 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ |
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209 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ |
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210 u16 reserved1 :2; /* bit 13:6 Reserved */ |
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211 u16 reserved2 :6; /* bit 13:6 Reserved */ |
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212 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ |
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213 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ |
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214 } hsf_status; |
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215 u16 regval; |
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216 }; |
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217 |
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218 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ |
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219 /* Offset 06h FLCTL */ |
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220 union ich8_hws_flash_ctrl { |
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221 struct ich8_hsflctl { |
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222 u16 flcgo :1; /* 0 Flash Cycle Go */ |
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223 u16 flcycle :2; /* 2:1 Flash Cycle */ |
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224 u16 reserved :5; /* 7:3 Reserved */ |
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225 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ |
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226 u16 flockdn :6; /* 15:10 Reserved */ |
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227 } hsf_ctrl; |
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228 u16 regval; |
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229 }; |
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230 |
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231 /* ICH Flash Region Access Permissions */ |
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232 union ich8_hws_flash_regacc { |
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233 struct ich8_flracc { |
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234 u32 grra :8; /* 0:7 GbE region Read Access */ |
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235 u32 grwa :8; /* 8:15 GbE region Write Access */ |
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236 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ |
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237 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ |
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238 } hsf_flregacc; |
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239 u16 regval; |
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240 }; |
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241 |
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242 /* ICH Flash Protected Region */ |
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243 union ich8_flash_protected_range { |
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244 struct ich8_pr { |
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245 u32 base:13; /* 0:12 Protected Range Base */ |
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246 u32 reserved1:2; /* 13:14 Reserved */ |
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247 u32 rpe:1; /* 15 Read Protection Enable */ |
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248 u32 limit:13; /* 16:28 Protected Range Limit */ |
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249 u32 reserved2:2; /* 29:30 Reserved */ |
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250 u32 wpe:1; /* 31 Write Protection Enable */ |
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251 } range; |
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252 u32 regval; |
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253 }; |
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254 |
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255 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); |
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256 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); |
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257 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); |
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258 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); |
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259 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
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260 u32 offset, u8 byte); |
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261 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
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262 u8 *data); |
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263 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
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264 u16 *data); |
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265 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
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266 u8 size, u16 *data); |
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267 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); |
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268 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); |
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269 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); |
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270 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); |
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271 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); |
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272 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); |
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273 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); |
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274 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); |
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275 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); |
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276 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); |
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277 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); |
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278 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); |
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279 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); |
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280 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); |
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281 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); |
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282 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); |
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283 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); |
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284 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); |
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285 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); |
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286 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); |
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287 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); |
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288 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); |
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289 |
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290 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) |
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291 { |
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292 return readw(hw->flash_address + reg); |
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293 } |
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294 |
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295 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) |
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296 { |
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297 return readl(hw->flash_address + reg); |
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298 } |
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299 |
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300 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) |
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301 { |
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302 writew(val, hw->flash_address + reg); |
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303 } |
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304 |
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305 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) |
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306 { |
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307 writel(val, hw->flash_address + reg); |
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308 } |
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309 |
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310 #define er16flash(reg) __er16flash(hw, (reg)) |
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311 #define er32flash(reg) __er32flash(hw, (reg)) |
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312 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) |
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313 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) |
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314 |
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315 /** |
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316 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers |
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317 * @hw: pointer to the HW structure |
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318 * |
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319 * Test access to the PHY registers by reading the PHY ID registers. If |
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320 * the PHY ID is already known (e.g. resume path) compare it with known ID, |
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321 * otherwise assume the read PHY ID is correct if it is valid. |
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322 * |
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323 * Assumes the sw/fw/hw semaphore is already acquired. |
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324 **/ |
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325 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) |
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326 { |
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327 u16 phy_reg = 0; |
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328 u32 phy_id = 0; |
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329 s32 ret_val; |
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330 u16 retry_count; |
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331 |
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332 for (retry_count = 0; retry_count < 2; retry_count++) { |
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333 ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg); |
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334 if (ret_val || (phy_reg == 0xFFFF)) |
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335 continue; |
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336 phy_id = (u32)(phy_reg << 16); |
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337 |
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338 ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg); |
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339 if (ret_val || (phy_reg == 0xFFFF)) { |
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340 phy_id = 0; |
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341 continue; |
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342 } |
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343 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); |
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344 break; |
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345 } |
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346 |
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347 if (hw->phy.id) { |
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348 if (hw->phy.id == phy_id) |
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349 return true; |
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350 } else if (phy_id) { |
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351 hw->phy.id = phy_id; |
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352 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); |
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353 return true; |
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354 } |
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355 |
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356 /* In case the PHY needs to be in mdio slow mode, |
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357 * set slow mode and try to get the PHY id again. |
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358 */ |
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359 hw->phy.ops.release(hw); |
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360 ret_val = e1000_set_mdio_slow_mode_hv(hw); |
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361 if (!ret_val) |
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362 ret_val = e1000e_get_phy_id(hw); |
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363 hw->phy.ops.acquire(hw); |
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364 |
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365 return !ret_val; |
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366 } |
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367 |
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368 /** |
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369 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds |
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370 * @hw: pointer to the HW structure |
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371 * |
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372 * Workarounds/flow necessary for PHY initialization during driver load |
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373 * and resume paths. |
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374 **/ |
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375 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) |
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376 { |
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377 u32 mac_reg, fwsm = er32(FWSM); |
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378 s32 ret_val; |
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379 u16 phy_reg; |
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380 |
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381 ret_val = hw->phy.ops.acquire(hw); |
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382 if (ret_val) { |
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383 e_dbg("Failed to initialize PHY flow\n"); |
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384 return ret_val; |
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385 } |
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386 |
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387 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is |
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388 * inaccessible and resetting the PHY is not blocked, toggle the |
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389 * LANPHYPC Value bit to force the interconnect to PCIe mode. |
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390 */ |
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391 switch (hw->mac.type) { |
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392 case e1000_pch_lpt: |
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393 if (e1000_phy_is_accessible_pchlan(hw)) |
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394 break; |
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395 |
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396 /* Before toggling LANPHYPC, see if PHY is accessible by |
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397 * forcing MAC to SMBus mode first. |
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398 */ |
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399 mac_reg = er32(CTRL_EXT); |
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400 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; |
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401 ew32(CTRL_EXT, mac_reg); |
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402 |
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403 /* fall-through */ |
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404 case e1000_pch2lan: |
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405 /* Gate automatic PHY configuration by hardware on |
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406 * non-managed 82579 |
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407 */ |
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408 if ((hw->mac.type == e1000_pch2lan) && |
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409 !(fwsm & E1000_ICH_FWSM_FW_VALID)) |
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410 e1000_gate_hw_phy_config_ich8lan(hw, true); |
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411 |
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412 if (e1000_phy_is_accessible_pchlan(hw)) { |
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413 if (hw->mac.type == e1000_pch_lpt) { |
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414 /* Unforce SMBus mode in PHY */ |
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415 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); |
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416 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; |
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417 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); |
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418 |
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419 /* Unforce SMBus mode in MAC */ |
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420 mac_reg = er32(CTRL_EXT); |
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421 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; |
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422 ew32(CTRL_EXT, mac_reg); |
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423 } |
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424 break; |
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425 } |
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426 |
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427 /* fall-through */ |
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428 case e1000_pchlan: |
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429 if ((hw->mac.type == e1000_pchlan) && |
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430 (fwsm & E1000_ICH_FWSM_FW_VALID)) |
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431 break; |
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432 |
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433 if (hw->phy.ops.check_reset_block(hw)) { |
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434 e_dbg("Required LANPHYPC toggle blocked by ME\n"); |
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435 break; |
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436 } |
|
437 |
|
438 e_dbg("Toggling LANPHYPC\n"); |
|
439 |
|
440 /* Set Phy Config Counter to 50msec */ |
|
441 mac_reg = er32(FEXTNVM3); |
|
442 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; |
|
443 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; |
|
444 ew32(FEXTNVM3, mac_reg); |
|
445 |
|
446 /* Toggle LANPHYPC Value bit */ |
|
447 mac_reg = er32(CTRL); |
|
448 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; |
|
449 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; |
|
450 ew32(CTRL, mac_reg); |
|
451 e1e_flush(); |
|
452 udelay(10); |
|
453 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; |
|
454 ew32(CTRL, mac_reg); |
|
455 e1e_flush(); |
|
456 if (hw->mac.type < e1000_pch_lpt) { |
|
457 msleep(50); |
|
458 } else { |
|
459 u16 count = 20; |
|
460 do { |
|
461 usleep_range(5000, 10000); |
|
462 } while (!(er32(CTRL_EXT) & |
|
463 E1000_CTRL_EXT_LPCD) && count--); |
|
464 } |
|
465 break; |
|
466 default: |
|
467 break; |
|
468 } |
|
469 |
|
470 hw->phy.ops.release(hw); |
|
471 |
|
472 /* Reset the PHY before any access to it. Doing so, ensures |
|
473 * that the PHY is in a known good state before we read/write |
|
474 * PHY registers. The generic reset is sufficient here, |
|
475 * because we haven't determined the PHY type yet. |
|
476 */ |
|
477 ret_val = e1000e_phy_hw_reset_generic(hw); |
|
478 |
|
479 /* Ungate automatic PHY configuration on non-managed 82579 */ |
|
480 if ((hw->mac.type == e1000_pch2lan) && |
|
481 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { |
|
482 usleep_range(10000, 20000); |
|
483 e1000_gate_hw_phy_config_ich8lan(hw, false); |
|
484 } |
|
485 |
|
486 return ret_val; |
|
487 } |
|
488 |
|
489 /** |
|
490 * e1000_init_phy_params_pchlan - Initialize PHY function pointers |
|
491 * @hw: pointer to the HW structure |
|
492 * |
|
493 * Initialize family-specific PHY parameters and function pointers. |
|
494 **/ |
|
495 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) |
|
496 { |
|
497 struct e1000_phy_info *phy = &hw->phy; |
|
498 s32 ret_val = 0; |
|
499 |
|
500 phy->addr = 1; |
|
501 phy->reset_delay_us = 100; |
|
502 |
|
503 phy->ops.set_page = e1000_set_page_igp; |
|
504 phy->ops.read_reg = e1000_read_phy_reg_hv; |
|
505 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; |
|
506 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; |
|
507 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; |
|
508 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; |
|
509 phy->ops.write_reg = e1000_write_phy_reg_hv; |
|
510 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; |
|
511 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; |
|
512 phy->ops.power_up = e1000_power_up_phy_copper; |
|
513 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
|
514 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
515 |
|
516 phy->id = e1000_phy_unknown; |
|
517 |
|
518 ret_val = e1000_init_phy_workarounds_pchlan(hw); |
|
519 if (ret_val) |
|
520 return ret_val; |
|
521 |
|
522 if (phy->id == e1000_phy_unknown) |
|
523 switch (hw->mac.type) { |
|
524 default: |
|
525 ret_val = e1000e_get_phy_id(hw); |
|
526 if (ret_val) |
|
527 return ret_val; |
|
528 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) |
|
529 break; |
|
530 /* fall-through */ |
|
531 case e1000_pch2lan: |
|
532 case e1000_pch_lpt: |
|
533 /* In case the PHY needs to be in mdio slow mode, |
|
534 * set slow mode and try to get the PHY id again. |
|
535 */ |
|
536 ret_val = e1000_set_mdio_slow_mode_hv(hw); |
|
537 if (ret_val) |
|
538 return ret_val; |
|
539 ret_val = e1000e_get_phy_id(hw); |
|
540 if (ret_val) |
|
541 return ret_val; |
|
542 break; |
|
543 } |
|
544 phy->type = e1000e_get_phy_type_from_id(phy->id); |
|
545 |
|
546 switch (phy->type) { |
|
547 case e1000_phy_82577: |
|
548 case e1000_phy_82579: |
|
549 case e1000_phy_i217: |
|
550 phy->ops.check_polarity = e1000_check_polarity_82577; |
|
551 phy->ops.force_speed_duplex = |
|
552 e1000_phy_force_speed_duplex_82577; |
|
553 phy->ops.get_cable_length = e1000_get_cable_length_82577; |
|
554 phy->ops.get_info = e1000_get_phy_info_82577; |
|
555 phy->ops.commit = e1000e_phy_sw_reset; |
|
556 break; |
|
557 case e1000_phy_82578: |
|
558 phy->ops.check_polarity = e1000_check_polarity_m88; |
|
559 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; |
|
560 phy->ops.get_cable_length = e1000e_get_cable_length_m88; |
|
561 phy->ops.get_info = e1000e_get_phy_info_m88; |
|
562 break; |
|
563 default: |
|
564 ret_val = -E1000_ERR_PHY; |
|
565 break; |
|
566 } |
|
567 |
|
568 return ret_val; |
|
569 } |
|
570 |
|
571 /** |
|
572 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers |
|
573 * @hw: pointer to the HW structure |
|
574 * |
|
575 * Initialize family-specific PHY parameters and function pointers. |
|
576 **/ |
|
577 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) |
|
578 { |
|
579 struct e1000_phy_info *phy = &hw->phy; |
|
580 s32 ret_val; |
|
581 u16 i = 0; |
|
582 |
|
583 phy->addr = 1; |
|
584 phy->reset_delay_us = 100; |
|
585 |
|
586 phy->ops.power_up = e1000_power_up_phy_copper; |
|
587 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
|
588 |
|
589 /* We may need to do this twice - once for IGP and if that fails, |
|
590 * we'll set BM func pointers and try again |
|
591 */ |
|
592 ret_val = e1000e_determine_phy_address(hw); |
|
593 if (ret_val) { |
|
594 phy->ops.write_reg = e1000e_write_phy_reg_bm; |
|
595 phy->ops.read_reg = e1000e_read_phy_reg_bm; |
|
596 ret_val = e1000e_determine_phy_address(hw); |
|
597 if (ret_val) { |
|
598 e_dbg("Cannot determine PHY addr. Erroring out\n"); |
|
599 return ret_val; |
|
600 } |
|
601 } |
|
602 |
|
603 phy->id = 0; |
|
604 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && |
|
605 (i++ < 100)) { |
|
606 usleep_range(1000, 2000); |
|
607 ret_val = e1000e_get_phy_id(hw); |
|
608 if (ret_val) |
|
609 return ret_val; |
|
610 } |
|
611 |
|
612 /* Verify phy id */ |
|
613 switch (phy->id) { |
|
614 case IGP03E1000_E_PHY_ID: |
|
615 phy->type = e1000_phy_igp_3; |
|
616 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
617 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; |
|
618 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; |
|
619 phy->ops.get_info = e1000e_get_phy_info_igp; |
|
620 phy->ops.check_polarity = e1000_check_polarity_igp; |
|
621 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; |
|
622 break; |
|
623 case IFE_E_PHY_ID: |
|
624 case IFE_PLUS_E_PHY_ID: |
|
625 case IFE_C_E_PHY_ID: |
|
626 phy->type = e1000_phy_ife; |
|
627 phy->autoneg_mask = E1000_ALL_NOT_GIG; |
|
628 phy->ops.get_info = e1000_get_phy_info_ife; |
|
629 phy->ops.check_polarity = e1000_check_polarity_ife; |
|
630 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; |
|
631 break; |
|
632 case BME1000_E_PHY_ID: |
|
633 phy->type = e1000_phy_bm; |
|
634 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
635 phy->ops.read_reg = e1000e_read_phy_reg_bm; |
|
636 phy->ops.write_reg = e1000e_write_phy_reg_bm; |
|
637 phy->ops.commit = e1000e_phy_sw_reset; |
|
638 phy->ops.get_info = e1000e_get_phy_info_m88; |
|
639 phy->ops.check_polarity = e1000_check_polarity_m88; |
|
640 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; |
|
641 break; |
|
642 default: |
|
643 return -E1000_ERR_PHY; |
|
644 break; |
|
645 } |
|
646 |
|
647 return 0; |
|
648 } |
|
649 |
|
650 /** |
|
651 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers |
|
652 * @hw: pointer to the HW structure |
|
653 * |
|
654 * Initialize family-specific NVM parameters and function |
|
655 * pointers. |
|
656 **/ |
|
657 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) |
|
658 { |
|
659 struct e1000_nvm_info *nvm = &hw->nvm; |
|
660 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
661 u32 gfpreg, sector_base_addr, sector_end_addr; |
|
662 u16 i; |
|
663 |
|
664 /* Can't read flash registers if the register set isn't mapped. */ |
|
665 if (!hw->flash_address) { |
|
666 e_dbg("ERROR: Flash registers not mapped\n"); |
|
667 return -E1000_ERR_CONFIG; |
|
668 } |
|
669 |
|
670 nvm->type = e1000_nvm_flash_sw; |
|
671 |
|
672 gfpreg = er32flash(ICH_FLASH_GFPREG); |
|
673 |
|
674 /* sector_X_addr is a "sector"-aligned address (4096 bytes) |
|
675 * Add 1 to sector_end_addr since this sector is included in |
|
676 * the overall size. |
|
677 */ |
|
678 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
|
679 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; |
|
680 |
|
681 /* flash_base_addr is byte-aligned */ |
|
682 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; |
|
683 |
|
684 /* find total size of the NVM, then cut in half since the total |
|
685 * size represents two separate NVM banks. |
|
686 */ |
|
687 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
|
688 << FLASH_SECTOR_ADDR_SHIFT; |
|
689 nvm->flash_bank_size /= 2; |
|
690 /* Adjust to word count */ |
|
691 nvm->flash_bank_size /= sizeof(u16); |
|
692 |
|
693 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; |
|
694 |
|
695 /* Clear shadow ram */ |
|
696 for (i = 0; i < nvm->word_size; i++) { |
|
697 dev_spec->shadow_ram[i].modified = false; |
|
698 dev_spec->shadow_ram[i].value = 0xFFFF; |
|
699 } |
|
700 |
|
701 return 0; |
|
702 } |
|
703 |
|
704 /** |
|
705 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers |
|
706 * @hw: pointer to the HW structure |
|
707 * |
|
708 * Initialize family-specific MAC parameters and function |
|
709 * pointers. |
|
710 **/ |
|
711 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) |
|
712 { |
|
713 struct e1000_mac_info *mac = &hw->mac; |
|
714 |
|
715 /* Set media type function pointer */ |
|
716 hw->phy.media_type = e1000_media_type_copper; |
|
717 |
|
718 /* Set mta register count */ |
|
719 mac->mta_reg_count = 32; |
|
720 /* Set rar entry count */ |
|
721 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; |
|
722 if (mac->type == e1000_ich8lan) |
|
723 mac->rar_entry_count--; |
|
724 /* FWSM register */ |
|
725 mac->has_fwsm = true; |
|
726 /* ARC subsystem not supported */ |
|
727 mac->arc_subsystem_valid = false; |
|
728 /* Adaptive IFS supported */ |
|
729 mac->adaptive_ifs = true; |
|
730 |
|
731 /* LED and other operations */ |
|
732 switch (mac->type) { |
|
733 case e1000_ich8lan: |
|
734 case e1000_ich9lan: |
|
735 case e1000_ich10lan: |
|
736 /* check management mode */ |
|
737 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; |
|
738 /* ID LED init */ |
|
739 mac->ops.id_led_init = e1000e_id_led_init_generic; |
|
740 /* blink LED */ |
|
741 mac->ops.blink_led = e1000e_blink_led_generic; |
|
742 /* setup LED */ |
|
743 mac->ops.setup_led = e1000e_setup_led_generic; |
|
744 /* cleanup LED */ |
|
745 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; |
|
746 /* turn on/off LED */ |
|
747 mac->ops.led_on = e1000_led_on_ich8lan; |
|
748 mac->ops.led_off = e1000_led_off_ich8lan; |
|
749 break; |
|
750 case e1000_pch2lan: |
|
751 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; |
|
752 mac->ops.rar_set = e1000_rar_set_pch2lan; |
|
753 /* fall-through */ |
|
754 case e1000_pch_lpt: |
|
755 case e1000_pchlan: |
|
756 /* check management mode */ |
|
757 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; |
|
758 /* ID LED init */ |
|
759 mac->ops.id_led_init = e1000_id_led_init_pchlan; |
|
760 /* setup LED */ |
|
761 mac->ops.setup_led = e1000_setup_led_pchlan; |
|
762 /* cleanup LED */ |
|
763 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; |
|
764 /* turn on/off LED */ |
|
765 mac->ops.led_on = e1000_led_on_pchlan; |
|
766 mac->ops.led_off = e1000_led_off_pchlan; |
|
767 break; |
|
768 default: |
|
769 break; |
|
770 } |
|
771 |
|
772 if (mac->type == e1000_pch_lpt) { |
|
773 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; |
|
774 mac->ops.rar_set = e1000_rar_set_pch_lpt; |
|
775 } |
|
776 |
|
777 /* Enable PCS Lock-loss workaround for ICH8 */ |
|
778 if (mac->type == e1000_ich8lan) |
|
779 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); |
|
780 |
|
781 /* Gate automatic PHY configuration by hardware on managed |
|
782 * 82579 and i217 |
|
783 */ |
|
784 if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) && |
|
785 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
|
786 e1000_gate_hw_phy_config_ich8lan(hw, true); |
|
787 |
|
788 return 0; |
|
789 } |
|
790 |
|
791 /** |
|
792 * e1000_set_eee_pchlan - Enable/disable EEE support |
|
793 * @hw: pointer to the HW structure |
|
794 * |
|
795 * Enable/disable EEE based on setting in dev_spec structure. The bits in |
|
796 * the LPI Control register will remain set only if/when link is up. |
|
797 **/ |
|
798 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) |
|
799 { |
|
800 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
801 s32 ret_val = 0; |
|
802 u16 phy_reg; |
|
803 |
|
804 if ((hw->phy.type != e1000_phy_82579) && |
|
805 (hw->phy.type != e1000_phy_i217)) |
|
806 return 0; |
|
807 |
|
808 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
|
809 if (ret_val) |
|
810 return ret_val; |
|
811 |
|
812 if (dev_spec->eee_disable) |
|
813 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; |
|
814 else |
|
815 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; |
|
816 |
|
817 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
|
818 if (ret_val) |
|
819 return ret_val; |
|
820 |
|
821 if ((hw->phy.type == e1000_phy_i217) && !dev_spec->eee_disable) { |
|
822 /* Save off link partner's EEE ability */ |
|
823 ret_val = hw->phy.ops.acquire(hw); |
|
824 if (ret_val) |
|
825 return ret_val; |
|
826 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, |
|
827 I217_EEE_LP_ABILITY); |
|
828 if (ret_val) |
|
829 goto release; |
|
830 e1e_rphy_locked(hw, I82579_EMI_DATA, &dev_spec->eee_lp_ability); |
|
831 |
|
832 /* EEE is not supported in 100Half, so ignore partner's EEE |
|
833 * in 100 ability if full-duplex is not advertised. |
|
834 */ |
|
835 e1e_rphy_locked(hw, PHY_LP_ABILITY, &phy_reg); |
|
836 if (!(phy_reg & NWAY_LPAR_100TX_FD_CAPS)) |
|
837 dev_spec->eee_lp_ability &= ~I217_EEE_100_SUPPORTED; |
|
838 release: |
|
839 hw->phy.ops.release(hw); |
|
840 } |
|
841 |
|
842 return 0; |
|
843 } |
|
844 |
|
845 /** |
|
846 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) |
|
847 * @hw: pointer to the HW structure |
|
848 * |
|
849 * Checks to see of the link status of the hardware has changed. If a |
|
850 * change in link status has been detected, then we read the PHY registers |
|
851 * to get the current speed/duplex if link exists. |
|
852 **/ |
|
853 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) |
|
854 { |
|
855 struct e1000_mac_info *mac = &hw->mac; |
|
856 s32 ret_val; |
|
857 bool link; |
|
858 u16 phy_reg; |
|
859 |
|
860 /* We only want to go out to the PHY registers to see if Auto-Neg |
|
861 * has completed and/or if our link status has changed. The |
|
862 * get_link_status flag is set upon receiving a Link Status |
|
863 * Change or Rx Sequence Error interrupt. |
|
864 */ |
|
865 if (!mac->get_link_status) |
|
866 return 0; |
|
867 |
|
868 /* First we want to see if the MII Status Register reports |
|
869 * link. If so, then we want to get the current speed/duplex |
|
870 * of the PHY. |
|
871 */ |
|
872 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
873 if (ret_val) |
|
874 return ret_val; |
|
875 |
|
876 if (hw->mac.type == e1000_pchlan) { |
|
877 ret_val = e1000_k1_gig_workaround_hv(hw, link); |
|
878 if (ret_val) |
|
879 return ret_val; |
|
880 } |
|
881 |
|
882 /* Clear link partner's EEE ability */ |
|
883 hw->dev_spec.ich8lan.eee_lp_ability = 0; |
|
884 |
|
885 if (!link) |
|
886 return 0; /* No link detected */ |
|
887 |
|
888 mac->get_link_status = false; |
|
889 |
|
890 switch (hw->mac.type) { |
|
891 case e1000_pch2lan: |
|
892 ret_val = e1000_k1_workaround_lv(hw); |
|
893 if (ret_val) |
|
894 return ret_val; |
|
895 /* fall-thru */ |
|
896 case e1000_pchlan: |
|
897 if (hw->phy.type == e1000_phy_82578) { |
|
898 ret_val = e1000_link_stall_workaround_hv(hw); |
|
899 if (ret_val) |
|
900 return ret_val; |
|
901 } |
|
902 |
|
903 /* Workaround for PCHx parts in half-duplex: |
|
904 * Set the number of preambles removed from the packet |
|
905 * when it is passed from the PHY to the MAC to prevent |
|
906 * the MAC from misinterpreting the packet type. |
|
907 */ |
|
908 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); |
|
909 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; |
|
910 |
|
911 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) |
|
912 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); |
|
913 |
|
914 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); |
|
915 break; |
|
916 default: |
|
917 break; |
|
918 } |
|
919 |
|
920 /* Check if there was DownShift, must be checked |
|
921 * immediately after link-up |
|
922 */ |
|
923 e1000e_check_downshift(hw); |
|
924 |
|
925 /* Enable/Disable EEE after link up */ |
|
926 ret_val = e1000_set_eee_pchlan(hw); |
|
927 if (ret_val) |
|
928 return ret_val; |
|
929 |
|
930 /* If we are forcing speed/duplex, then we simply return since |
|
931 * we have already determined whether we have link or not. |
|
932 */ |
|
933 if (!mac->autoneg) |
|
934 return -E1000_ERR_CONFIG; |
|
935 |
|
936 /* Auto-Neg is enabled. Auto Speed Detection takes care |
|
937 * of MAC speed/duplex configuration. So we only need to |
|
938 * configure Collision Distance in the MAC. |
|
939 */ |
|
940 mac->ops.config_collision_dist(hw); |
|
941 |
|
942 /* Configure Flow Control now that Auto-Neg has completed. |
|
943 * First, we need to restore the desired flow control |
|
944 * settings because we may have had to re-autoneg with a |
|
945 * different link partner. |
|
946 */ |
|
947 ret_val = e1000e_config_fc_after_link_up(hw); |
|
948 if (ret_val) |
|
949 e_dbg("Error configuring flow control\n"); |
|
950 |
|
951 return ret_val; |
|
952 } |
|
953 |
|
954 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
|
955 { |
|
956 struct e1000_hw *hw = &adapter->hw; |
|
957 s32 rc; |
|
958 |
|
959 rc = e1000_init_mac_params_ich8lan(hw); |
|
960 if (rc) |
|
961 return rc; |
|
962 |
|
963 rc = e1000_init_nvm_params_ich8lan(hw); |
|
964 if (rc) |
|
965 return rc; |
|
966 |
|
967 switch (hw->mac.type) { |
|
968 case e1000_ich8lan: |
|
969 case e1000_ich9lan: |
|
970 case e1000_ich10lan: |
|
971 rc = e1000_init_phy_params_ich8lan(hw); |
|
972 break; |
|
973 case e1000_pchlan: |
|
974 case e1000_pch2lan: |
|
975 case e1000_pch_lpt: |
|
976 rc = e1000_init_phy_params_pchlan(hw); |
|
977 break; |
|
978 default: |
|
979 break; |
|
980 } |
|
981 if (rc) |
|
982 return rc; |
|
983 |
|
984 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or |
|
985 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). |
|
986 */ |
|
987 if ((adapter->hw.phy.type == e1000_phy_ife) || |
|
988 ((adapter->hw.mac.type >= e1000_pch2lan) && |
|
989 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { |
|
990 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; |
|
991 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; |
|
992 |
|
993 hw->mac.ops.blink_led = NULL; |
|
994 } |
|
995 |
|
996 if ((adapter->hw.mac.type == e1000_ich8lan) && |
|
997 (adapter->hw.phy.type != e1000_phy_ife)) |
|
998 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; |
|
999 |
|
1000 /* Enable workaround for 82579 w/ ME enabled */ |
|
1001 if ((adapter->hw.mac.type == e1000_pch2lan) && |
|
1002 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
|
1003 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; |
|
1004 |
|
1005 /* Disable EEE by default until IEEE802.3az spec is finalized */ |
|
1006 if (adapter->flags2 & FLAG2_HAS_EEE) |
|
1007 adapter->hw.dev_spec.ich8lan.eee_disable = true; |
|
1008 |
|
1009 return 0; |
|
1010 } |
|
1011 |
|
1012 static DEFINE_MUTEX(nvm_mutex); |
|
1013 |
|
1014 /** |
|
1015 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex |
|
1016 * @hw: pointer to the HW structure |
|
1017 * |
|
1018 * Acquires the mutex for performing NVM operations. |
|
1019 **/ |
|
1020 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) |
|
1021 { |
|
1022 mutex_lock(&nvm_mutex); |
|
1023 |
|
1024 return 0; |
|
1025 } |
|
1026 |
|
1027 /** |
|
1028 * e1000_release_nvm_ich8lan - Release NVM mutex |
|
1029 * @hw: pointer to the HW structure |
|
1030 * |
|
1031 * Releases the mutex used while performing NVM operations. |
|
1032 **/ |
|
1033 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) |
|
1034 { |
|
1035 mutex_unlock(&nvm_mutex); |
|
1036 } |
|
1037 |
|
1038 /** |
|
1039 * e1000_acquire_swflag_ich8lan - Acquire software control flag |
|
1040 * @hw: pointer to the HW structure |
|
1041 * |
|
1042 * Acquires the software control flag for performing PHY and select |
|
1043 * MAC CSR accesses. |
|
1044 **/ |
|
1045 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) |
|
1046 { |
|
1047 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; |
|
1048 s32 ret_val = 0; |
|
1049 |
|
1050 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, |
|
1051 &hw->adapter->state)) { |
|
1052 e_dbg("contention for Phy access\n"); |
|
1053 return -E1000_ERR_PHY; |
|
1054 } |
|
1055 |
|
1056 while (timeout) { |
|
1057 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
1058 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) |
|
1059 break; |
|
1060 |
|
1061 mdelay(1); |
|
1062 timeout--; |
|
1063 } |
|
1064 |
|
1065 if (!timeout) { |
|
1066 e_dbg("SW has already locked the resource.\n"); |
|
1067 ret_val = -E1000_ERR_CONFIG; |
|
1068 goto out; |
|
1069 } |
|
1070 |
|
1071 timeout = SW_FLAG_TIMEOUT; |
|
1072 |
|
1073 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
|
1074 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
1075 |
|
1076 while (timeout) { |
|
1077 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
1078 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
|
1079 break; |
|
1080 |
|
1081 mdelay(1); |
|
1082 timeout--; |
|
1083 } |
|
1084 |
|
1085 if (!timeout) { |
|
1086 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", |
|
1087 er32(FWSM), extcnf_ctrl); |
|
1088 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
|
1089 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
1090 ret_val = -E1000_ERR_CONFIG; |
|
1091 goto out; |
|
1092 } |
|
1093 |
|
1094 out: |
|
1095 if (ret_val) |
|
1096 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
|
1097 |
|
1098 return ret_val; |
|
1099 } |
|
1100 |
|
1101 /** |
|
1102 * e1000_release_swflag_ich8lan - Release software control flag |
|
1103 * @hw: pointer to the HW structure |
|
1104 * |
|
1105 * Releases the software control flag for performing PHY and select |
|
1106 * MAC CSR accesses. |
|
1107 **/ |
|
1108 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) |
|
1109 { |
|
1110 u32 extcnf_ctrl; |
|
1111 |
|
1112 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
1113 |
|
1114 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { |
|
1115 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
|
1116 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
1117 } else { |
|
1118 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); |
|
1119 } |
|
1120 |
|
1121 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
|
1122 } |
|
1123 |
|
1124 /** |
|
1125 * e1000_check_mng_mode_ich8lan - Checks management mode |
|
1126 * @hw: pointer to the HW structure |
|
1127 * |
|
1128 * This checks if the adapter has any manageability enabled. |
|
1129 * This is a function pointer entry point only called by read/write |
|
1130 * routines for the PHY and NVM parts. |
|
1131 **/ |
|
1132 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) |
|
1133 { |
|
1134 u32 fwsm; |
|
1135 |
|
1136 fwsm = er32(FWSM); |
|
1137 return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
|
1138 ((fwsm & E1000_FWSM_MODE_MASK) == |
|
1139 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); |
|
1140 } |
|
1141 |
|
1142 /** |
|
1143 * e1000_check_mng_mode_pchlan - Checks management mode |
|
1144 * @hw: pointer to the HW structure |
|
1145 * |
|
1146 * This checks if the adapter has iAMT enabled. |
|
1147 * This is a function pointer entry point only called by read/write |
|
1148 * routines for the PHY and NVM parts. |
|
1149 **/ |
|
1150 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) |
|
1151 { |
|
1152 u32 fwsm; |
|
1153 |
|
1154 fwsm = er32(FWSM); |
|
1155 return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
|
1156 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); |
|
1157 } |
|
1158 |
|
1159 /** |
|
1160 * e1000_rar_set_pch2lan - Set receive address register |
|
1161 * @hw: pointer to the HW structure |
|
1162 * @addr: pointer to the receive address |
|
1163 * @index: receive address array register |
|
1164 * |
|
1165 * Sets the receive address array register at index to the address passed |
|
1166 * in by addr. For 82579, RAR[0] is the base address register that is to |
|
1167 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). |
|
1168 * Use SHRA[0-3] in place of those reserved for ME. |
|
1169 **/ |
|
1170 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) |
|
1171 { |
|
1172 u32 rar_low, rar_high; |
|
1173 |
|
1174 /* HW expects these in little endian so we reverse the byte order |
|
1175 * from network order (big endian) to little endian |
|
1176 */ |
|
1177 rar_low = ((u32)addr[0] | |
|
1178 ((u32)addr[1] << 8) | |
|
1179 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
|
1180 |
|
1181 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
|
1182 |
|
1183 /* If MAC address zero, no need to set the AV bit */ |
|
1184 if (rar_low || rar_high) |
|
1185 rar_high |= E1000_RAH_AV; |
|
1186 |
|
1187 if (index == 0) { |
|
1188 ew32(RAL(index), rar_low); |
|
1189 e1e_flush(); |
|
1190 ew32(RAH(index), rar_high); |
|
1191 e1e_flush(); |
|
1192 return; |
|
1193 } |
|
1194 |
|
1195 if (index < hw->mac.rar_entry_count) { |
|
1196 s32 ret_val; |
|
1197 |
|
1198 ret_val = e1000_acquire_swflag_ich8lan(hw); |
|
1199 if (ret_val) |
|
1200 goto out; |
|
1201 |
|
1202 ew32(SHRAL(index - 1), rar_low); |
|
1203 e1e_flush(); |
|
1204 ew32(SHRAH(index - 1), rar_high); |
|
1205 e1e_flush(); |
|
1206 |
|
1207 e1000_release_swflag_ich8lan(hw); |
|
1208 |
|
1209 /* verify the register updates */ |
|
1210 if ((er32(SHRAL(index - 1)) == rar_low) && |
|
1211 (er32(SHRAH(index - 1)) == rar_high)) |
|
1212 return; |
|
1213 |
|
1214 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", |
|
1215 (index - 1), er32(FWSM)); |
|
1216 } |
|
1217 |
|
1218 out: |
|
1219 e_dbg("Failed to write receive address at index %d\n", index); |
|
1220 } |
|
1221 |
|
1222 /** |
|
1223 * e1000_rar_set_pch_lpt - Set receive address registers |
|
1224 * @hw: pointer to the HW structure |
|
1225 * @addr: pointer to the receive address |
|
1226 * @index: receive address array register |
|
1227 * |
|
1228 * Sets the receive address register array at index to the address passed |
|
1229 * in by addr. For LPT, RAR[0] is the base address register that is to |
|
1230 * contain the MAC address. SHRA[0-10] are the shared receive address |
|
1231 * registers that are shared between the Host and manageability engine (ME). |
|
1232 **/ |
|
1233 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) |
|
1234 { |
|
1235 u32 rar_low, rar_high; |
|
1236 u32 wlock_mac; |
|
1237 |
|
1238 /* HW expects these in little endian so we reverse the byte order |
|
1239 * from network order (big endian) to little endian |
|
1240 */ |
|
1241 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | |
|
1242 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
|
1243 |
|
1244 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
|
1245 |
|
1246 /* If MAC address zero, no need to set the AV bit */ |
|
1247 if (rar_low || rar_high) |
|
1248 rar_high |= E1000_RAH_AV; |
|
1249 |
|
1250 if (index == 0) { |
|
1251 ew32(RAL(index), rar_low); |
|
1252 e1e_flush(); |
|
1253 ew32(RAH(index), rar_high); |
|
1254 e1e_flush(); |
|
1255 return; |
|
1256 } |
|
1257 |
|
1258 /* The manageability engine (ME) can lock certain SHRAR registers that |
|
1259 * it is using - those registers are unavailable for use. |
|
1260 */ |
|
1261 if (index < hw->mac.rar_entry_count) { |
|
1262 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; |
|
1263 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; |
|
1264 |
|
1265 /* Check if all SHRAR registers are locked */ |
|
1266 if (wlock_mac == 1) |
|
1267 goto out; |
|
1268 |
|
1269 if ((wlock_mac == 0) || (index <= wlock_mac)) { |
|
1270 s32 ret_val; |
|
1271 |
|
1272 ret_val = e1000_acquire_swflag_ich8lan(hw); |
|
1273 |
|
1274 if (ret_val) |
|
1275 goto out; |
|
1276 |
|
1277 ew32(SHRAL_PCH_LPT(index - 1), rar_low); |
|
1278 e1e_flush(); |
|
1279 ew32(SHRAH_PCH_LPT(index - 1), rar_high); |
|
1280 e1e_flush(); |
|
1281 |
|
1282 e1000_release_swflag_ich8lan(hw); |
|
1283 |
|
1284 /* verify the register updates */ |
|
1285 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && |
|
1286 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) |
|
1287 return; |
|
1288 } |
|
1289 } |
|
1290 |
|
1291 out: |
|
1292 e_dbg("Failed to write receive address at index %d\n", index); |
|
1293 } |
|
1294 |
|
1295 /** |
|
1296 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked |
|
1297 * @hw: pointer to the HW structure |
|
1298 * |
|
1299 * Checks if firmware is blocking the reset of the PHY. |
|
1300 * This is a function pointer entry point only called by |
|
1301 * reset routines. |
|
1302 **/ |
|
1303 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) |
|
1304 { |
|
1305 u32 fwsm; |
|
1306 |
|
1307 fwsm = er32(FWSM); |
|
1308 |
|
1309 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; |
|
1310 } |
|
1311 |
|
1312 /** |
|
1313 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states |
|
1314 * @hw: pointer to the HW structure |
|
1315 * |
|
1316 * Assumes semaphore already acquired. |
|
1317 * |
|
1318 **/ |
|
1319 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) |
|
1320 { |
|
1321 u16 phy_data; |
|
1322 u32 strap = er32(STRAP); |
|
1323 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> |
|
1324 E1000_STRAP_SMT_FREQ_SHIFT; |
|
1325 s32 ret_val = 0; |
|
1326 |
|
1327 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; |
|
1328 |
|
1329 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); |
|
1330 if (ret_val) |
|
1331 return ret_val; |
|
1332 |
|
1333 phy_data &= ~HV_SMB_ADDR_MASK; |
|
1334 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); |
|
1335 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; |
|
1336 |
|
1337 if (hw->phy.type == e1000_phy_i217) { |
|
1338 /* Restore SMBus frequency */ |
|
1339 if (freq--) { |
|
1340 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; |
|
1341 phy_data |= (freq & (1 << 0)) << |
|
1342 HV_SMB_ADDR_FREQ_LOW_SHIFT; |
|
1343 phy_data |= (freq & (1 << 1)) << |
|
1344 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); |
|
1345 } else { |
|
1346 e_dbg("Unsupported SMB frequency in PHY\n"); |
|
1347 } |
|
1348 } |
|
1349 |
|
1350 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); |
|
1351 } |
|
1352 |
|
1353 /** |
|
1354 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration |
|
1355 * @hw: pointer to the HW structure |
|
1356 * |
|
1357 * SW should configure the LCD from the NVM extended configuration region |
|
1358 * as a workaround for certain parts. |
|
1359 **/ |
|
1360 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) |
|
1361 { |
|
1362 struct e1000_phy_info *phy = &hw->phy; |
|
1363 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; |
|
1364 s32 ret_val = 0; |
|
1365 u16 word_addr, reg_data, reg_addr, phy_page = 0; |
|
1366 |
|
1367 /* Initialize the PHY from the NVM on ICH platforms. This |
|
1368 * is needed due to an issue where the NVM configuration is |
|
1369 * not properly autoloaded after power transitions. |
|
1370 * Therefore, after each PHY reset, we will load the |
|
1371 * configuration data out of the NVM manually. |
|
1372 */ |
|
1373 switch (hw->mac.type) { |
|
1374 case e1000_ich8lan: |
|
1375 if (phy->type != e1000_phy_igp_3) |
|
1376 return ret_val; |
|
1377 |
|
1378 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || |
|
1379 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { |
|
1380 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; |
|
1381 break; |
|
1382 } |
|
1383 /* Fall-thru */ |
|
1384 case e1000_pchlan: |
|
1385 case e1000_pch2lan: |
|
1386 case e1000_pch_lpt: |
|
1387 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; |
|
1388 break; |
|
1389 default: |
|
1390 return ret_val; |
|
1391 } |
|
1392 |
|
1393 ret_val = hw->phy.ops.acquire(hw); |
|
1394 if (ret_val) |
|
1395 return ret_val; |
|
1396 |
|
1397 data = er32(FEXTNVM); |
|
1398 if (!(data & sw_cfg_mask)) |
|
1399 goto release; |
|
1400 |
|
1401 /* Make sure HW does not configure LCD from PHY |
|
1402 * extended configuration before SW configuration |
|
1403 */ |
|
1404 data = er32(EXTCNF_CTRL); |
|
1405 if ((hw->mac.type < e1000_pch2lan) && |
|
1406 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) |
|
1407 goto release; |
|
1408 |
|
1409 cnf_size = er32(EXTCNF_SIZE); |
|
1410 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; |
|
1411 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; |
|
1412 if (!cnf_size) |
|
1413 goto release; |
|
1414 |
|
1415 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; |
|
1416 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; |
|
1417 |
|
1418 if (((hw->mac.type == e1000_pchlan) && |
|
1419 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || |
|
1420 (hw->mac.type > e1000_pchlan)) { |
|
1421 /* HW configures the SMBus address and LEDs when the |
|
1422 * OEM and LCD Write Enable bits are set in the NVM. |
|
1423 * When both NVM bits are cleared, SW will configure |
|
1424 * them instead. |
|
1425 */ |
|
1426 ret_val = e1000_write_smbus_addr(hw); |
|
1427 if (ret_val) |
|
1428 goto release; |
|
1429 |
|
1430 data = er32(LEDCTL); |
|
1431 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, |
|
1432 (u16)data); |
|
1433 if (ret_val) |
|
1434 goto release; |
|
1435 } |
|
1436 |
|
1437 /* Configure LCD from extended configuration region. */ |
|
1438 |
|
1439 /* cnf_base_addr is in DWORD */ |
|
1440 word_addr = (u16)(cnf_base_addr << 1); |
|
1441 |
|
1442 for (i = 0; i < cnf_size; i++) { |
|
1443 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, |
|
1444 ®_data); |
|
1445 if (ret_val) |
|
1446 goto release; |
|
1447 |
|
1448 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), |
|
1449 1, ®_addr); |
|
1450 if (ret_val) |
|
1451 goto release; |
|
1452 |
|
1453 /* Save off the PHY page for future writes. */ |
|
1454 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { |
|
1455 phy_page = reg_data; |
|
1456 continue; |
|
1457 } |
|
1458 |
|
1459 reg_addr &= PHY_REG_MASK; |
|
1460 reg_addr |= phy_page; |
|
1461 |
|
1462 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); |
|
1463 if (ret_val) |
|
1464 goto release; |
|
1465 } |
|
1466 |
|
1467 release: |
|
1468 hw->phy.ops.release(hw); |
|
1469 return ret_val; |
|
1470 } |
|
1471 |
|
1472 /** |
|
1473 * e1000_k1_gig_workaround_hv - K1 Si workaround |
|
1474 * @hw: pointer to the HW structure |
|
1475 * @link: link up bool flag |
|
1476 * |
|
1477 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning |
|
1478 * from a lower speed. This workaround disables K1 whenever link is at 1Gig |
|
1479 * If link is down, the function will restore the default K1 setting located |
|
1480 * in the NVM. |
|
1481 **/ |
|
1482 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) |
|
1483 { |
|
1484 s32 ret_val = 0; |
|
1485 u16 status_reg = 0; |
|
1486 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; |
|
1487 |
|
1488 if (hw->mac.type != e1000_pchlan) |
|
1489 return 0; |
|
1490 |
|
1491 /* Wrap the whole flow with the sw flag */ |
|
1492 ret_val = hw->phy.ops.acquire(hw); |
|
1493 if (ret_val) |
|
1494 return ret_val; |
|
1495 |
|
1496 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ |
|
1497 if (link) { |
|
1498 if (hw->phy.type == e1000_phy_82578) { |
|
1499 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, |
|
1500 &status_reg); |
|
1501 if (ret_val) |
|
1502 goto release; |
|
1503 |
|
1504 status_reg &= BM_CS_STATUS_LINK_UP | |
|
1505 BM_CS_STATUS_RESOLVED | |
|
1506 BM_CS_STATUS_SPEED_MASK; |
|
1507 |
|
1508 if (status_reg == (BM_CS_STATUS_LINK_UP | |
|
1509 BM_CS_STATUS_RESOLVED | |
|
1510 BM_CS_STATUS_SPEED_1000)) |
|
1511 k1_enable = false; |
|
1512 } |
|
1513 |
|
1514 if (hw->phy.type == e1000_phy_82577) { |
|
1515 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); |
|
1516 if (ret_val) |
|
1517 goto release; |
|
1518 |
|
1519 status_reg &= HV_M_STATUS_LINK_UP | |
|
1520 HV_M_STATUS_AUTONEG_COMPLETE | |
|
1521 HV_M_STATUS_SPEED_MASK; |
|
1522 |
|
1523 if (status_reg == (HV_M_STATUS_LINK_UP | |
|
1524 HV_M_STATUS_AUTONEG_COMPLETE | |
|
1525 HV_M_STATUS_SPEED_1000)) |
|
1526 k1_enable = false; |
|
1527 } |
|
1528 |
|
1529 /* Link stall fix for link up */ |
|
1530 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); |
|
1531 if (ret_val) |
|
1532 goto release; |
|
1533 |
|
1534 } else { |
|
1535 /* Link stall fix for link down */ |
|
1536 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); |
|
1537 if (ret_val) |
|
1538 goto release; |
|
1539 } |
|
1540 |
|
1541 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); |
|
1542 |
|
1543 release: |
|
1544 hw->phy.ops.release(hw); |
|
1545 |
|
1546 return ret_val; |
|
1547 } |
|
1548 |
|
1549 /** |
|
1550 * e1000_configure_k1_ich8lan - Configure K1 power state |
|
1551 * @hw: pointer to the HW structure |
|
1552 * @enable: K1 state to configure |
|
1553 * |
|
1554 * Configure the K1 power state based on the provided parameter. |
|
1555 * Assumes semaphore already acquired. |
|
1556 * |
|
1557 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1558 **/ |
|
1559 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) |
|
1560 { |
|
1561 s32 ret_val = 0; |
|
1562 u32 ctrl_reg = 0; |
|
1563 u32 ctrl_ext = 0; |
|
1564 u32 reg = 0; |
|
1565 u16 kmrn_reg = 0; |
|
1566 |
|
1567 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
|
1568 &kmrn_reg); |
|
1569 if (ret_val) |
|
1570 return ret_val; |
|
1571 |
|
1572 if (k1_enable) |
|
1573 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; |
|
1574 else |
|
1575 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; |
|
1576 |
|
1577 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
|
1578 kmrn_reg); |
|
1579 if (ret_val) |
|
1580 return ret_val; |
|
1581 |
|
1582 udelay(20); |
|
1583 ctrl_ext = er32(CTRL_EXT); |
|
1584 ctrl_reg = er32(CTRL); |
|
1585 |
|
1586 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
1587 reg |= E1000_CTRL_FRCSPD; |
|
1588 ew32(CTRL, reg); |
|
1589 |
|
1590 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); |
|
1591 e1e_flush(); |
|
1592 udelay(20); |
|
1593 ew32(CTRL, ctrl_reg); |
|
1594 ew32(CTRL_EXT, ctrl_ext); |
|
1595 e1e_flush(); |
|
1596 udelay(20); |
|
1597 |
|
1598 return 0; |
|
1599 } |
|
1600 |
|
1601 /** |
|
1602 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration |
|
1603 * @hw: pointer to the HW structure |
|
1604 * @d0_state: boolean if entering d0 or d3 device state |
|
1605 * |
|
1606 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are |
|
1607 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit |
|
1608 * in NVM determines whether HW should configure LPLU and Gbe Disable. |
|
1609 **/ |
|
1610 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) |
|
1611 { |
|
1612 s32 ret_val = 0; |
|
1613 u32 mac_reg; |
|
1614 u16 oem_reg; |
|
1615 |
|
1616 if (hw->mac.type < e1000_pchlan) |
|
1617 return ret_val; |
|
1618 |
|
1619 ret_val = hw->phy.ops.acquire(hw); |
|
1620 if (ret_val) |
|
1621 return ret_val; |
|
1622 |
|
1623 if (hw->mac.type == e1000_pchlan) { |
|
1624 mac_reg = er32(EXTCNF_CTRL); |
|
1625 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) |
|
1626 goto release; |
|
1627 } |
|
1628 |
|
1629 mac_reg = er32(FEXTNVM); |
|
1630 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) |
|
1631 goto release; |
|
1632 |
|
1633 mac_reg = er32(PHY_CTRL); |
|
1634 |
|
1635 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); |
|
1636 if (ret_val) |
|
1637 goto release; |
|
1638 |
|
1639 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); |
|
1640 |
|
1641 if (d0_state) { |
|
1642 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) |
|
1643 oem_reg |= HV_OEM_BITS_GBE_DIS; |
|
1644 |
|
1645 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) |
|
1646 oem_reg |= HV_OEM_BITS_LPLU; |
|
1647 } else { |
|
1648 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | |
|
1649 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) |
|
1650 oem_reg |= HV_OEM_BITS_GBE_DIS; |
|
1651 |
|
1652 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | |
|
1653 E1000_PHY_CTRL_NOND0A_LPLU)) |
|
1654 oem_reg |= HV_OEM_BITS_LPLU; |
|
1655 } |
|
1656 |
|
1657 /* Set Restart auto-neg to activate the bits */ |
|
1658 if ((d0_state || (hw->mac.type != e1000_pchlan)) && |
|
1659 !hw->phy.ops.check_reset_block(hw)) |
|
1660 oem_reg |= HV_OEM_BITS_RESTART_AN; |
|
1661 |
|
1662 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); |
|
1663 |
|
1664 release: |
|
1665 hw->phy.ops.release(hw); |
|
1666 |
|
1667 return ret_val; |
|
1668 } |
|
1669 |
|
1670 |
|
1671 /** |
|
1672 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode |
|
1673 * @hw: pointer to the HW structure |
|
1674 **/ |
|
1675 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) |
|
1676 { |
|
1677 s32 ret_val; |
|
1678 u16 data; |
|
1679 |
|
1680 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); |
|
1681 if (ret_val) |
|
1682 return ret_val; |
|
1683 |
|
1684 data |= HV_KMRN_MDIO_SLOW; |
|
1685 |
|
1686 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); |
|
1687 |
|
1688 return ret_val; |
|
1689 } |
|
1690 |
|
1691 /** |
|
1692 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be |
|
1693 * done after every PHY reset. |
|
1694 **/ |
|
1695 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) |
|
1696 { |
|
1697 s32 ret_val = 0; |
|
1698 u16 phy_data; |
|
1699 |
|
1700 if (hw->mac.type != e1000_pchlan) |
|
1701 return 0; |
|
1702 |
|
1703 /* Set MDIO slow mode before any other MDIO access */ |
|
1704 if (hw->phy.type == e1000_phy_82577) { |
|
1705 ret_val = e1000_set_mdio_slow_mode_hv(hw); |
|
1706 if (ret_val) |
|
1707 return ret_val; |
|
1708 } |
|
1709 |
|
1710 if (((hw->phy.type == e1000_phy_82577) && |
|
1711 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || |
|
1712 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { |
|
1713 /* Disable generation of early preamble */ |
|
1714 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); |
|
1715 if (ret_val) |
|
1716 return ret_val; |
|
1717 |
|
1718 /* Preamble tuning for SSC */ |
|
1719 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); |
|
1720 if (ret_val) |
|
1721 return ret_val; |
|
1722 } |
|
1723 |
|
1724 if (hw->phy.type == e1000_phy_82578) { |
|
1725 /* Return registers to default by doing a soft reset then |
|
1726 * writing 0x3140 to the control register. |
|
1727 */ |
|
1728 if (hw->phy.revision < 2) { |
|
1729 e1000e_phy_sw_reset(hw); |
|
1730 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); |
|
1731 } |
|
1732 } |
|
1733 |
|
1734 /* Select page 0 */ |
|
1735 ret_val = hw->phy.ops.acquire(hw); |
|
1736 if (ret_val) |
|
1737 return ret_val; |
|
1738 |
|
1739 hw->phy.addr = 1; |
|
1740 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); |
|
1741 hw->phy.ops.release(hw); |
|
1742 if (ret_val) |
|
1743 return ret_val; |
|
1744 |
|
1745 /* Configure the K1 Si workaround during phy reset assuming there is |
|
1746 * link so that it disables K1 if link is in 1Gbps. |
|
1747 */ |
|
1748 ret_val = e1000_k1_gig_workaround_hv(hw, true); |
|
1749 if (ret_val) |
|
1750 return ret_val; |
|
1751 |
|
1752 /* Workaround for link disconnects on a busy hub in half duplex */ |
|
1753 ret_val = hw->phy.ops.acquire(hw); |
|
1754 if (ret_val) |
|
1755 return ret_val; |
|
1756 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); |
|
1757 if (ret_val) |
|
1758 goto release; |
|
1759 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); |
|
1760 release: |
|
1761 hw->phy.ops.release(hw); |
|
1762 |
|
1763 return ret_val; |
|
1764 } |
|
1765 |
|
1766 /** |
|
1767 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY |
|
1768 * @hw: pointer to the HW structure |
|
1769 **/ |
|
1770 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) |
|
1771 { |
|
1772 u32 mac_reg; |
|
1773 u16 i, phy_reg = 0; |
|
1774 s32 ret_val; |
|
1775 |
|
1776 ret_val = hw->phy.ops.acquire(hw); |
|
1777 if (ret_val) |
|
1778 return; |
|
1779 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
|
1780 if (ret_val) |
|
1781 goto release; |
|
1782 |
|
1783 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ |
|
1784 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { |
|
1785 mac_reg = er32(RAL(i)); |
|
1786 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), |
|
1787 (u16)(mac_reg & 0xFFFF)); |
|
1788 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), |
|
1789 (u16)((mac_reg >> 16) & 0xFFFF)); |
|
1790 |
|
1791 mac_reg = er32(RAH(i)); |
|
1792 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), |
|
1793 (u16)(mac_reg & 0xFFFF)); |
|
1794 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), |
|
1795 (u16)((mac_reg & E1000_RAH_AV) |
|
1796 >> 16)); |
|
1797 } |
|
1798 |
|
1799 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
|
1800 |
|
1801 release: |
|
1802 hw->phy.ops.release(hw); |
|
1803 } |
|
1804 |
|
1805 /** |
|
1806 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation |
|
1807 * with 82579 PHY |
|
1808 * @hw: pointer to the HW structure |
|
1809 * @enable: flag to enable/disable workaround when enabling/disabling jumbos |
|
1810 **/ |
|
1811 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) |
|
1812 { |
|
1813 s32 ret_val = 0; |
|
1814 u16 phy_reg, data; |
|
1815 u32 mac_reg; |
|
1816 u16 i; |
|
1817 |
|
1818 if (hw->mac.type < e1000_pch2lan) |
|
1819 return 0; |
|
1820 |
|
1821 /* disable Rx path while enabling/disabling workaround */ |
|
1822 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); |
|
1823 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); |
|
1824 if (ret_val) |
|
1825 return ret_val; |
|
1826 |
|
1827 if (enable) { |
|
1828 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for |
|
1829 * SHRAL/H) and initial CRC values to the MAC |
|
1830 */ |
|
1831 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { |
|
1832 u8 mac_addr[ETH_ALEN] = {0}; |
|
1833 u32 addr_high, addr_low; |
|
1834 |
|
1835 addr_high = er32(RAH(i)); |
|
1836 if (!(addr_high & E1000_RAH_AV)) |
|
1837 continue; |
|
1838 addr_low = er32(RAL(i)); |
|
1839 mac_addr[0] = (addr_low & 0xFF); |
|
1840 mac_addr[1] = ((addr_low >> 8) & 0xFF); |
|
1841 mac_addr[2] = ((addr_low >> 16) & 0xFF); |
|
1842 mac_addr[3] = ((addr_low >> 24) & 0xFF); |
|
1843 mac_addr[4] = (addr_high & 0xFF); |
|
1844 mac_addr[5] = ((addr_high >> 8) & 0xFF); |
|
1845 |
|
1846 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); |
|
1847 } |
|
1848 |
|
1849 /* Write Rx addresses to the PHY */ |
|
1850 e1000_copy_rx_addrs_to_phy_ich8lan(hw); |
|
1851 |
|
1852 /* Enable jumbo frame workaround in the MAC */ |
|
1853 mac_reg = er32(FFLT_DBG); |
|
1854 mac_reg &= ~(1 << 14); |
|
1855 mac_reg |= (7 << 15); |
|
1856 ew32(FFLT_DBG, mac_reg); |
|
1857 |
|
1858 mac_reg = er32(RCTL); |
|
1859 mac_reg |= E1000_RCTL_SECRC; |
|
1860 ew32(RCTL, mac_reg); |
|
1861 |
|
1862 ret_val = e1000e_read_kmrn_reg(hw, |
|
1863 E1000_KMRNCTRLSTA_CTRL_OFFSET, |
|
1864 &data); |
|
1865 if (ret_val) |
|
1866 return ret_val; |
|
1867 ret_val = e1000e_write_kmrn_reg(hw, |
|
1868 E1000_KMRNCTRLSTA_CTRL_OFFSET, |
|
1869 data | (1 << 0)); |
|
1870 if (ret_val) |
|
1871 return ret_val; |
|
1872 ret_val = e1000e_read_kmrn_reg(hw, |
|
1873 E1000_KMRNCTRLSTA_HD_CTRL, |
|
1874 &data); |
|
1875 if (ret_val) |
|
1876 return ret_val; |
|
1877 data &= ~(0xF << 8); |
|
1878 data |= (0xB << 8); |
|
1879 ret_val = e1000e_write_kmrn_reg(hw, |
|
1880 E1000_KMRNCTRLSTA_HD_CTRL, |
|
1881 data); |
|
1882 if (ret_val) |
|
1883 return ret_val; |
|
1884 |
|
1885 /* Enable jumbo frame workaround in the PHY */ |
|
1886 e1e_rphy(hw, PHY_REG(769, 23), &data); |
|
1887 data &= ~(0x7F << 5); |
|
1888 data |= (0x37 << 5); |
|
1889 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
|
1890 if (ret_val) |
|
1891 return ret_val; |
|
1892 e1e_rphy(hw, PHY_REG(769, 16), &data); |
|
1893 data &= ~(1 << 13); |
|
1894 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
|
1895 if (ret_val) |
|
1896 return ret_val; |
|
1897 e1e_rphy(hw, PHY_REG(776, 20), &data); |
|
1898 data &= ~(0x3FF << 2); |
|
1899 data |= (0x1A << 2); |
|
1900 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
|
1901 if (ret_val) |
|
1902 return ret_val; |
|
1903 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); |
|
1904 if (ret_val) |
|
1905 return ret_val; |
|
1906 e1e_rphy(hw, HV_PM_CTRL, &data); |
|
1907 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); |
|
1908 if (ret_val) |
|
1909 return ret_val; |
|
1910 } else { |
|
1911 /* Write MAC register values back to h/w defaults */ |
|
1912 mac_reg = er32(FFLT_DBG); |
|
1913 mac_reg &= ~(0xF << 14); |
|
1914 ew32(FFLT_DBG, mac_reg); |
|
1915 |
|
1916 mac_reg = er32(RCTL); |
|
1917 mac_reg &= ~E1000_RCTL_SECRC; |
|
1918 ew32(RCTL, mac_reg); |
|
1919 |
|
1920 ret_val = e1000e_read_kmrn_reg(hw, |
|
1921 E1000_KMRNCTRLSTA_CTRL_OFFSET, |
|
1922 &data); |
|
1923 if (ret_val) |
|
1924 return ret_val; |
|
1925 ret_val = e1000e_write_kmrn_reg(hw, |
|
1926 E1000_KMRNCTRLSTA_CTRL_OFFSET, |
|
1927 data & ~(1 << 0)); |
|
1928 if (ret_val) |
|
1929 return ret_val; |
|
1930 ret_val = e1000e_read_kmrn_reg(hw, |
|
1931 E1000_KMRNCTRLSTA_HD_CTRL, |
|
1932 &data); |
|
1933 if (ret_val) |
|
1934 return ret_val; |
|
1935 data &= ~(0xF << 8); |
|
1936 data |= (0xB << 8); |
|
1937 ret_val = e1000e_write_kmrn_reg(hw, |
|
1938 E1000_KMRNCTRLSTA_HD_CTRL, |
|
1939 data); |
|
1940 if (ret_val) |
|
1941 return ret_val; |
|
1942 |
|
1943 /* Write PHY register values back to h/w defaults */ |
|
1944 e1e_rphy(hw, PHY_REG(769, 23), &data); |
|
1945 data &= ~(0x7F << 5); |
|
1946 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
|
1947 if (ret_val) |
|
1948 return ret_val; |
|
1949 e1e_rphy(hw, PHY_REG(769, 16), &data); |
|
1950 data |= (1 << 13); |
|
1951 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
|
1952 if (ret_val) |
|
1953 return ret_val; |
|
1954 e1e_rphy(hw, PHY_REG(776, 20), &data); |
|
1955 data &= ~(0x3FF << 2); |
|
1956 data |= (0x8 << 2); |
|
1957 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
|
1958 if (ret_val) |
|
1959 return ret_val; |
|
1960 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); |
|
1961 if (ret_val) |
|
1962 return ret_val; |
|
1963 e1e_rphy(hw, HV_PM_CTRL, &data); |
|
1964 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); |
|
1965 if (ret_val) |
|
1966 return ret_val; |
|
1967 } |
|
1968 |
|
1969 /* re-enable Rx path after enabling/disabling workaround */ |
|
1970 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); |
|
1971 } |
|
1972 |
|
1973 /** |
|
1974 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be |
|
1975 * done after every PHY reset. |
|
1976 **/ |
|
1977 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) |
|
1978 { |
|
1979 s32 ret_val = 0; |
|
1980 |
|
1981 if (hw->mac.type != e1000_pch2lan) |
|
1982 return 0; |
|
1983 |
|
1984 /* Set MDIO slow mode before any other MDIO access */ |
|
1985 ret_val = e1000_set_mdio_slow_mode_hv(hw); |
|
1986 |
|
1987 ret_val = hw->phy.ops.acquire(hw); |
|
1988 if (ret_val) |
|
1989 return ret_val; |
|
1990 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, I82579_MSE_THRESHOLD); |
|
1991 if (ret_val) |
|
1992 goto release; |
|
1993 /* set MSE higher to enable link to stay up when noise is high */ |
|
1994 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x0034); |
|
1995 if (ret_val) |
|
1996 goto release; |
|
1997 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, I82579_MSE_LINK_DOWN); |
|
1998 if (ret_val) |
|
1999 goto release; |
|
2000 /* drop link after 5 times MSE threshold was reached */ |
|
2001 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x0005); |
|
2002 release: |
|
2003 hw->phy.ops.release(hw); |
|
2004 |
|
2005 return ret_val; |
|
2006 } |
|
2007 |
|
2008 /** |
|
2009 * e1000_k1_gig_workaround_lv - K1 Si workaround |
|
2010 * @hw: pointer to the HW structure |
|
2011 * |
|
2012 * Workaround to set the K1 beacon duration for 82579 parts |
|
2013 **/ |
|
2014 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) |
|
2015 { |
|
2016 s32 ret_val = 0; |
|
2017 u16 status_reg = 0; |
|
2018 u32 mac_reg; |
|
2019 u16 phy_reg; |
|
2020 |
|
2021 if (hw->mac.type != e1000_pch2lan) |
|
2022 return 0; |
|
2023 |
|
2024 /* Set K1 beacon duration based on 1Gbps speed or otherwise */ |
|
2025 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); |
|
2026 if (ret_val) |
|
2027 return ret_val; |
|
2028 |
|
2029 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) |
|
2030 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { |
|
2031 mac_reg = er32(FEXTNVM4); |
|
2032 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; |
|
2033 |
|
2034 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
|
2035 if (ret_val) |
|
2036 return ret_val; |
|
2037 |
|
2038 if (status_reg & HV_M_STATUS_SPEED_1000) { |
|
2039 u16 pm_phy_reg; |
|
2040 |
|
2041 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; |
|
2042 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; |
|
2043 /* LV 1G Packet drop issue wa */ |
|
2044 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); |
|
2045 if (ret_val) |
|
2046 return ret_val; |
|
2047 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; |
|
2048 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); |
|
2049 if (ret_val) |
|
2050 return ret_val; |
|
2051 } else { |
|
2052 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; |
|
2053 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; |
|
2054 } |
|
2055 ew32(FEXTNVM4, mac_reg); |
|
2056 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
|
2057 } |
|
2058 |
|
2059 return ret_val; |
|
2060 } |
|
2061 |
|
2062 /** |
|
2063 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware |
|
2064 * @hw: pointer to the HW structure |
|
2065 * @gate: boolean set to true to gate, false to ungate |
|
2066 * |
|
2067 * Gate/ungate the automatic PHY configuration via hardware; perform |
|
2068 * the configuration via software instead. |
|
2069 **/ |
|
2070 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) |
|
2071 { |
|
2072 u32 extcnf_ctrl; |
|
2073 |
|
2074 if (hw->mac.type < e1000_pch2lan) |
|
2075 return; |
|
2076 |
|
2077 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
2078 |
|
2079 if (gate) |
|
2080 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; |
|
2081 else |
|
2082 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; |
|
2083 |
|
2084 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
2085 } |
|
2086 |
|
2087 /** |
|
2088 * e1000_lan_init_done_ich8lan - Check for PHY config completion |
|
2089 * @hw: pointer to the HW structure |
|
2090 * |
|
2091 * Check the appropriate indication the MAC has finished configuring the |
|
2092 * PHY after a software reset. |
|
2093 **/ |
|
2094 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) |
|
2095 { |
|
2096 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; |
|
2097 |
|
2098 /* Wait for basic configuration completes before proceeding */ |
|
2099 do { |
|
2100 data = er32(STATUS); |
|
2101 data &= E1000_STATUS_LAN_INIT_DONE; |
|
2102 udelay(100); |
|
2103 } while ((!data) && --loop); |
|
2104 |
|
2105 /* If basic configuration is incomplete before the above loop |
|
2106 * count reaches 0, loading the configuration from NVM will |
|
2107 * leave the PHY in a bad state possibly resulting in no link. |
|
2108 */ |
|
2109 if (loop == 0) |
|
2110 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); |
|
2111 |
|
2112 /* Clear the Init Done bit for the next init event */ |
|
2113 data = er32(STATUS); |
|
2114 data &= ~E1000_STATUS_LAN_INIT_DONE; |
|
2115 ew32(STATUS, data); |
|
2116 } |
|
2117 |
|
2118 /** |
|
2119 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset |
|
2120 * @hw: pointer to the HW structure |
|
2121 **/ |
|
2122 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) |
|
2123 { |
|
2124 s32 ret_val = 0; |
|
2125 u16 reg; |
|
2126 |
|
2127 if (hw->phy.ops.check_reset_block(hw)) |
|
2128 return 0; |
|
2129 |
|
2130 /* Allow time for h/w to get to quiescent state after reset */ |
|
2131 usleep_range(10000, 20000); |
|
2132 |
|
2133 /* Perform any necessary post-reset workarounds */ |
|
2134 switch (hw->mac.type) { |
|
2135 case e1000_pchlan: |
|
2136 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); |
|
2137 if (ret_val) |
|
2138 return ret_val; |
|
2139 break; |
|
2140 case e1000_pch2lan: |
|
2141 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); |
|
2142 if (ret_val) |
|
2143 return ret_val; |
|
2144 break; |
|
2145 default: |
|
2146 break; |
|
2147 } |
|
2148 |
|
2149 /* Clear the host wakeup bit after lcd reset */ |
|
2150 if (hw->mac.type >= e1000_pchlan) { |
|
2151 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); |
|
2152 reg &= ~BM_WUC_HOST_WU_BIT; |
|
2153 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); |
|
2154 } |
|
2155 |
|
2156 /* Configure the LCD with the extended configuration region in NVM */ |
|
2157 ret_val = e1000_sw_lcd_config_ich8lan(hw); |
|
2158 if (ret_val) |
|
2159 return ret_val; |
|
2160 |
|
2161 /* Configure the LCD with the OEM bits in NVM */ |
|
2162 ret_val = e1000_oem_bits_config_ich8lan(hw, true); |
|
2163 |
|
2164 if (hw->mac.type == e1000_pch2lan) { |
|
2165 /* Ungate automatic PHY configuration on non-managed 82579 */ |
|
2166 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
|
2167 usleep_range(10000, 20000); |
|
2168 e1000_gate_hw_phy_config_ich8lan(hw, false); |
|
2169 } |
|
2170 |
|
2171 /* Set EEE LPI Update Timer to 200usec */ |
|
2172 ret_val = hw->phy.ops.acquire(hw); |
|
2173 if (ret_val) |
|
2174 return ret_val; |
|
2175 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, |
|
2176 I82579_LPI_UPDATE_TIMER); |
|
2177 if (!ret_val) |
|
2178 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x1387); |
|
2179 hw->phy.ops.release(hw); |
|
2180 } |
|
2181 |
|
2182 return ret_val; |
|
2183 } |
|
2184 |
|
2185 /** |
|
2186 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset |
|
2187 * @hw: pointer to the HW structure |
|
2188 * |
|
2189 * Resets the PHY |
|
2190 * This is a function pointer entry point called by drivers |
|
2191 * or other shared routines. |
|
2192 **/ |
|
2193 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) |
|
2194 { |
|
2195 s32 ret_val = 0; |
|
2196 |
|
2197 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ |
|
2198 if ((hw->mac.type == e1000_pch2lan) && |
|
2199 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
|
2200 e1000_gate_hw_phy_config_ich8lan(hw, true); |
|
2201 |
|
2202 ret_val = e1000e_phy_hw_reset_generic(hw); |
|
2203 if (ret_val) |
|
2204 return ret_val; |
|
2205 |
|
2206 return e1000_post_phy_reset_ich8lan(hw); |
|
2207 } |
|
2208 |
|
2209 /** |
|
2210 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state |
|
2211 * @hw: pointer to the HW structure |
|
2212 * @active: true to enable LPLU, false to disable |
|
2213 * |
|
2214 * Sets the LPLU state according to the active flag. For PCH, if OEM write |
|
2215 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set |
|
2216 * the phy speed. This function will manually set the LPLU bit and restart |
|
2217 * auto-neg as hw would do. D3 and D0 LPLU will call the same function |
|
2218 * since it configures the same bit. |
|
2219 **/ |
|
2220 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) |
|
2221 { |
|
2222 s32 ret_val = 0; |
|
2223 u16 oem_reg; |
|
2224 |
|
2225 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); |
|
2226 if (ret_val) |
|
2227 return ret_val; |
|
2228 |
|
2229 if (active) |
|
2230 oem_reg |= HV_OEM_BITS_LPLU; |
|
2231 else |
|
2232 oem_reg &= ~HV_OEM_BITS_LPLU; |
|
2233 |
|
2234 if (!hw->phy.ops.check_reset_block(hw)) |
|
2235 oem_reg |= HV_OEM_BITS_RESTART_AN; |
|
2236 |
|
2237 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); |
|
2238 } |
|
2239 |
|
2240 /** |
|
2241 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state |
|
2242 * @hw: pointer to the HW structure |
|
2243 * @active: true to enable LPLU, false to disable |
|
2244 * |
|
2245 * Sets the LPLU D0 state according to the active flag. When |
|
2246 * activating LPLU this function also disables smart speed |
|
2247 * and vice versa. LPLU will not be activated unless the |
|
2248 * device autonegotiation advertisement meets standards of |
|
2249 * either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
2250 * This is a function pointer entry point only called by |
|
2251 * PHY setup routines. |
|
2252 **/ |
|
2253 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) |
|
2254 { |
|
2255 struct e1000_phy_info *phy = &hw->phy; |
|
2256 u32 phy_ctrl; |
|
2257 s32 ret_val = 0; |
|
2258 u16 data; |
|
2259 |
|
2260 if (phy->type == e1000_phy_ife) |
|
2261 return 0; |
|
2262 |
|
2263 phy_ctrl = er32(PHY_CTRL); |
|
2264 |
|
2265 if (active) { |
|
2266 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
|
2267 ew32(PHY_CTRL, phy_ctrl); |
|
2268 |
|
2269 if (phy->type != e1000_phy_igp_3) |
|
2270 return 0; |
|
2271 |
|
2272 /* Call gig speed drop workaround on LPLU before accessing |
|
2273 * any PHY registers |
|
2274 */ |
|
2275 if (hw->mac.type == e1000_ich8lan) |
|
2276 e1000e_gig_downshift_workaround_ich8lan(hw); |
|
2277 |
|
2278 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
2279 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
2280 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
2281 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
2282 if (ret_val) |
|
2283 return ret_val; |
|
2284 } else { |
|
2285 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
|
2286 ew32(PHY_CTRL, phy_ctrl); |
|
2287 |
|
2288 if (phy->type != e1000_phy_igp_3) |
|
2289 return 0; |
|
2290 |
|
2291 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
2292 * during Dx states where the power conservation is most |
|
2293 * important. During driver activity we should enable |
|
2294 * SmartSpeed, so performance is maintained. |
|
2295 */ |
|
2296 if (phy->smart_speed == e1000_smart_speed_on) { |
|
2297 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2298 &data); |
|
2299 if (ret_val) |
|
2300 return ret_val; |
|
2301 |
|
2302 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
2303 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2304 data); |
|
2305 if (ret_val) |
|
2306 return ret_val; |
|
2307 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
2308 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2309 &data); |
|
2310 if (ret_val) |
|
2311 return ret_val; |
|
2312 |
|
2313 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
2314 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2315 data); |
|
2316 if (ret_val) |
|
2317 return ret_val; |
|
2318 } |
|
2319 } |
|
2320 |
|
2321 return 0; |
|
2322 } |
|
2323 |
|
2324 /** |
|
2325 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state |
|
2326 * @hw: pointer to the HW structure |
|
2327 * @active: true to enable LPLU, false to disable |
|
2328 * |
|
2329 * Sets the LPLU D3 state according to the active flag. When |
|
2330 * activating LPLU this function also disables smart speed |
|
2331 * and vice versa. LPLU will not be activated unless the |
|
2332 * device autonegotiation advertisement meets standards of |
|
2333 * either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
2334 * This is a function pointer entry point only called by |
|
2335 * PHY setup routines. |
|
2336 **/ |
|
2337 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) |
|
2338 { |
|
2339 struct e1000_phy_info *phy = &hw->phy; |
|
2340 u32 phy_ctrl; |
|
2341 s32 ret_val = 0; |
|
2342 u16 data; |
|
2343 |
|
2344 phy_ctrl = er32(PHY_CTRL); |
|
2345 |
|
2346 if (!active) { |
|
2347 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
|
2348 ew32(PHY_CTRL, phy_ctrl); |
|
2349 |
|
2350 if (phy->type != e1000_phy_igp_3) |
|
2351 return 0; |
|
2352 |
|
2353 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
2354 * during Dx states where the power conservation is most |
|
2355 * important. During driver activity we should enable |
|
2356 * SmartSpeed, so performance is maintained. |
|
2357 */ |
|
2358 if (phy->smart_speed == e1000_smart_speed_on) { |
|
2359 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2360 &data); |
|
2361 if (ret_val) |
|
2362 return ret_val; |
|
2363 |
|
2364 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
2365 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2366 data); |
|
2367 if (ret_val) |
|
2368 return ret_val; |
|
2369 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
2370 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2371 &data); |
|
2372 if (ret_val) |
|
2373 return ret_val; |
|
2374 |
|
2375 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
2376 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
2377 data); |
|
2378 if (ret_val) |
|
2379 return ret_val; |
|
2380 } |
|
2381 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
|
2382 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
|
2383 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
|
2384 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
|
2385 ew32(PHY_CTRL, phy_ctrl); |
|
2386 |
|
2387 if (phy->type != e1000_phy_igp_3) |
|
2388 return 0; |
|
2389 |
|
2390 /* Call gig speed drop workaround on LPLU before accessing |
|
2391 * any PHY registers |
|
2392 */ |
|
2393 if (hw->mac.type == e1000_ich8lan) |
|
2394 e1000e_gig_downshift_workaround_ich8lan(hw); |
|
2395 |
|
2396 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
2397 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
2398 if (ret_val) |
|
2399 return ret_val; |
|
2400 |
|
2401 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
2402 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
2403 } |
|
2404 |
|
2405 return ret_val; |
|
2406 } |
|
2407 |
|
2408 /** |
|
2409 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 |
|
2410 * @hw: pointer to the HW structure |
|
2411 * @bank: pointer to the variable that returns the active bank |
|
2412 * |
|
2413 * Reads signature byte from the NVM using the flash access registers. |
|
2414 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. |
|
2415 **/ |
|
2416 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) |
|
2417 { |
|
2418 u32 eecd; |
|
2419 struct e1000_nvm_info *nvm = &hw->nvm; |
|
2420 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); |
|
2421 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; |
|
2422 u8 sig_byte = 0; |
|
2423 s32 ret_val; |
|
2424 |
|
2425 switch (hw->mac.type) { |
|
2426 case e1000_ich8lan: |
|
2427 case e1000_ich9lan: |
|
2428 eecd = er32(EECD); |
|
2429 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == |
|
2430 E1000_EECD_SEC1VAL_VALID_MASK) { |
|
2431 if (eecd & E1000_EECD_SEC1VAL) |
|
2432 *bank = 1; |
|
2433 else |
|
2434 *bank = 0; |
|
2435 |
|
2436 return 0; |
|
2437 } |
|
2438 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); |
|
2439 /* fall-thru */ |
|
2440 default: |
|
2441 /* set bank to 0 in case flash read fails */ |
|
2442 *bank = 0; |
|
2443 |
|
2444 /* Check bank 0 */ |
|
2445 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, |
|
2446 &sig_byte); |
|
2447 if (ret_val) |
|
2448 return ret_val; |
|
2449 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
|
2450 E1000_ICH_NVM_SIG_VALUE) { |
|
2451 *bank = 0; |
|
2452 return 0; |
|
2453 } |
|
2454 |
|
2455 /* Check bank 1 */ |
|
2456 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + |
|
2457 bank1_offset, |
|
2458 &sig_byte); |
|
2459 if (ret_val) |
|
2460 return ret_val; |
|
2461 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
|
2462 E1000_ICH_NVM_SIG_VALUE) { |
|
2463 *bank = 1; |
|
2464 return 0; |
|
2465 } |
|
2466 |
|
2467 e_dbg("ERROR: No valid NVM bank present\n"); |
|
2468 return -E1000_ERR_NVM; |
|
2469 } |
|
2470 } |
|
2471 |
|
2472 /** |
|
2473 * e1000_read_nvm_ich8lan - Read word(s) from the NVM |
|
2474 * @hw: pointer to the HW structure |
|
2475 * @offset: The offset (in bytes) of the word(s) to read. |
|
2476 * @words: Size of data to read in words |
|
2477 * @data: Pointer to the word(s) to read at offset. |
|
2478 * |
|
2479 * Reads a word(s) from the NVM using the flash access registers. |
|
2480 **/ |
|
2481 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, |
|
2482 u16 *data) |
|
2483 { |
|
2484 struct e1000_nvm_info *nvm = &hw->nvm; |
|
2485 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
2486 u32 act_offset; |
|
2487 s32 ret_val = 0; |
|
2488 u32 bank = 0; |
|
2489 u16 i, word; |
|
2490 |
|
2491 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
|
2492 (words == 0)) { |
|
2493 e_dbg("nvm parameter(s) out of bounds\n"); |
|
2494 ret_val = -E1000_ERR_NVM; |
|
2495 goto out; |
|
2496 } |
|
2497 |
|
2498 nvm->ops.acquire(hw); |
|
2499 |
|
2500 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
|
2501 if (ret_val) { |
|
2502 e_dbg("Could not detect valid bank, assuming bank 0\n"); |
|
2503 bank = 0; |
|
2504 } |
|
2505 |
|
2506 act_offset = (bank) ? nvm->flash_bank_size : 0; |
|
2507 act_offset += offset; |
|
2508 |
|
2509 ret_val = 0; |
|
2510 for (i = 0; i < words; i++) { |
|
2511 if (dev_spec->shadow_ram[offset+i].modified) { |
|
2512 data[i] = dev_spec->shadow_ram[offset+i].value; |
|
2513 } else { |
|
2514 ret_val = e1000_read_flash_word_ich8lan(hw, |
|
2515 act_offset + i, |
|
2516 &word); |
|
2517 if (ret_val) |
|
2518 break; |
|
2519 data[i] = word; |
|
2520 } |
|
2521 } |
|
2522 |
|
2523 nvm->ops.release(hw); |
|
2524 |
|
2525 out: |
|
2526 if (ret_val) |
|
2527 e_dbg("NVM read error: %d\n", ret_val); |
|
2528 |
|
2529 return ret_val; |
|
2530 } |
|
2531 |
|
2532 /** |
|
2533 * e1000_flash_cycle_init_ich8lan - Initialize flash |
|
2534 * @hw: pointer to the HW structure |
|
2535 * |
|
2536 * This function does initial flash setup so that a new read/write/erase cycle |
|
2537 * can be started. |
|
2538 **/ |
|
2539 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) |
|
2540 { |
|
2541 union ich8_hws_flash_status hsfsts; |
|
2542 s32 ret_val = -E1000_ERR_NVM; |
|
2543 |
|
2544 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
2545 |
|
2546 /* Check if the flash descriptor is valid */ |
|
2547 if (!hsfsts.hsf_status.fldesvalid) { |
|
2548 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); |
|
2549 return -E1000_ERR_NVM; |
|
2550 } |
|
2551 |
|
2552 /* Clear FCERR and DAEL in hw status by writing 1 */ |
|
2553 hsfsts.hsf_status.flcerr = 1; |
|
2554 hsfsts.hsf_status.dael = 1; |
|
2555 |
|
2556 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
|
2557 |
|
2558 /* Either we should have a hardware SPI cycle in progress |
|
2559 * bit to check against, in order to start a new cycle or |
|
2560 * FDONE bit should be changed in the hardware so that it |
|
2561 * is 1 after hardware reset, which can then be used as an |
|
2562 * indication whether a cycle is in progress or has been |
|
2563 * completed. |
|
2564 */ |
|
2565 |
|
2566 if (!hsfsts.hsf_status.flcinprog) { |
|
2567 /* There is no cycle running at present, |
|
2568 * so we can start a cycle. |
|
2569 * Begin by setting Flash Cycle Done. |
|
2570 */ |
|
2571 hsfsts.hsf_status.flcdone = 1; |
|
2572 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
|
2573 ret_val = 0; |
|
2574 } else { |
|
2575 s32 i; |
|
2576 |
|
2577 /* Otherwise poll for sometime so the current |
|
2578 * cycle has a chance to end before giving up. |
|
2579 */ |
|
2580 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
|
2581 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
2582 if (!hsfsts.hsf_status.flcinprog) { |
|
2583 ret_val = 0; |
|
2584 break; |
|
2585 } |
|
2586 udelay(1); |
|
2587 } |
|
2588 if (!ret_val) { |
|
2589 /* Successful in waiting for previous cycle to timeout, |
|
2590 * now set the Flash Cycle Done. |
|
2591 */ |
|
2592 hsfsts.hsf_status.flcdone = 1; |
|
2593 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
|
2594 } else { |
|
2595 e_dbg("Flash controller busy, cannot get access\n"); |
|
2596 } |
|
2597 } |
|
2598 |
|
2599 return ret_val; |
|
2600 } |
|
2601 |
|
2602 /** |
|
2603 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) |
|
2604 * @hw: pointer to the HW structure |
|
2605 * @timeout: maximum time to wait for completion |
|
2606 * |
|
2607 * This function starts a flash cycle and waits for its completion. |
|
2608 **/ |
|
2609 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) |
|
2610 { |
|
2611 union ich8_hws_flash_ctrl hsflctl; |
|
2612 union ich8_hws_flash_status hsfsts; |
|
2613 u32 i = 0; |
|
2614 |
|
2615 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ |
|
2616 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
|
2617 hsflctl.hsf_ctrl.flcgo = 1; |
|
2618 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
|
2619 |
|
2620 /* wait till FDONE bit is set to 1 */ |
|
2621 do { |
|
2622 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
2623 if (hsfsts.hsf_status.flcdone) |
|
2624 break; |
|
2625 udelay(1); |
|
2626 } while (i++ < timeout); |
|
2627 |
|
2628 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) |
|
2629 return 0; |
|
2630 |
|
2631 return -E1000_ERR_NVM; |
|
2632 } |
|
2633 |
|
2634 /** |
|
2635 * e1000_read_flash_word_ich8lan - Read word from flash |
|
2636 * @hw: pointer to the HW structure |
|
2637 * @offset: offset to data location |
|
2638 * @data: pointer to the location for storing the data |
|
2639 * |
|
2640 * Reads the flash word at offset into data. Offset is converted |
|
2641 * to bytes before read. |
|
2642 **/ |
|
2643 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
|
2644 u16 *data) |
|
2645 { |
|
2646 /* Must convert offset into bytes. */ |
|
2647 offset <<= 1; |
|
2648 |
|
2649 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); |
|
2650 } |
|
2651 |
|
2652 /** |
|
2653 * e1000_read_flash_byte_ich8lan - Read byte from flash |
|
2654 * @hw: pointer to the HW structure |
|
2655 * @offset: The offset of the byte to read. |
|
2656 * @data: Pointer to a byte to store the value read. |
|
2657 * |
|
2658 * Reads a single byte from the NVM using the flash access registers. |
|
2659 **/ |
|
2660 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
|
2661 u8 *data) |
|
2662 { |
|
2663 s32 ret_val; |
|
2664 u16 word = 0; |
|
2665 |
|
2666 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); |
|
2667 if (ret_val) |
|
2668 return ret_val; |
|
2669 |
|
2670 *data = (u8)word; |
|
2671 |
|
2672 return 0; |
|
2673 } |
|
2674 |
|
2675 /** |
|
2676 * e1000_read_flash_data_ich8lan - Read byte or word from NVM |
|
2677 * @hw: pointer to the HW structure |
|
2678 * @offset: The offset (in bytes) of the byte or word to read. |
|
2679 * @size: Size of data to read, 1=byte 2=word |
|
2680 * @data: Pointer to the word to store the value read. |
|
2681 * |
|
2682 * Reads a byte or word from the NVM using the flash access registers. |
|
2683 **/ |
|
2684 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
|
2685 u8 size, u16 *data) |
|
2686 { |
|
2687 union ich8_hws_flash_status hsfsts; |
|
2688 union ich8_hws_flash_ctrl hsflctl; |
|
2689 u32 flash_linear_addr; |
|
2690 u32 flash_data = 0; |
|
2691 s32 ret_val = -E1000_ERR_NVM; |
|
2692 u8 count = 0; |
|
2693 |
|
2694 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) |
|
2695 return -E1000_ERR_NVM; |
|
2696 |
|
2697 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
|
2698 hw->nvm.flash_base_addr; |
|
2699 |
|
2700 do { |
|
2701 udelay(1); |
|
2702 /* Steps */ |
|
2703 ret_val = e1000_flash_cycle_init_ich8lan(hw); |
|
2704 if (ret_val) |
|
2705 break; |
|
2706 |
|
2707 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
|
2708 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
|
2709 hsflctl.hsf_ctrl.fldbcount = size - 1; |
|
2710 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
|
2711 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
|
2712 |
|
2713 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
|
2714 |
|
2715 ret_val = e1000_flash_cycle_ich8lan(hw, |
|
2716 ICH_FLASH_READ_COMMAND_TIMEOUT); |
|
2717 |
|
2718 /* Check if FCERR is set to 1, if set to 1, clear it |
|
2719 * and try the whole sequence a few more times, else |
|
2720 * read in (shift in) the Flash Data0, the order is |
|
2721 * least significant byte first msb to lsb |
|
2722 */ |
|
2723 if (!ret_val) { |
|
2724 flash_data = er32flash(ICH_FLASH_FDATA0); |
|
2725 if (size == 1) |
|
2726 *data = (u8)(flash_data & 0x000000FF); |
|
2727 else if (size == 2) |
|
2728 *data = (u16)(flash_data & 0x0000FFFF); |
|
2729 break; |
|
2730 } else { |
|
2731 /* If we've gotten here, then things are probably |
|
2732 * completely hosed, but if the error condition is |
|
2733 * detected, it won't hurt to give it another try... |
|
2734 * ICH_FLASH_CYCLE_REPEAT_COUNT times. |
|
2735 */ |
|
2736 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
2737 if (hsfsts.hsf_status.flcerr) { |
|
2738 /* Repeat for some time before giving up. */ |
|
2739 continue; |
|
2740 } else if (!hsfsts.hsf_status.flcdone) { |
|
2741 e_dbg("Timeout error - flash cycle did not complete.\n"); |
|
2742 break; |
|
2743 } |
|
2744 } |
|
2745 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
|
2746 |
|
2747 return ret_val; |
|
2748 } |
|
2749 |
|
2750 /** |
|
2751 * e1000_write_nvm_ich8lan - Write word(s) to the NVM |
|
2752 * @hw: pointer to the HW structure |
|
2753 * @offset: The offset (in bytes) of the word(s) to write. |
|
2754 * @words: Size of data to write in words |
|
2755 * @data: Pointer to the word(s) to write at offset. |
|
2756 * |
|
2757 * Writes a byte or word to the NVM using the flash access registers. |
|
2758 **/ |
|
2759 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, |
|
2760 u16 *data) |
|
2761 { |
|
2762 struct e1000_nvm_info *nvm = &hw->nvm; |
|
2763 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
2764 u16 i; |
|
2765 |
|
2766 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
|
2767 (words == 0)) { |
|
2768 e_dbg("nvm parameter(s) out of bounds\n"); |
|
2769 return -E1000_ERR_NVM; |
|
2770 } |
|
2771 |
|
2772 nvm->ops.acquire(hw); |
|
2773 |
|
2774 for (i = 0; i < words; i++) { |
|
2775 dev_spec->shadow_ram[offset+i].modified = true; |
|
2776 dev_spec->shadow_ram[offset+i].value = data[i]; |
|
2777 } |
|
2778 |
|
2779 nvm->ops.release(hw); |
|
2780 |
|
2781 return 0; |
|
2782 } |
|
2783 |
|
2784 /** |
|
2785 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM |
|
2786 * @hw: pointer to the HW structure |
|
2787 * |
|
2788 * The NVM checksum is updated by calling the generic update_nvm_checksum, |
|
2789 * which writes the checksum to the shadow ram. The changes in the shadow |
|
2790 * ram are then committed to the EEPROM by processing each bank at a time |
|
2791 * checking for the modified bit and writing only the pending changes. |
|
2792 * After a successful commit, the shadow ram is cleared and is ready for |
|
2793 * future writes. |
|
2794 **/ |
|
2795 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) |
|
2796 { |
|
2797 struct e1000_nvm_info *nvm = &hw->nvm; |
|
2798 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
2799 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
|
2800 s32 ret_val; |
|
2801 u16 data; |
|
2802 |
|
2803 ret_val = e1000e_update_nvm_checksum_generic(hw); |
|
2804 if (ret_val) |
|
2805 goto out; |
|
2806 |
|
2807 if (nvm->type != e1000_nvm_flash_sw) |
|
2808 goto out; |
|
2809 |
|
2810 nvm->ops.acquire(hw); |
|
2811 |
|
2812 /* We're writing to the opposite bank so if we're on bank 1, |
|
2813 * write to bank 0 etc. We also need to erase the segment that |
|
2814 * is going to be written |
|
2815 */ |
|
2816 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
|
2817 if (ret_val) { |
|
2818 e_dbg("Could not detect valid bank, assuming bank 0\n"); |
|
2819 bank = 0; |
|
2820 } |
|
2821 |
|
2822 if (bank == 0) { |
|
2823 new_bank_offset = nvm->flash_bank_size; |
|
2824 old_bank_offset = 0; |
|
2825 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
|
2826 if (ret_val) |
|
2827 goto release; |
|
2828 } else { |
|
2829 old_bank_offset = nvm->flash_bank_size; |
|
2830 new_bank_offset = 0; |
|
2831 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
|
2832 if (ret_val) |
|
2833 goto release; |
|
2834 } |
|
2835 |
|
2836 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
|
2837 /* Determine whether to write the value stored |
|
2838 * in the other NVM bank or a modified value stored |
|
2839 * in the shadow RAM |
|
2840 */ |
|
2841 if (dev_spec->shadow_ram[i].modified) { |
|
2842 data = dev_spec->shadow_ram[i].value; |
|
2843 } else { |
|
2844 ret_val = e1000_read_flash_word_ich8lan(hw, i + |
|
2845 old_bank_offset, |
|
2846 &data); |
|
2847 if (ret_val) |
|
2848 break; |
|
2849 } |
|
2850 |
|
2851 /* If the word is 0x13, then make sure the signature bits |
|
2852 * (15:14) are 11b until the commit has completed. |
|
2853 * This will allow us to write 10b which indicates the |
|
2854 * signature is valid. We want to do this after the write |
|
2855 * has completed so that we don't mark the segment valid |
|
2856 * while the write is still in progress |
|
2857 */ |
|
2858 if (i == E1000_ICH_NVM_SIG_WORD) |
|
2859 data |= E1000_ICH_NVM_SIG_MASK; |
|
2860 |
|
2861 /* Convert offset to bytes. */ |
|
2862 act_offset = (i + new_bank_offset) << 1; |
|
2863 |
|
2864 udelay(100); |
|
2865 /* Write the bytes to the new bank. */ |
|
2866 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
|
2867 act_offset, |
|
2868 (u8)data); |
|
2869 if (ret_val) |
|
2870 break; |
|
2871 |
|
2872 udelay(100); |
|
2873 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
|
2874 act_offset + 1, |
|
2875 (u8)(data >> 8)); |
|
2876 if (ret_val) |
|
2877 break; |
|
2878 } |
|
2879 |
|
2880 /* Don't bother writing the segment valid bits if sector |
|
2881 * programming failed. |
|
2882 */ |
|
2883 if (ret_val) { |
|
2884 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
|
2885 e_dbg("Flash commit failed.\n"); |
|
2886 goto release; |
|
2887 } |
|
2888 |
|
2889 /* Finally validate the new segment by setting bit 15:14 |
|
2890 * to 10b in word 0x13 , this can be done without an |
|
2891 * erase as well since these bits are 11 to start with |
|
2892 * and we need to change bit 14 to 0b |
|
2893 */ |
|
2894 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
|
2895 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
|
2896 if (ret_val) |
|
2897 goto release; |
|
2898 |
|
2899 data &= 0xBFFF; |
|
2900 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
|
2901 act_offset * 2 + 1, |
|
2902 (u8)(data >> 8)); |
|
2903 if (ret_val) |
|
2904 goto release; |
|
2905 |
|
2906 /* And invalidate the previously valid segment by setting |
|
2907 * its signature word (0x13) high_byte to 0b. This can be |
|
2908 * done without an erase because flash erase sets all bits |
|
2909 * to 1's. We can write 1's to 0's without an erase |
|
2910 */ |
|
2911 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
|
2912 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); |
|
2913 if (ret_val) |
|
2914 goto release; |
|
2915 |
|
2916 /* Great! Everything worked, we can now clear the cached entries. */ |
|
2917 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
|
2918 dev_spec->shadow_ram[i].modified = false; |
|
2919 dev_spec->shadow_ram[i].value = 0xFFFF; |
|
2920 } |
|
2921 |
|
2922 release: |
|
2923 nvm->ops.release(hw); |
|
2924 |
|
2925 /* Reload the EEPROM, or else modifications will not appear |
|
2926 * until after the next adapter reset. |
|
2927 */ |
|
2928 if (!ret_val) { |
|
2929 nvm->ops.reload(hw); |
|
2930 usleep_range(10000, 20000); |
|
2931 } |
|
2932 |
|
2933 out: |
|
2934 if (ret_val) |
|
2935 e_dbg("NVM update error: %d\n", ret_val); |
|
2936 |
|
2937 return ret_val; |
|
2938 } |
|
2939 |
|
2940 /** |
|
2941 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum |
|
2942 * @hw: pointer to the HW structure |
|
2943 * |
|
2944 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. |
|
2945 * If the bit is 0, that the EEPROM had been modified, but the checksum was not |
|
2946 * calculated, in which case we need to calculate the checksum and set bit 6. |
|
2947 **/ |
|
2948 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) |
|
2949 { |
|
2950 s32 ret_val; |
|
2951 u16 data; |
|
2952 |
|
2953 /* Read 0x19 and check bit 6. If this bit is 0, the checksum |
|
2954 * needs to be fixed. This bit is an indication that the NVM |
|
2955 * was prepared by OEM software and did not calculate the |
|
2956 * checksum...a likely scenario. |
|
2957 */ |
|
2958 ret_val = e1000_read_nvm(hw, 0x19, 1, &data); |
|
2959 if (ret_val) |
|
2960 return ret_val; |
|
2961 |
|
2962 if (!(data & 0x40)) { |
|
2963 data |= 0x40; |
|
2964 ret_val = e1000_write_nvm(hw, 0x19, 1, &data); |
|
2965 if (ret_val) |
|
2966 return ret_val; |
|
2967 ret_val = e1000e_update_nvm_checksum(hw); |
|
2968 if (ret_val) |
|
2969 return ret_val; |
|
2970 } |
|
2971 |
|
2972 return e1000e_validate_nvm_checksum_generic(hw); |
|
2973 } |
|
2974 |
|
2975 /** |
|
2976 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only |
|
2977 * @hw: pointer to the HW structure |
|
2978 * |
|
2979 * To prevent malicious write/erase of the NVM, set it to be read-only |
|
2980 * so that the hardware ignores all write/erase cycles of the NVM via |
|
2981 * the flash control registers. The shadow-ram copy of the NVM will |
|
2982 * still be updated, however any updates to this copy will not stick |
|
2983 * across driver reloads. |
|
2984 **/ |
|
2985 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) |
|
2986 { |
|
2987 struct e1000_nvm_info *nvm = &hw->nvm; |
|
2988 union ich8_flash_protected_range pr0; |
|
2989 union ich8_hws_flash_status hsfsts; |
|
2990 u32 gfpreg; |
|
2991 |
|
2992 nvm->ops.acquire(hw); |
|
2993 |
|
2994 gfpreg = er32flash(ICH_FLASH_GFPREG); |
|
2995 |
|
2996 /* Write-protect GbE Sector of NVM */ |
|
2997 pr0.regval = er32flash(ICH_FLASH_PR0); |
|
2998 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; |
|
2999 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); |
|
3000 pr0.range.wpe = true; |
|
3001 ew32flash(ICH_FLASH_PR0, pr0.regval); |
|
3002 |
|
3003 /* Lock down a subset of GbE Flash Control Registers, e.g. |
|
3004 * PR0 to prevent the write-protection from being lifted. |
|
3005 * Once FLOCKDN is set, the registers protected by it cannot |
|
3006 * be written until FLOCKDN is cleared by a hardware reset. |
|
3007 */ |
|
3008 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
3009 hsfsts.hsf_status.flockdn = true; |
|
3010 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
|
3011 |
|
3012 nvm->ops.release(hw); |
|
3013 } |
|
3014 |
|
3015 /** |
|
3016 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM |
|
3017 * @hw: pointer to the HW structure |
|
3018 * @offset: The offset (in bytes) of the byte/word to read. |
|
3019 * @size: Size of data to read, 1=byte 2=word |
|
3020 * @data: The byte(s) to write to the NVM. |
|
3021 * |
|
3022 * Writes one/two bytes to the NVM using the flash access registers. |
|
3023 **/ |
|
3024 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
|
3025 u8 size, u16 data) |
|
3026 { |
|
3027 union ich8_hws_flash_status hsfsts; |
|
3028 union ich8_hws_flash_ctrl hsflctl; |
|
3029 u32 flash_linear_addr; |
|
3030 u32 flash_data = 0; |
|
3031 s32 ret_val; |
|
3032 u8 count = 0; |
|
3033 |
|
3034 if (size < 1 || size > 2 || data > size * 0xff || |
|
3035 offset > ICH_FLASH_LINEAR_ADDR_MASK) |
|
3036 return -E1000_ERR_NVM; |
|
3037 |
|
3038 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
|
3039 hw->nvm.flash_base_addr; |
|
3040 |
|
3041 do { |
|
3042 udelay(1); |
|
3043 /* Steps */ |
|
3044 ret_val = e1000_flash_cycle_init_ich8lan(hw); |
|
3045 if (ret_val) |
|
3046 break; |
|
3047 |
|
3048 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
|
3049 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
|
3050 hsflctl.hsf_ctrl.fldbcount = size -1; |
|
3051 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
|
3052 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
|
3053 |
|
3054 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
|
3055 |
|
3056 if (size == 1) |
|
3057 flash_data = (u32)data & 0x00FF; |
|
3058 else |
|
3059 flash_data = (u32)data; |
|
3060 |
|
3061 ew32flash(ICH_FLASH_FDATA0, flash_data); |
|
3062 |
|
3063 /* check if FCERR is set to 1 , if set to 1, clear it |
|
3064 * and try the whole sequence a few more times else done |
|
3065 */ |
|
3066 ret_val = e1000_flash_cycle_ich8lan(hw, |
|
3067 ICH_FLASH_WRITE_COMMAND_TIMEOUT); |
|
3068 if (!ret_val) |
|
3069 break; |
|
3070 |
|
3071 /* If we're here, then things are most likely |
|
3072 * completely hosed, but if the error condition |
|
3073 * is detected, it won't hurt to give it another |
|
3074 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
|
3075 */ |
|
3076 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
3077 if (hsfsts.hsf_status.flcerr) |
|
3078 /* Repeat for some time before giving up. */ |
|
3079 continue; |
|
3080 if (!hsfsts.hsf_status.flcdone) { |
|
3081 e_dbg("Timeout error - flash cycle did not complete.\n"); |
|
3082 break; |
|
3083 } |
|
3084 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
|
3085 |
|
3086 return ret_val; |
|
3087 } |
|
3088 |
|
3089 /** |
|
3090 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM |
|
3091 * @hw: pointer to the HW structure |
|
3092 * @offset: The index of the byte to read. |
|
3093 * @data: The byte to write to the NVM. |
|
3094 * |
|
3095 * Writes a single byte to the NVM using the flash access registers. |
|
3096 **/ |
|
3097 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
|
3098 u8 data) |
|
3099 { |
|
3100 u16 word = (u16)data; |
|
3101 |
|
3102 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); |
|
3103 } |
|
3104 |
|
3105 /** |
|
3106 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM |
|
3107 * @hw: pointer to the HW structure |
|
3108 * @offset: The offset of the byte to write. |
|
3109 * @byte: The byte to write to the NVM. |
|
3110 * |
|
3111 * Writes a single byte to the NVM using the flash access registers. |
|
3112 * Goes through a retry algorithm before giving up. |
|
3113 **/ |
|
3114 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
|
3115 u32 offset, u8 byte) |
|
3116 { |
|
3117 s32 ret_val; |
|
3118 u16 program_retries; |
|
3119 |
|
3120 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
|
3121 if (!ret_val) |
|
3122 return ret_val; |
|
3123 |
|
3124 for (program_retries = 0; program_retries < 100; program_retries++) { |
|
3125 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); |
|
3126 udelay(100); |
|
3127 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
|
3128 if (!ret_val) |
|
3129 break; |
|
3130 } |
|
3131 if (program_retries == 100) |
|
3132 return -E1000_ERR_NVM; |
|
3133 |
|
3134 return 0; |
|
3135 } |
|
3136 |
|
3137 /** |
|
3138 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM |
|
3139 * @hw: pointer to the HW structure |
|
3140 * @bank: 0 for first bank, 1 for second bank, etc. |
|
3141 * |
|
3142 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. |
|
3143 * bank N is 4096 * N + flash_reg_addr. |
|
3144 **/ |
|
3145 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) |
|
3146 { |
|
3147 struct e1000_nvm_info *nvm = &hw->nvm; |
|
3148 union ich8_hws_flash_status hsfsts; |
|
3149 union ich8_hws_flash_ctrl hsflctl; |
|
3150 u32 flash_linear_addr; |
|
3151 /* bank size is in 16bit words - adjust to bytes */ |
|
3152 u32 flash_bank_size = nvm->flash_bank_size * 2; |
|
3153 s32 ret_val; |
|
3154 s32 count = 0; |
|
3155 s32 j, iteration, sector_size; |
|
3156 |
|
3157 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
3158 |
|
3159 /* Determine HW Sector size: Read BERASE bits of hw flash status |
|
3160 * register |
|
3161 * 00: The Hw sector is 256 bytes, hence we need to erase 16 |
|
3162 * consecutive sectors. The start index for the nth Hw sector |
|
3163 * can be calculated as = bank * 4096 + n * 256 |
|
3164 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
|
3165 * The start index for the nth Hw sector can be calculated |
|
3166 * as = bank * 4096 |
|
3167 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 |
|
3168 * (ich9 only, otherwise error condition) |
|
3169 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 |
|
3170 */ |
|
3171 switch (hsfsts.hsf_status.berasesz) { |
|
3172 case 0: |
|
3173 /* Hw sector size 256 */ |
|
3174 sector_size = ICH_FLASH_SEG_SIZE_256; |
|
3175 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; |
|
3176 break; |
|
3177 case 1: |
|
3178 sector_size = ICH_FLASH_SEG_SIZE_4K; |
|
3179 iteration = 1; |
|
3180 break; |
|
3181 case 2: |
|
3182 sector_size = ICH_FLASH_SEG_SIZE_8K; |
|
3183 iteration = 1; |
|
3184 break; |
|
3185 case 3: |
|
3186 sector_size = ICH_FLASH_SEG_SIZE_64K; |
|
3187 iteration = 1; |
|
3188 break; |
|
3189 default: |
|
3190 return -E1000_ERR_NVM; |
|
3191 } |
|
3192 |
|
3193 /* Start with the base address, then add the sector offset. */ |
|
3194 flash_linear_addr = hw->nvm.flash_base_addr; |
|
3195 flash_linear_addr += (bank) ? flash_bank_size : 0; |
|
3196 |
|
3197 for (j = 0; j < iteration ; j++) { |
|
3198 do { |
|
3199 /* Steps */ |
|
3200 ret_val = e1000_flash_cycle_init_ich8lan(hw); |
|
3201 if (ret_val) |
|
3202 return ret_val; |
|
3203 |
|
3204 /* Write a value 11 (block Erase) in Flash |
|
3205 * Cycle field in hw flash control |
|
3206 */ |
|
3207 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
|
3208 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; |
|
3209 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
|
3210 |
|
3211 /* Write the last 24 bits of an index within the |
|
3212 * block into Flash Linear address field in Flash |
|
3213 * Address. |
|
3214 */ |
|
3215 flash_linear_addr += (j * sector_size); |
|
3216 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
|
3217 |
|
3218 ret_val = e1000_flash_cycle_ich8lan(hw, |
|
3219 ICH_FLASH_ERASE_COMMAND_TIMEOUT); |
|
3220 if (!ret_val) |
|
3221 break; |
|
3222 |
|
3223 /* Check if FCERR is set to 1. If 1, |
|
3224 * clear it and try the whole sequence |
|
3225 * a few more times else Done |
|
3226 */ |
|
3227 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
|
3228 if (hsfsts.hsf_status.flcerr) |
|
3229 /* repeat for some time before giving up */ |
|
3230 continue; |
|
3231 else if (!hsfsts.hsf_status.flcdone) |
|
3232 return ret_val; |
|
3233 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); |
|
3234 } |
|
3235 |
|
3236 return 0; |
|
3237 } |
|
3238 |
|
3239 /** |
|
3240 * e1000_valid_led_default_ich8lan - Set the default LED settings |
|
3241 * @hw: pointer to the HW structure |
|
3242 * @data: Pointer to the LED settings |
|
3243 * |
|
3244 * Reads the LED default settings from the NVM to data. If the NVM LED |
|
3245 * settings is all 0's or F's, set the LED default to a valid LED default |
|
3246 * setting. |
|
3247 **/ |
|
3248 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) |
|
3249 { |
|
3250 s32 ret_val; |
|
3251 |
|
3252 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
|
3253 if (ret_val) { |
|
3254 e_dbg("NVM Read Error\n"); |
|
3255 return ret_val; |
|
3256 } |
|
3257 |
|
3258 if (*data == ID_LED_RESERVED_0000 || |
|
3259 *data == ID_LED_RESERVED_FFFF) |
|
3260 *data = ID_LED_DEFAULT_ICH8LAN; |
|
3261 |
|
3262 return 0; |
|
3263 } |
|
3264 |
|
3265 /** |
|
3266 * e1000_id_led_init_pchlan - store LED configurations |
|
3267 * @hw: pointer to the HW structure |
|
3268 * |
|
3269 * PCH does not control LEDs via the LEDCTL register, rather it uses |
|
3270 * the PHY LED configuration register. |
|
3271 * |
|
3272 * PCH also does not have an "always on" or "always off" mode which |
|
3273 * complicates the ID feature. Instead of using the "on" mode to indicate |
|
3274 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), |
|
3275 * use "link_up" mode. The LEDs will still ID on request if there is no |
|
3276 * link based on logic in e1000_led_[on|off]_pchlan(). |
|
3277 **/ |
|
3278 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) |
|
3279 { |
|
3280 struct e1000_mac_info *mac = &hw->mac; |
|
3281 s32 ret_val; |
|
3282 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; |
|
3283 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; |
|
3284 u16 data, i, temp, shift; |
|
3285 |
|
3286 /* Get default ID LED modes */ |
|
3287 ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
|
3288 if (ret_val) |
|
3289 return ret_val; |
|
3290 |
|
3291 mac->ledctl_default = er32(LEDCTL); |
|
3292 mac->ledctl_mode1 = mac->ledctl_default; |
|
3293 mac->ledctl_mode2 = mac->ledctl_default; |
|
3294 |
|
3295 for (i = 0; i < 4; i++) { |
|
3296 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; |
|
3297 shift = (i * 5); |
|
3298 switch (temp) { |
|
3299 case ID_LED_ON1_DEF2: |
|
3300 case ID_LED_ON1_ON2: |
|
3301 case ID_LED_ON1_OFF2: |
|
3302 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); |
|
3303 mac->ledctl_mode1 |= (ledctl_on << shift); |
|
3304 break; |
|
3305 case ID_LED_OFF1_DEF2: |
|
3306 case ID_LED_OFF1_ON2: |
|
3307 case ID_LED_OFF1_OFF2: |
|
3308 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); |
|
3309 mac->ledctl_mode1 |= (ledctl_off << shift); |
|
3310 break; |
|
3311 default: |
|
3312 /* Do nothing */ |
|
3313 break; |
|
3314 } |
|
3315 switch (temp) { |
|
3316 case ID_LED_DEF1_ON2: |
|
3317 case ID_LED_ON1_ON2: |
|
3318 case ID_LED_OFF1_ON2: |
|
3319 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); |
|
3320 mac->ledctl_mode2 |= (ledctl_on << shift); |
|
3321 break; |
|
3322 case ID_LED_DEF1_OFF2: |
|
3323 case ID_LED_ON1_OFF2: |
|
3324 case ID_LED_OFF1_OFF2: |
|
3325 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); |
|
3326 mac->ledctl_mode2 |= (ledctl_off << shift); |
|
3327 break; |
|
3328 default: |
|
3329 /* Do nothing */ |
|
3330 break; |
|
3331 } |
|
3332 } |
|
3333 |
|
3334 return 0; |
|
3335 } |
|
3336 |
|
3337 /** |
|
3338 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width |
|
3339 * @hw: pointer to the HW structure |
|
3340 * |
|
3341 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability |
|
3342 * register, so the the bus width is hard coded. |
|
3343 **/ |
|
3344 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) |
|
3345 { |
|
3346 struct e1000_bus_info *bus = &hw->bus; |
|
3347 s32 ret_val; |
|
3348 |
|
3349 ret_val = e1000e_get_bus_info_pcie(hw); |
|
3350 |
|
3351 /* ICH devices are "PCI Express"-ish. They have |
|
3352 * a configuration space, but do not contain |
|
3353 * PCI Express Capability registers, so bus width |
|
3354 * must be hardcoded. |
|
3355 */ |
|
3356 if (bus->width == e1000_bus_width_unknown) |
|
3357 bus->width = e1000_bus_width_pcie_x1; |
|
3358 |
|
3359 return ret_val; |
|
3360 } |
|
3361 |
|
3362 /** |
|
3363 * e1000_reset_hw_ich8lan - Reset the hardware |
|
3364 * @hw: pointer to the HW structure |
|
3365 * |
|
3366 * Does a full reset of the hardware which includes a reset of the PHY and |
|
3367 * MAC. |
|
3368 **/ |
|
3369 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) |
|
3370 { |
|
3371 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
3372 u16 kum_cfg; |
|
3373 u32 ctrl, reg; |
|
3374 s32 ret_val; |
|
3375 |
|
3376 /* Prevent the PCI-E bus from sticking if there is no TLP connection |
|
3377 * on the last TLP read/write transaction when MAC is reset. |
|
3378 */ |
|
3379 ret_val = e1000e_disable_pcie_master(hw); |
|
3380 if (ret_val) |
|
3381 e_dbg("PCI-E Master disable polling has failed.\n"); |
|
3382 |
|
3383 e_dbg("Masking off all interrupts\n"); |
|
3384 ew32(IMC, 0xffffffff); |
|
3385 |
|
3386 /* Disable the Transmit and Receive units. Then delay to allow |
|
3387 * any pending transactions to complete before we hit the MAC |
|
3388 * with the global reset. |
|
3389 */ |
|
3390 ew32(RCTL, 0); |
|
3391 ew32(TCTL, E1000_TCTL_PSP); |
|
3392 e1e_flush(); |
|
3393 |
|
3394 usleep_range(10000, 20000); |
|
3395 |
|
3396 /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
|
3397 if (hw->mac.type == e1000_ich8lan) { |
|
3398 /* Set Tx and Rx buffer allocation to 8k apiece. */ |
|
3399 ew32(PBA, E1000_PBA_8K); |
|
3400 /* Set Packet Buffer Size to 16k. */ |
|
3401 ew32(PBS, E1000_PBS_16K); |
|
3402 } |
|
3403 |
|
3404 if (hw->mac.type == e1000_pchlan) { |
|
3405 /* Save the NVM K1 bit setting */ |
|
3406 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); |
|
3407 if (ret_val) |
|
3408 return ret_val; |
|
3409 |
|
3410 if (kum_cfg & E1000_NVM_K1_ENABLE) |
|
3411 dev_spec->nvm_k1_enabled = true; |
|
3412 else |
|
3413 dev_spec->nvm_k1_enabled = false; |
|
3414 } |
|
3415 |
|
3416 ctrl = er32(CTRL); |
|
3417 |
|
3418 if (!hw->phy.ops.check_reset_block(hw)) { |
|
3419 /* Full-chip reset requires MAC and PHY reset at the same |
|
3420 * time to make sure the interface between MAC and the |
|
3421 * external PHY is reset. |
|
3422 */ |
|
3423 ctrl |= E1000_CTRL_PHY_RST; |
|
3424 |
|
3425 /* Gate automatic PHY configuration by hardware on |
|
3426 * non-managed 82579 |
|
3427 */ |
|
3428 if ((hw->mac.type == e1000_pch2lan) && |
|
3429 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
|
3430 e1000_gate_hw_phy_config_ich8lan(hw, true); |
|
3431 } |
|
3432 ret_val = e1000_acquire_swflag_ich8lan(hw); |
|
3433 e_dbg("Issuing a global reset to ich8lan\n"); |
|
3434 ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
|
3435 /* cannot issue a flush here because it hangs the hardware */ |
|
3436 msleep(20); |
|
3437 |
|
3438 /* Set Phy Config Counter to 50msec */ |
|
3439 if (hw->mac.type == e1000_pch2lan) { |
|
3440 reg = er32(FEXTNVM3); |
|
3441 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; |
|
3442 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; |
|
3443 ew32(FEXTNVM3, reg); |
|
3444 } |
|
3445 |
|
3446 if (!ret_val) |
|
3447 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
|
3448 |
|
3449 if (ctrl & E1000_CTRL_PHY_RST) { |
|
3450 ret_val = hw->phy.ops.get_cfg_done(hw); |
|
3451 if (ret_val) |
|
3452 return ret_val; |
|
3453 |
|
3454 ret_val = e1000_post_phy_reset_ich8lan(hw); |
|
3455 if (ret_val) |
|
3456 return ret_val; |
|
3457 } |
|
3458 |
|
3459 /* For PCH, this write will make sure that any noise |
|
3460 * will be detected as a CRC error and be dropped rather than show up |
|
3461 * as a bad packet to the DMA engine. |
|
3462 */ |
|
3463 if (hw->mac.type == e1000_pchlan) |
|
3464 ew32(CRC_OFFSET, 0x65656565); |
|
3465 |
|
3466 ew32(IMC, 0xffffffff); |
|
3467 er32(ICR); |
|
3468 |
|
3469 reg = er32(KABGTXD); |
|
3470 reg |= E1000_KABGTXD_BGSQLBIAS; |
|
3471 ew32(KABGTXD, reg); |
|
3472 |
|
3473 return 0; |
|
3474 } |
|
3475 |
|
3476 /** |
|
3477 * e1000_init_hw_ich8lan - Initialize the hardware |
|
3478 * @hw: pointer to the HW structure |
|
3479 * |
|
3480 * Prepares the hardware for transmit and receive by doing the following: |
|
3481 * - initialize hardware bits |
|
3482 * - initialize LED identification |
|
3483 * - setup receive address registers |
|
3484 * - setup flow control |
|
3485 * - setup transmit descriptors |
|
3486 * - clear statistics |
|
3487 **/ |
|
3488 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) |
|
3489 { |
|
3490 struct e1000_mac_info *mac = &hw->mac; |
|
3491 u32 ctrl_ext, txdctl, snoop; |
|
3492 s32 ret_val; |
|
3493 u16 i; |
|
3494 |
|
3495 e1000_initialize_hw_bits_ich8lan(hw); |
|
3496 |
|
3497 /* Initialize identification LED */ |
|
3498 ret_val = mac->ops.id_led_init(hw); |
|
3499 if (ret_val) |
|
3500 e_dbg("Error initializing identification LED\n"); |
|
3501 /* This is not fatal and we should not stop init due to this */ |
|
3502 |
|
3503 /* Setup the receive address. */ |
|
3504 e1000e_init_rx_addrs(hw, mac->rar_entry_count); |
|
3505 |
|
3506 /* Zero out the Multicast HASH table */ |
|
3507 e_dbg("Zeroing the MTA\n"); |
|
3508 for (i = 0; i < mac->mta_reg_count; i++) |
|
3509 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
|
3510 |
|
3511 /* The 82578 Rx buffer will stall if wakeup is enabled in host and |
|
3512 * the ME. Disable wakeup by clearing the host wakeup bit. |
|
3513 * Reset the phy after disabling host wakeup to reset the Rx buffer. |
|
3514 */ |
|
3515 if (hw->phy.type == e1000_phy_82578) { |
|
3516 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); |
|
3517 i &= ~BM_WUC_HOST_WU_BIT; |
|
3518 e1e_wphy(hw, BM_PORT_GEN_CFG, i); |
|
3519 ret_val = e1000_phy_hw_reset_ich8lan(hw); |
|
3520 if (ret_val) |
|
3521 return ret_val; |
|
3522 } |
|
3523 |
|
3524 /* Setup link and flow control */ |
|
3525 ret_val = mac->ops.setup_link(hw); |
|
3526 |
|
3527 /* Set the transmit descriptor write-back policy for both queues */ |
|
3528 txdctl = er32(TXDCTL(0)); |
|
3529 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
|
3530 E1000_TXDCTL_FULL_TX_DESC_WB; |
|
3531 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | |
|
3532 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; |
|
3533 ew32(TXDCTL(0), txdctl); |
|
3534 txdctl = er32(TXDCTL(1)); |
|
3535 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
|
3536 E1000_TXDCTL_FULL_TX_DESC_WB; |
|
3537 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | |
|
3538 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; |
|
3539 ew32(TXDCTL(1), txdctl); |
|
3540 |
|
3541 /* ICH8 has opposite polarity of no_snoop bits. |
|
3542 * By default, we should use snoop behavior. |
|
3543 */ |
|
3544 if (mac->type == e1000_ich8lan) |
|
3545 snoop = PCIE_ICH8_SNOOP_ALL; |
|
3546 else |
|
3547 snoop = (u32) ~(PCIE_NO_SNOOP_ALL); |
|
3548 e1000e_set_pcie_no_snoop(hw, snoop); |
|
3549 |
|
3550 ctrl_ext = er32(CTRL_EXT); |
|
3551 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
3552 ew32(CTRL_EXT, ctrl_ext); |
|
3553 |
|
3554 /* Clear all of the statistics registers (clear on read). It is |
|
3555 * important that we do this after we have tried to establish link |
|
3556 * because the symbol error count will increment wildly if there |
|
3557 * is no link. |
|
3558 */ |
|
3559 e1000_clear_hw_cntrs_ich8lan(hw); |
|
3560 |
|
3561 return ret_val; |
|
3562 } |
|
3563 /** |
|
3564 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits |
|
3565 * @hw: pointer to the HW structure |
|
3566 * |
|
3567 * Sets/Clears required hardware bits necessary for correctly setting up the |
|
3568 * hardware for transmit and receive. |
|
3569 **/ |
|
3570 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) |
|
3571 { |
|
3572 u32 reg; |
|
3573 |
|
3574 /* Extended Device Control */ |
|
3575 reg = er32(CTRL_EXT); |
|
3576 reg |= (1 << 22); |
|
3577 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
|
3578 if (hw->mac.type >= e1000_pchlan) |
|
3579 reg |= E1000_CTRL_EXT_PHYPDEN; |
|
3580 ew32(CTRL_EXT, reg); |
|
3581 |
|
3582 /* Transmit Descriptor Control 0 */ |
|
3583 reg = er32(TXDCTL(0)); |
|
3584 reg |= (1 << 22); |
|
3585 ew32(TXDCTL(0), reg); |
|
3586 |
|
3587 /* Transmit Descriptor Control 1 */ |
|
3588 reg = er32(TXDCTL(1)); |
|
3589 reg |= (1 << 22); |
|
3590 ew32(TXDCTL(1), reg); |
|
3591 |
|
3592 /* Transmit Arbitration Control 0 */ |
|
3593 reg = er32(TARC(0)); |
|
3594 if (hw->mac.type == e1000_ich8lan) |
|
3595 reg |= (1 << 28) | (1 << 29); |
|
3596 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); |
|
3597 ew32(TARC(0), reg); |
|
3598 |
|
3599 /* Transmit Arbitration Control 1 */ |
|
3600 reg = er32(TARC(1)); |
|
3601 if (er32(TCTL) & E1000_TCTL_MULR) |
|
3602 reg &= ~(1 << 28); |
|
3603 else |
|
3604 reg |= (1 << 28); |
|
3605 reg |= (1 << 24) | (1 << 26) | (1 << 30); |
|
3606 ew32(TARC(1), reg); |
|
3607 |
|
3608 /* Device Status */ |
|
3609 if (hw->mac.type == e1000_ich8lan) { |
|
3610 reg = er32(STATUS); |
|
3611 reg &= ~(1 << 31); |
|
3612 ew32(STATUS, reg); |
|
3613 } |
|
3614 |
|
3615 /* work-around descriptor data corruption issue during nfs v2 udp |
|
3616 * traffic, just disable the nfs filtering capability |
|
3617 */ |
|
3618 reg = er32(RFCTL); |
|
3619 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); |
|
3620 |
|
3621 /* Disable IPv6 extension header parsing because some malformed |
|
3622 * IPv6 headers can hang the Rx. |
|
3623 */ |
|
3624 if (hw->mac.type == e1000_ich8lan) |
|
3625 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); |
|
3626 ew32(RFCTL, reg); |
|
3627 |
|
3628 /* Enable ECC on Lynxpoint */ |
|
3629 if (hw->mac.type == e1000_pch_lpt) { |
|
3630 reg = er32(PBECCSTS); |
|
3631 reg |= E1000_PBECCSTS_ECC_ENABLE; |
|
3632 ew32(PBECCSTS, reg); |
|
3633 |
|
3634 reg = er32(CTRL); |
|
3635 reg |= E1000_CTRL_MEHE; |
|
3636 ew32(CTRL, reg); |
|
3637 } |
|
3638 } |
|
3639 |
|
3640 /** |
|
3641 * e1000_setup_link_ich8lan - Setup flow control and link settings |
|
3642 * @hw: pointer to the HW structure |
|
3643 * |
|
3644 * Determines which flow control settings to use, then configures flow |
|
3645 * control. Calls the appropriate media-specific link configuration |
|
3646 * function. Assuming the adapter has a valid link partner, a valid link |
|
3647 * should be established. Assumes the hardware has previously been reset |
|
3648 * and the transmitter and receiver are not enabled. |
|
3649 **/ |
|
3650 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) |
|
3651 { |
|
3652 s32 ret_val; |
|
3653 |
|
3654 if (hw->phy.ops.check_reset_block(hw)) |
|
3655 return 0; |
|
3656 |
|
3657 /* ICH parts do not have a word in the NVM to determine |
|
3658 * the default flow control setting, so we explicitly |
|
3659 * set it to full. |
|
3660 */ |
|
3661 if (hw->fc.requested_mode == e1000_fc_default) { |
|
3662 /* Workaround h/w hang when Tx flow control enabled */ |
|
3663 if (hw->mac.type == e1000_pchlan) |
|
3664 hw->fc.requested_mode = e1000_fc_rx_pause; |
|
3665 else |
|
3666 hw->fc.requested_mode = e1000_fc_full; |
|
3667 } |
|
3668 |
|
3669 /* Save off the requested flow control mode for use later. Depending |
|
3670 * on the link partner's capabilities, we may or may not use this mode. |
|
3671 */ |
|
3672 hw->fc.current_mode = hw->fc.requested_mode; |
|
3673 |
|
3674 e_dbg("After fix-ups FlowControl is now = %x\n", |
|
3675 hw->fc.current_mode); |
|
3676 |
|
3677 /* Continue to configure the copper link. */ |
|
3678 ret_val = hw->mac.ops.setup_physical_interface(hw); |
|
3679 if (ret_val) |
|
3680 return ret_val; |
|
3681 |
|
3682 ew32(FCTTV, hw->fc.pause_time); |
|
3683 if ((hw->phy.type == e1000_phy_82578) || |
|
3684 (hw->phy.type == e1000_phy_82579) || |
|
3685 (hw->phy.type == e1000_phy_i217) || |
|
3686 (hw->phy.type == e1000_phy_82577)) { |
|
3687 ew32(FCRTV_PCH, hw->fc.refresh_time); |
|
3688 |
|
3689 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), |
|
3690 hw->fc.pause_time); |
|
3691 if (ret_val) |
|
3692 return ret_val; |
|
3693 } |
|
3694 |
|
3695 return e1000e_set_fc_watermarks(hw); |
|
3696 } |
|
3697 |
|
3698 /** |
|
3699 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface |
|
3700 * @hw: pointer to the HW structure |
|
3701 * |
|
3702 * Configures the kumeran interface to the PHY to wait the appropriate time |
|
3703 * when polling the PHY, then call the generic setup_copper_link to finish |
|
3704 * configuring the copper link. |
|
3705 **/ |
|
3706 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) |
|
3707 { |
|
3708 u32 ctrl; |
|
3709 s32 ret_val; |
|
3710 u16 reg_data; |
|
3711 |
|
3712 ctrl = er32(CTRL); |
|
3713 ctrl |= E1000_CTRL_SLU; |
|
3714 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
3715 ew32(CTRL, ctrl); |
|
3716 |
|
3717 /* Set the mac to wait the maximum time between each iteration |
|
3718 * and increase the max iterations when polling the phy; |
|
3719 * this fixes erroneous timeouts at 10Mbps. |
|
3720 */ |
|
3721 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); |
|
3722 if (ret_val) |
|
3723 return ret_val; |
|
3724 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
|
3725 ®_data); |
|
3726 if (ret_val) |
|
3727 return ret_val; |
|
3728 reg_data |= 0x3F; |
|
3729 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
|
3730 reg_data); |
|
3731 if (ret_val) |
|
3732 return ret_val; |
|
3733 |
|
3734 switch (hw->phy.type) { |
|
3735 case e1000_phy_igp_3: |
|
3736 ret_val = e1000e_copper_link_setup_igp(hw); |
|
3737 if (ret_val) |
|
3738 return ret_val; |
|
3739 break; |
|
3740 case e1000_phy_bm: |
|
3741 case e1000_phy_82578: |
|
3742 ret_val = e1000e_copper_link_setup_m88(hw); |
|
3743 if (ret_val) |
|
3744 return ret_val; |
|
3745 break; |
|
3746 case e1000_phy_82577: |
|
3747 case e1000_phy_82579: |
|
3748 case e1000_phy_i217: |
|
3749 ret_val = e1000_copper_link_setup_82577(hw); |
|
3750 if (ret_val) |
|
3751 return ret_val; |
|
3752 break; |
|
3753 case e1000_phy_ife: |
|
3754 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); |
|
3755 if (ret_val) |
|
3756 return ret_val; |
|
3757 |
|
3758 reg_data &= ~IFE_PMC_AUTO_MDIX; |
|
3759 |
|
3760 switch (hw->phy.mdix) { |
|
3761 case 1: |
|
3762 reg_data &= ~IFE_PMC_FORCE_MDIX; |
|
3763 break; |
|
3764 case 2: |
|
3765 reg_data |= IFE_PMC_FORCE_MDIX; |
|
3766 break; |
|
3767 case 0: |
|
3768 default: |
|
3769 reg_data |= IFE_PMC_AUTO_MDIX; |
|
3770 break; |
|
3771 } |
|
3772 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); |
|
3773 if (ret_val) |
|
3774 return ret_val; |
|
3775 break; |
|
3776 default: |
|
3777 break; |
|
3778 } |
|
3779 |
|
3780 return e1000e_setup_copper_link(hw); |
|
3781 } |
|
3782 |
|
3783 /** |
|
3784 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex |
|
3785 * @hw: pointer to the HW structure |
|
3786 * @speed: pointer to store current link speed |
|
3787 * @duplex: pointer to store the current link duplex |
|
3788 * |
|
3789 * Calls the generic get_speed_and_duplex to retrieve the current link |
|
3790 * information and then calls the Kumeran lock loss workaround for links at |
|
3791 * gigabit speeds. |
|
3792 **/ |
|
3793 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, |
|
3794 u16 *duplex) |
|
3795 { |
|
3796 s32 ret_val; |
|
3797 |
|
3798 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); |
|
3799 if (ret_val) |
|
3800 return ret_val; |
|
3801 |
|
3802 if ((hw->mac.type == e1000_ich8lan) && |
|
3803 (hw->phy.type == e1000_phy_igp_3) && |
|
3804 (*speed == SPEED_1000)) { |
|
3805 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); |
|
3806 } |
|
3807 |
|
3808 return ret_val; |
|
3809 } |
|
3810 |
|
3811 /** |
|
3812 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround |
|
3813 * @hw: pointer to the HW structure |
|
3814 * |
|
3815 * Work-around for 82566 Kumeran PCS lock loss: |
|
3816 * On link status change (i.e. PCI reset, speed change) and link is up and |
|
3817 * speed is gigabit- |
|
3818 * 0) if workaround is optionally disabled do nothing |
|
3819 * 1) wait 1ms for Kumeran link to come up |
|
3820 * 2) check Kumeran Diagnostic register PCS lock loss bit |
|
3821 * 3) if not set the link is locked (all is good), otherwise... |
|
3822 * 4) reset the PHY |
|
3823 * 5) repeat up to 10 times |
|
3824 * Note: this is only called for IGP3 copper when speed is 1gb. |
|
3825 **/ |
|
3826 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) |
|
3827 { |
|
3828 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
3829 u32 phy_ctrl; |
|
3830 s32 ret_val; |
|
3831 u16 i, data; |
|
3832 bool link; |
|
3833 |
|
3834 if (!dev_spec->kmrn_lock_loss_workaround_enabled) |
|
3835 return 0; |
|
3836 |
|
3837 /* Make sure link is up before proceeding. If not just return. |
|
3838 * Attempting this while link is negotiating fouled up link |
|
3839 * stability |
|
3840 */ |
|
3841 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
3842 if (!link) |
|
3843 return 0; |
|
3844 |
|
3845 for (i = 0; i < 10; i++) { |
|
3846 /* read once to clear */ |
|
3847 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); |
|
3848 if (ret_val) |
|
3849 return ret_val; |
|
3850 /* and again to get new status */ |
|
3851 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); |
|
3852 if (ret_val) |
|
3853 return ret_val; |
|
3854 |
|
3855 /* check for PCS lock */ |
|
3856 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) |
|
3857 return 0; |
|
3858 |
|
3859 /* Issue PHY reset */ |
|
3860 e1000_phy_hw_reset(hw); |
|
3861 mdelay(5); |
|
3862 } |
|
3863 /* Disable GigE link negotiation */ |
|
3864 phy_ctrl = er32(PHY_CTRL); |
|
3865 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | |
|
3866 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
|
3867 ew32(PHY_CTRL, phy_ctrl); |
|
3868 |
|
3869 /* Call gig speed drop workaround on Gig disable before accessing |
|
3870 * any PHY registers |
|
3871 */ |
|
3872 e1000e_gig_downshift_workaround_ich8lan(hw); |
|
3873 |
|
3874 /* unable to acquire PCS lock */ |
|
3875 return -E1000_ERR_PHY; |
|
3876 } |
|
3877 |
|
3878 /** |
|
3879 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
|
3880 * @hw: pointer to the HW structure |
|
3881 * @state: boolean value used to set the current Kumeran workaround state |
|
3882 * |
|
3883 * If ICH8, set the current Kumeran workaround state (enabled - true |
|
3884 * /disabled - false). |
|
3885 **/ |
|
3886 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, |
|
3887 bool state) |
|
3888 { |
|
3889 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
3890 |
|
3891 if (hw->mac.type != e1000_ich8lan) { |
|
3892 e_dbg("Workaround applies to ICH8 only.\n"); |
|
3893 return; |
|
3894 } |
|
3895 |
|
3896 dev_spec->kmrn_lock_loss_workaround_enabled = state; |
|
3897 } |
|
3898 |
|
3899 /** |
|
3900 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 |
|
3901 * @hw: pointer to the HW structure |
|
3902 * |
|
3903 * Workaround for 82566 power-down on D3 entry: |
|
3904 * 1) disable gigabit link |
|
3905 * 2) write VR power-down enable |
|
3906 * 3) read it back |
|
3907 * Continue if successful, else issue LCD reset and repeat |
|
3908 **/ |
|
3909 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) |
|
3910 { |
|
3911 u32 reg; |
|
3912 u16 data; |
|
3913 u8 retry = 0; |
|
3914 |
|
3915 if (hw->phy.type != e1000_phy_igp_3) |
|
3916 return; |
|
3917 |
|
3918 /* Try the workaround twice (if needed) */ |
|
3919 do { |
|
3920 /* Disable link */ |
|
3921 reg = er32(PHY_CTRL); |
|
3922 reg |= (E1000_PHY_CTRL_GBE_DISABLE | |
|
3923 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
|
3924 ew32(PHY_CTRL, reg); |
|
3925 |
|
3926 /* Call gig speed drop workaround on Gig disable before |
|
3927 * accessing any PHY registers |
|
3928 */ |
|
3929 if (hw->mac.type == e1000_ich8lan) |
|
3930 e1000e_gig_downshift_workaround_ich8lan(hw); |
|
3931 |
|
3932 /* Write VR power-down enable */ |
|
3933 e1e_rphy(hw, IGP3_VR_CTRL, &data); |
|
3934 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; |
|
3935 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); |
|
3936 |
|
3937 /* Read it back and test */ |
|
3938 e1e_rphy(hw, IGP3_VR_CTRL, &data); |
|
3939 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; |
|
3940 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) |
|
3941 break; |
|
3942 |
|
3943 /* Issue PHY reset and repeat at most one more time */ |
|
3944 reg = er32(CTRL); |
|
3945 ew32(CTRL, reg | E1000_CTRL_PHY_RST); |
|
3946 retry++; |
|
3947 } while (retry); |
|
3948 } |
|
3949 |
|
3950 /** |
|
3951 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working |
|
3952 * @hw: pointer to the HW structure |
|
3953 * |
|
3954 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), |
|
3955 * LPLU, Gig disable, MDIC PHY reset): |
|
3956 * 1) Set Kumeran Near-end loopback |
|
3957 * 2) Clear Kumeran Near-end loopback |
|
3958 * Should only be called for ICH8[m] devices with any 1G Phy. |
|
3959 **/ |
|
3960 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) |
|
3961 { |
|
3962 s32 ret_val; |
|
3963 u16 reg_data; |
|
3964 |
|
3965 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) |
|
3966 return; |
|
3967 |
|
3968 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
|
3969 ®_data); |
|
3970 if (ret_val) |
|
3971 return; |
|
3972 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; |
|
3973 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
|
3974 reg_data); |
|
3975 if (ret_val) |
|
3976 return; |
|
3977 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; |
|
3978 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
|
3979 reg_data); |
|
3980 } |
|
3981 |
|
3982 /** |
|
3983 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx |
|
3984 * @hw: pointer to the HW structure |
|
3985 * |
|
3986 * During S0 to Sx transition, it is possible the link remains at gig |
|
3987 * instead of negotiating to a lower speed. Before going to Sx, set |
|
3988 * 'Gig Disable' to force link speed negotiation to a lower speed based on |
|
3989 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, |
|
3990 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also |
|
3991 * needs to be written. |
|
3992 * Parts that support (and are linked to a partner which support) EEE in |
|
3993 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power |
|
3994 * than 10Mbps w/o EEE. |
|
3995 **/ |
|
3996 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) |
|
3997 { |
|
3998 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
|
3999 u32 phy_ctrl; |
|
4000 s32 ret_val; |
|
4001 |
|
4002 phy_ctrl = er32(PHY_CTRL); |
|
4003 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; |
|
4004 if (hw->phy.type == e1000_phy_i217) { |
|
4005 u16 phy_reg; |
|
4006 |
|
4007 ret_val = hw->phy.ops.acquire(hw); |
|
4008 if (ret_val) |
|
4009 goto out; |
|
4010 |
|
4011 if (!dev_spec->eee_disable) { |
|
4012 u16 eee_advert; |
|
4013 |
|
4014 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, |
|
4015 I217_EEE_ADVERTISEMENT); |
|
4016 if (ret_val) |
|
4017 goto release; |
|
4018 e1e_rphy_locked(hw, I82579_EMI_DATA, &eee_advert); |
|
4019 |
|
4020 /* Disable LPLU if both link partners support 100BaseT |
|
4021 * EEE and 100Full is advertised on both ends of the |
|
4022 * link. |
|
4023 */ |
|
4024 if ((eee_advert & I217_EEE_100_SUPPORTED) && |
|
4025 (dev_spec->eee_lp_ability & |
|
4026 I217_EEE_100_SUPPORTED) && |
|
4027 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) |
|
4028 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | |
|
4029 E1000_PHY_CTRL_NOND0A_LPLU); |
|
4030 } |
|
4031 |
|
4032 /* For i217 Intel Rapid Start Technology support, |
|
4033 * when the system is going into Sx and no manageability engine |
|
4034 * is present, the driver must configure proxy to reset only on |
|
4035 * power good. LPI (Low Power Idle) state must also reset only |
|
4036 * on power good, as well as the MTA (Multicast table array). |
|
4037 * The SMBus release must also be disabled on LCD reset. |
|
4038 */ |
|
4039 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
|
4040 |
|
4041 /* Enable proxy to reset only on power good. */ |
|
4042 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); |
|
4043 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; |
|
4044 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); |
|
4045 |
|
4046 /* Set bit enable LPI (EEE) to reset only on |
|
4047 * power good. |
|
4048 */ |
|
4049 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); |
|
4050 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; |
|
4051 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); |
|
4052 |
|
4053 /* Disable the SMB release on LCD reset. */ |
|
4054 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); |
|
4055 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; |
|
4056 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); |
|
4057 } |
|
4058 |
|
4059 /* Enable MTA to reset for Intel Rapid Start Technology |
|
4060 * Support |
|
4061 */ |
|
4062 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); |
|
4063 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; |
|
4064 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); |
|
4065 |
|
4066 release: |
|
4067 hw->phy.ops.release(hw); |
|
4068 } |
|
4069 out: |
|
4070 ew32(PHY_CTRL, phy_ctrl); |
|
4071 |
|
4072 if (hw->mac.type == e1000_ich8lan) |
|
4073 e1000e_gig_downshift_workaround_ich8lan(hw); |
|
4074 |
|
4075 if (hw->mac.type >= e1000_pchlan) { |
|
4076 e1000_oem_bits_config_ich8lan(hw, false); |
|
4077 |
|
4078 /* Reset PHY to activate OEM bits on 82577/8 */ |
|
4079 if (hw->mac.type == e1000_pchlan) |
|
4080 e1000e_phy_hw_reset_generic(hw); |
|
4081 |
|
4082 ret_val = hw->phy.ops.acquire(hw); |
|
4083 if (ret_val) |
|
4084 return; |
|
4085 e1000_write_smbus_addr(hw); |
|
4086 hw->phy.ops.release(hw); |
|
4087 } |
|
4088 } |
|
4089 |
|
4090 /** |
|
4091 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 |
|
4092 * @hw: pointer to the HW structure |
|
4093 * |
|
4094 * During Sx to S0 transitions on non-managed devices or managed devices |
|
4095 * on which PHY resets are not blocked, if the PHY registers cannot be |
|
4096 * accessed properly by the s/w toggle the LANPHYPC value to power cycle |
|
4097 * the PHY. |
|
4098 * On i217, setup Intel Rapid Start Technology. |
|
4099 **/ |
|
4100 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) |
|
4101 { |
|
4102 s32 ret_val; |
|
4103 |
|
4104 if (hw->mac.type < e1000_pch2lan) |
|
4105 return; |
|
4106 |
|
4107 ret_val = e1000_init_phy_workarounds_pchlan(hw); |
|
4108 if (ret_val) { |
|
4109 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); |
|
4110 return; |
|
4111 } |
|
4112 |
|
4113 /* For i217 Intel Rapid Start Technology support when the system |
|
4114 * is transitioning from Sx and no manageability engine is present |
|
4115 * configure SMBus to restore on reset, disable proxy, and enable |
|
4116 * the reset on MTA (Multicast table array). |
|
4117 */ |
|
4118 if (hw->phy.type == e1000_phy_i217) { |
|
4119 u16 phy_reg; |
|
4120 |
|
4121 ret_val = hw->phy.ops.acquire(hw); |
|
4122 if (ret_val) { |
|
4123 e_dbg("Failed to setup iRST\n"); |
|
4124 return; |
|
4125 } |
|
4126 |
|
4127 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
|
4128 /* Restore clear on SMB if no manageability engine |
|
4129 * is present |
|
4130 */ |
|
4131 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); |
|
4132 if (ret_val) |
|
4133 goto release; |
|
4134 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; |
|
4135 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); |
|
4136 |
|
4137 /* Disable Proxy */ |
|
4138 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); |
|
4139 } |
|
4140 /* Enable reset on MTA */ |
|
4141 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); |
|
4142 if (ret_val) |
|
4143 goto release; |
|
4144 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; |
|
4145 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); |
|
4146 release: |
|
4147 if (ret_val) |
|
4148 e_dbg("Error %d in resume workarounds\n", ret_val); |
|
4149 hw->phy.ops.release(hw); |
|
4150 } |
|
4151 } |
|
4152 |
|
4153 /** |
|
4154 * e1000_cleanup_led_ich8lan - Restore the default LED operation |
|
4155 * @hw: pointer to the HW structure |
|
4156 * |
|
4157 * Return the LED back to the default configuration. |
|
4158 **/ |
|
4159 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) |
|
4160 { |
|
4161 if (hw->phy.type == e1000_phy_ife) |
|
4162 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); |
|
4163 |
|
4164 ew32(LEDCTL, hw->mac.ledctl_default); |
|
4165 return 0; |
|
4166 } |
|
4167 |
|
4168 /** |
|
4169 * e1000_led_on_ich8lan - Turn LEDs on |
|
4170 * @hw: pointer to the HW structure |
|
4171 * |
|
4172 * Turn on the LEDs. |
|
4173 **/ |
|
4174 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) |
|
4175 { |
|
4176 if (hw->phy.type == e1000_phy_ife) |
|
4177 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
|
4178 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); |
|
4179 |
|
4180 ew32(LEDCTL, hw->mac.ledctl_mode2); |
|
4181 return 0; |
|
4182 } |
|
4183 |
|
4184 /** |
|
4185 * e1000_led_off_ich8lan - Turn LEDs off |
|
4186 * @hw: pointer to the HW structure |
|
4187 * |
|
4188 * Turn off the LEDs. |
|
4189 **/ |
|
4190 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) |
|
4191 { |
|
4192 if (hw->phy.type == e1000_phy_ife) |
|
4193 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
|
4194 (IFE_PSCL_PROBE_MODE | |
|
4195 IFE_PSCL_PROBE_LEDS_OFF)); |
|
4196 |
|
4197 ew32(LEDCTL, hw->mac.ledctl_mode1); |
|
4198 return 0; |
|
4199 } |
|
4200 |
|
4201 /** |
|
4202 * e1000_setup_led_pchlan - Configures SW controllable LED |
|
4203 * @hw: pointer to the HW structure |
|
4204 * |
|
4205 * This prepares the SW controllable LED for use. |
|
4206 **/ |
|
4207 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) |
|
4208 { |
|
4209 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); |
|
4210 } |
|
4211 |
|
4212 /** |
|
4213 * e1000_cleanup_led_pchlan - Restore the default LED operation |
|
4214 * @hw: pointer to the HW structure |
|
4215 * |
|
4216 * Return the LED back to the default configuration. |
|
4217 **/ |
|
4218 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) |
|
4219 { |
|
4220 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); |
|
4221 } |
|
4222 |
|
4223 /** |
|
4224 * e1000_led_on_pchlan - Turn LEDs on |
|
4225 * @hw: pointer to the HW structure |
|
4226 * |
|
4227 * Turn on the LEDs. |
|
4228 **/ |
|
4229 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) |
|
4230 { |
|
4231 u16 data = (u16)hw->mac.ledctl_mode2; |
|
4232 u32 i, led; |
|
4233 |
|
4234 /* If no link, then turn LED on by setting the invert bit |
|
4235 * for each LED that's mode is "link_up" in ledctl_mode2. |
|
4236 */ |
|
4237 if (!(er32(STATUS) & E1000_STATUS_LU)) { |
|
4238 for (i = 0; i < 3; i++) { |
|
4239 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; |
|
4240 if ((led & E1000_PHY_LED0_MODE_MASK) != |
|
4241 E1000_LEDCTL_MODE_LINK_UP) |
|
4242 continue; |
|
4243 if (led & E1000_PHY_LED0_IVRT) |
|
4244 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); |
|
4245 else |
|
4246 data |= (E1000_PHY_LED0_IVRT << (i * 5)); |
|
4247 } |
|
4248 } |
|
4249 |
|
4250 return e1e_wphy(hw, HV_LED_CONFIG, data); |
|
4251 } |
|
4252 |
|
4253 /** |
|
4254 * e1000_led_off_pchlan - Turn LEDs off |
|
4255 * @hw: pointer to the HW structure |
|
4256 * |
|
4257 * Turn off the LEDs. |
|
4258 **/ |
|
4259 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) |
|
4260 { |
|
4261 u16 data = (u16)hw->mac.ledctl_mode1; |
|
4262 u32 i, led; |
|
4263 |
|
4264 /* If no link, then turn LED off by clearing the invert bit |
|
4265 * for each LED that's mode is "link_up" in ledctl_mode1. |
|
4266 */ |
|
4267 if (!(er32(STATUS) & E1000_STATUS_LU)) { |
|
4268 for (i = 0; i < 3; i++) { |
|
4269 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; |
|
4270 if ((led & E1000_PHY_LED0_MODE_MASK) != |
|
4271 E1000_LEDCTL_MODE_LINK_UP) |
|
4272 continue; |
|
4273 if (led & E1000_PHY_LED0_IVRT) |
|
4274 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); |
|
4275 else |
|
4276 data |= (E1000_PHY_LED0_IVRT << (i * 5)); |
|
4277 } |
|
4278 } |
|
4279 |
|
4280 return e1e_wphy(hw, HV_LED_CONFIG, data); |
|
4281 } |
|
4282 |
|
4283 /** |
|
4284 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset |
|
4285 * @hw: pointer to the HW structure |
|
4286 * |
|
4287 * Read appropriate register for the config done bit for completion status |
|
4288 * and configure the PHY through s/w for EEPROM-less parts. |
|
4289 * |
|
4290 * NOTE: some silicon which is EEPROM-less will fail trying to read the |
|
4291 * config done bit, so only an error is logged and continues. If we were |
|
4292 * to return with error, EEPROM-less silicon would not be able to be reset |
|
4293 * or change link. |
|
4294 **/ |
|
4295 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) |
|
4296 { |
|
4297 s32 ret_val = 0; |
|
4298 u32 bank = 0; |
|
4299 u32 status; |
|
4300 |
|
4301 e1000e_get_cfg_done(hw); |
|
4302 |
|
4303 /* Wait for indication from h/w that it has completed basic config */ |
|
4304 if (hw->mac.type >= e1000_ich10lan) { |
|
4305 e1000_lan_init_done_ich8lan(hw); |
|
4306 } else { |
|
4307 ret_val = e1000e_get_auto_rd_done(hw); |
|
4308 if (ret_val) { |
|
4309 /* When auto config read does not complete, do not |
|
4310 * return with an error. This can happen in situations |
|
4311 * where there is no eeprom and prevents getting link. |
|
4312 */ |
|
4313 e_dbg("Auto Read Done did not complete\n"); |
|
4314 ret_val = 0; |
|
4315 } |
|
4316 } |
|
4317 |
|
4318 /* Clear PHY Reset Asserted bit */ |
|
4319 status = er32(STATUS); |
|
4320 if (status & E1000_STATUS_PHYRA) |
|
4321 ew32(STATUS, status & ~E1000_STATUS_PHYRA); |
|
4322 else |
|
4323 e_dbg("PHY Reset Asserted not set - needs delay\n"); |
|
4324 |
|
4325 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ |
|
4326 if (hw->mac.type <= e1000_ich9lan) { |
|
4327 if (!(er32(EECD) & E1000_EECD_PRES) && |
|
4328 (hw->phy.type == e1000_phy_igp_3)) { |
|
4329 e1000e_phy_init_script_igp3(hw); |
|
4330 } |
|
4331 } else { |
|
4332 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { |
|
4333 /* Maybe we should do a basic PHY config */ |
|
4334 e_dbg("EEPROM not present\n"); |
|
4335 ret_val = -E1000_ERR_CONFIG; |
|
4336 } |
|
4337 } |
|
4338 |
|
4339 return ret_val; |
|
4340 } |
|
4341 |
|
4342 /** |
|
4343 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down |
|
4344 * @hw: pointer to the HW structure |
|
4345 * |
|
4346 * In the case of a PHY power down to save power, or to turn off link during a |
|
4347 * driver unload, or wake on lan is not enabled, remove the link. |
|
4348 **/ |
|
4349 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) |
|
4350 { |
|
4351 /* If the management interface is not enabled, then power down */ |
|
4352 if (!(hw->mac.ops.check_mng_mode(hw) || |
|
4353 hw->phy.ops.check_reset_block(hw))) |
|
4354 e1000_power_down_phy_copper(hw); |
|
4355 } |
|
4356 |
|
4357 /** |
|
4358 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters |
|
4359 * @hw: pointer to the HW structure |
|
4360 * |
|
4361 * Clears hardware counters specific to the silicon family and calls |
|
4362 * clear_hw_cntrs_generic to clear all general purpose counters. |
|
4363 **/ |
|
4364 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) |
|
4365 { |
|
4366 u16 phy_data; |
|
4367 s32 ret_val; |
|
4368 |
|
4369 e1000e_clear_hw_cntrs_base(hw); |
|
4370 |
|
4371 er32(ALGNERRC); |
|
4372 er32(RXERRC); |
|
4373 er32(TNCRS); |
|
4374 er32(CEXTERR); |
|
4375 er32(TSCTC); |
|
4376 er32(TSCTFC); |
|
4377 |
|
4378 er32(MGTPRC); |
|
4379 er32(MGTPDC); |
|
4380 er32(MGTPTC); |
|
4381 |
|
4382 er32(IAC); |
|
4383 er32(ICRXOC); |
|
4384 |
|
4385 /* Clear PHY statistics registers */ |
|
4386 if ((hw->phy.type == e1000_phy_82578) || |
|
4387 (hw->phy.type == e1000_phy_82579) || |
|
4388 (hw->phy.type == e1000_phy_i217) || |
|
4389 (hw->phy.type == e1000_phy_82577)) { |
|
4390 ret_val = hw->phy.ops.acquire(hw); |
|
4391 if (ret_val) |
|
4392 return; |
|
4393 ret_val = hw->phy.ops.set_page(hw, |
|
4394 HV_STATS_PAGE << IGP_PAGE_SHIFT); |
|
4395 if (ret_val) |
|
4396 goto release; |
|
4397 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); |
|
4398 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); |
|
4399 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); |
|
4400 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); |
|
4401 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); |
|
4402 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); |
|
4403 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); |
|
4404 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); |
|
4405 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); |
|
4406 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); |
|
4407 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); |
|
4408 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); |
|
4409 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); |
|
4410 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); |
|
4411 release: |
|
4412 hw->phy.ops.release(hw); |
|
4413 } |
|
4414 } |
|
4415 |
|
4416 static const struct e1000_mac_operations ich8_mac_ops = { |
|
4417 /* check_mng_mode dependent on mac type */ |
|
4418 .check_for_link = e1000_check_for_copper_link_ich8lan, |
|
4419 /* cleanup_led dependent on mac type */ |
|
4420 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, |
|
4421 .get_bus_info = e1000_get_bus_info_ich8lan, |
|
4422 .set_lan_id = e1000_set_lan_id_single_port, |
|
4423 .get_link_up_info = e1000_get_link_up_info_ich8lan, |
|
4424 /* led_on dependent on mac type */ |
|
4425 /* led_off dependent on mac type */ |
|
4426 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
|
4427 .reset_hw = e1000_reset_hw_ich8lan, |
|
4428 .init_hw = e1000_init_hw_ich8lan, |
|
4429 .setup_link = e1000_setup_link_ich8lan, |
|
4430 .setup_physical_interface= e1000_setup_copper_link_ich8lan, |
|
4431 /* id_led_init dependent on mac type */ |
|
4432 .config_collision_dist = e1000e_config_collision_dist_generic, |
|
4433 .rar_set = e1000e_rar_set_generic, |
|
4434 }; |
|
4435 |
|
4436 static const struct e1000_phy_operations ich8_phy_ops = { |
|
4437 .acquire = e1000_acquire_swflag_ich8lan, |
|
4438 .check_reset_block = e1000_check_reset_block_ich8lan, |
|
4439 .commit = NULL, |
|
4440 .get_cfg_done = e1000_get_cfg_done_ich8lan, |
|
4441 .get_cable_length = e1000e_get_cable_length_igp_2, |
|
4442 .read_reg = e1000e_read_phy_reg_igp, |
|
4443 .release = e1000_release_swflag_ich8lan, |
|
4444 .reset = e1000_phy_hw_reset_ich8lan, |
|
4445 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, |
|
4446 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, |
|
4447 .write_reg = e1000e_write_phy_reg_igp, |
|
4448 }; |
|
4449 |
|
4450 static const struct e1000_nvm_operations ich8_nvm_ops = { |
|
4451 .acquire = e1000_acquire_nvm_ich8lan, |
|
4452 .read = e1000_read_nvm_ich8lan, |
|
4453 .release = e1000_release_nvm_ich8lan, |
|
4454 .reload = e1000e_reload_nvm_generic, |
|
4455 .update = e1000_update_nvm_checksum_ich8lan, |
|
4456 .valid_led_default = e1000_valid_led_default_ich8lan, |
|
4457 .validate = e1000_validate_nvm_checksum_ich8lan, |
|
4458 .write = e1000_write_nvm_ich8lan, |
|
4459 }; |
|
4460 |
|
4461 const struct e1000_info e1000_ich8_info = { |
|
4462 .mac = e1000_ich8lan, |
|
4463 .flags = FLAG_HAS_WOL |
|
4464 | FLAG_IS_ICH |
|
4465 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
4466 | FLAG_HAS_AMT |
|
4467 | FLAG_HAS_FLASH |
|
4468 | FLAG_APME_IN_WUC, |
|
4469 .pba = 8, |
|
4470 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
|
4471 .get_variants = e1000_get_variants_ich8lan, |
|
4472 .mac_ops = &ich8_mac_ops, |
|
4473 .phy_ops = &ich8_phy_ops, |
|
4474 .nvm_ops = &ich8_nvm_ops, |
|
4475 }; |
|
4476 |
|
4477 const struct e1000_info e1000_ich9_info = { |
|
4478 .mac = e1000_ich9lan, |
|
4479 .flags = FLAG_HAS_JUMBO_FRAMES |
|
4480 | FLAG_IS_ICH |
|
4481 | FLAG_HAS_WOL |
|
4482 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
4483 | FLAG_HAS_AMT |
|
4484 | FLAG_HAS_FLASH |
|
4485 | FLAG_APME_IN_WUC, |
|
4486 .pba = 18, |
|
4487 .max_hw_frame_size = DEFAULT_JUMBO, |
|
4488 .get_variants = e1000_get_variants_ich8lan, |
|
4489 .mac_ops = &ich8_mac_ops, |
|
4490 .phy_ops = &ich8_phy_ops, |
|
4491 .nvm_ops = &ich8_nvm_ops, |
|
4492 }; |
|
4493 |
|
4494 const struct e1000_info e1000_ich10_info = { |
|
4495 .mac = e1000_ich10lan, |
|
4496 .flags = FLAG_HAS_JUMBO_FRAMES |
|
4497 | FLAG_IS_ICH |
|
4498 | FLAG_HAS_WOL |
|
4499 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
4500 | FLAG_HAS_AMT |
|
4501 | FLAG_HAS_FLASH |
|
4502 | FLAG_APME_IN_WUC, |
|
4503 .pba = 18, |
|
4504 .max_hw_frame_size = DEFAULT_JUMBO, |
|
4505 .get_variants = e1000_get_variants_ich8lan, |
|
4506 .mac_ops = &ich8_mac_ops, |
|
4507 .phy_ops = &ich8_phy_ops, |
|
4508 .nvm_ops = &ich8_nvm_ops, |
|
4509 }; |
|
4510 |
|
4511 const struct e1000_info e1000_pch_info = { |
|
4512 .mac = e1000_pchlan, |
|
4513 .flags = FLAG_IS_ICH |
|
4514 | FLAG_HAS_WOL |
|
4515 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
4516 | FLAG_HAS_AMT |
|
4517 | FLAG_HAS_FLASH |
|
4518 | FLAG_HAS_JUMBO_FRAMES |
|
4519 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ |
|
4520 | FLAG_APME_IN_WUC, |
|
4521 .flags2 = FLAG2_HAS_PHY_STATS, |
|
4522 .pba = 26, |
|
4523 .max_hw_frame_size = 4096, |
|
4524 .get_variants = e1000_get_variants_ich8lan, |
|
4525 .mac_ops = &ich8_mac_ops, |
|
4526 .phy_ops = &ich8_phy_ops, |
|
4527 .nvm_ops = &ich8_nvm_ops, |
|
4528 }; |
|
4529 |
|
4530 const struct e1000_info e1000_pch2_info = { |
|
4531 .mac = e1000_pch2lan, |
|
4532 .flags = FLAG_IS_ICH |
|
4533 | FLAG_HAS_WOL |
|
4534 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
4535 | FLAG_HAS_AMT |
|
4536 | FLAG_HAS_FLASH |
|
4537 | FLAG_HAS_JUMBO_FRAMES |
|
4538 | FLAG_APME_IN_WUC, |
|
4539 .flags2 = FLAG2_HAS_PHY_STATS |
|
4540 | FLAG2_HAS_EEE, |
|
4541 .pba = 26, |
|
4542 .max_hw_frame_size = DEFAULT_JUMBO, |
|
4543 .get_variants = e1000_get_variants_ich8lan, |
|
4544 .mac_ops = &ich8_mac_ops, |
|
4545 .phy_ops = &ich8_phy_ops, |
|
4546 .nvm_ops = &ich8_nvm_ops, |
|
4547 }; |
|
4548 |
|
4549 const struct e1000_info e1000_pch_lpt_info = { |
|
4550 .mac = e1000_pch_lpt, |
|
4551 .flags = FLAG_IS_ICH |
|
4552 | FLAG_HAS_WOL |
|
4553 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
4554 | FLAG_HAS_AMT |
|
4555 | FLAG_HAS_FLASH |
|
4556 | FLAG_HAS_JUMBO_FRAMES |
|
4557 | FLAG_APME_IN_WUC, |
|
4558 .flags2 = FLAG2_HAS_PHY_STATS |
|
4559 | FLAG2_HAS_EEE, |
|
4560 .pba = 26, |
|
4561 .max_hw_frame_size = DEFAULT_JUMBO, |
|
4562 .get_variants = e1000_get_variants_ich8lan, |
|
4563 .mac_ops = &ich8_mac_ops, |
|
4564 .phy_ops = &ich8_phy_ops, |
|
4565 .nvm_ops = &ich8_nvm_ops, |
|
4566 }; |