1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2013 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* 82562G 10/100 Network Connection

    30  * 82562G-2 10/100 Network Connection

    31  * 82562GT 10/100 Network Connection

    32  * 82562GT-2 10/100 Network Connection

    33  * 82562V 10/100 Network Connection

    34  * 82562V-2 10/100 Network Connection

    35  * 82566DC-2 Gigabit Network Connection

    36  * 82566DC Gigabit Network Connection

    37  * 82566DM-2 Gigabit Network Connection

    38  * 82566DM Gigabit Network Connection

    39  * 82566MC Gigabit Network Connection

    40  * 82566MM Gigabit Network Connection

    41  * 82567LM Gigabit Network Connection

    42  * 82567LF Gigabit Network Connection

    43  * 82567V Gigabit Network Connection

    44  * 82567LM-2 Gigabit Network Connection

    45  * 82567LF-2 Gigabit Network Connection

    46  * 82567V-2 Gigabit Network Connection

    47  * 82567LF-3 Gigabit Network Connection

    48  * 82567LM-3 Gigabit Network Connection

    49  * 82567LM-4 Gigabit Network Connection

    50  * 82577LM Gigabit Network Connection

    51  * 82577LC Gigabit Network Connection

    52  * 82578DM Gigabit Network Connection

    53  * 82578DC Gigabit Network Connection

    54  * 82579LM Gigabit Network Connection

    55  * 82579V Gigabit Network Connection

    56  */

    57 

    58 #include "e1000.h"

    59 

    60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

    61 /* Offset 04h HSFSTS */

    62 union ich8_hws_flash_status {

    63 	struct ich8_hsfsts {

    64 		u16 flcdone:1;	/* bit 0 Flash Cycle Done */

    65 		u16 flcerr:1;	/* bit 1 Flash Cycle Error */

    66 		u16 dael:1;	/* bit 2 Direct Access error Log */

    67 		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */

    68 		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */

    69 		u16 reserved1:2;	/* bit 13:6 Reserved */

    70 		u16 reserved2:6;	/* bit 13:6 Reserved */

    71 		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */

    72 		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */

    73 	} hsf_status;

    74 	u16 regval;

    75 };

    76 

    77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

    78 /* Offset 06h FLCTL */

    79 union ich8_hws_flash_ctrl {

    80 	struct ich8_hsflctl {

    81 		u16 flcgo:1;	/* 0 Flash Cycle Go */

    82 		u16 flcycle:2;	/* 2:1 Flash Cycle */

    83 		u16 reserved:5;	/* 7:3 Reserved  */

    84 		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */

    85 		u16 flockdn:6;	/* 15:10 Reserved */

    86 	} hsf_ctrl;

    87 	u16 regval;

    88 };

    89 

    90 /* ICH Flash Region Access Permissions */

    91 union ich8_hws_flash_regacc {

    92 	struct ich8_flracc {

    93 		u32 grra:8;	/* 0:7 GbE region Read Access */

    94 		u32 grwa:8;	/* 8:15 GbE region Write Access */

    95 		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */

    96 		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */

    97 	} hsf_flregacc;

    98 	u16 regval;

    99 };

   100 

   101 /* ICH Flash Protected Region */

   102 union ich8_flash_protected_range {

   103 	struct ich8_pr {

   104 		u32 base:13;	/* 0:12 Protected Range Base */

   105 		u32 reserved1:2;	/* 13:14 Reserved */

   106 		u32 rpe:1;	/* 15 Read Protection Enable */

   107 		u32 limit:13;	/* 16:28 Protected Range Limit */

   108 		u32 reserved2:2;	/* 29:30 Reserved */

   109 		u32 wpe:1;	/* 31 Write Protection Enable */

   110 	} range;

   111 	u32 regval;

   112 };

   113 

   114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   118 						u32 offset, u8 byte);

   119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   120 					 u8 *data);

   121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   122 					 u16 *data);

   123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   124 					 u8 size, u16 *data);

   125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

   142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

   143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   145 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);

   146 

   147 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   148 {

   149 	return readw(hw->flash_address + reg);

   150 }

   151 

   152 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   153 {

   154 	return readl(hw->flash_address + reg);

   155 }

   156 

   157 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   158 {

   159 	writew(val, hw->flash_address + reg);

   160 }

   161 

   162 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   163 {

   164 	writel(val, hw->flash_address + reg);

   165 }

   166 

   167 #define er16flash(reg)		__er16flash(hw, (reg))

   168 #define er32flash(reg)		__er32flash(hw, (reg))

   169 #define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

   170 #define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   171 

   172 /**

   173  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers

   174  *  @hw: pointer to the HW structure

   175  *

   176  *  Test access to the PHY registers by reading the PHY ID registers.  If

   177  *  the PHY ID is already known (e.g. resume path) compare it with known ID,

   178  *  otherwise assume the read PHY ID is correct if it is valid.

   179  *

   180  *  Assumes the sw/fw/hw semaphore is already acquired.

   181  **/

   182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)

   183 {

   184 	u16 phy_reg = 0;

   185 	u32 phy_id = 0;

   186 	s32 ret_val;

   187 	u16 retry_count;

   188 	u32 mac_reg = 0;

   189 

   190 	for (retry_count = 0; retry_count < 2; retry_count++) {

   191 		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);

   192 		if (ret_val || (phy_reg == 0xFFFF))

   193 			continue;

   194 		phy_id = (u32)(phy_reg << 16);

   195 

   196 		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);

   197 		if (ret_val || (phy_reg == 0xFFFF)) {

   198 			phy_id = 0;

   199 			continue;

   200 		}

   201 		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

   202 		break;

   203 	}

   204 

   205 	if (hw->phy.id) {

   206 		if (hw->phy.id == phy_id)

   207 			goto out;

   208 	} else if (phy_id) {

   209 		hw->phy.id = phy_id;

   210 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

   211 		goto out;

   212 	}

   213 

   214 	/* In case the PHY needs to be in mdio slow mode,

   215 	 * set slow mode and try to get the PHY id again.

   216 	 */

   217 	hw->phy.ops.release(hw);

   218 	ret_val = e1000_set_mdio_slow_mode_hv(hw);

   219 	if (!ret_val)

   220 		ret_val = e1000e_get_phy_id(hw);

   221 	hw->phy.ops.acquire(hw);

   222 

   223 	if (ret_val)

   224 		return false;

   225 out:

   226 	if (hw->mac.type == e1000_pch_lpt) {

   227 		/* Unforce SMBus mode in PHY */

   228 		e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);

   229 		phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;

   230 		e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

   231 

   232 		/* Unforce SMBus mode in MAC */

   233 		mac_reg = er32(CTRL_EXT);

   234 		mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   235 		ew32(CTRL_EXT, mac_reg);

   236 	}

   237 

   238 	return true;

   239 }

   240 

   241 /**

   242  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds

   243  *  @hw: pointer to the HW structure

   244  *

   245  *  Workarounds/flow necessary for PHY initialization during driver load

   246  *  and resume paths.

   247  **/

   248 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

   249 {

   250 	u32 mac_reg, fwsm = er32(FWSM);

   251 	s32 ret_val;

   252 

   253 	/* Gate automatic PHY configuration by hardware on managed and

   254 	 * non-managed 82579 and newer adapters.

   255 	 */

   256 	e1000_gate_hw_phy_config_ich8lan(hw, true);

   257 

   258 	ret_val = hw->phy.ops.acquire(hw);

   259 	if (ret_val) {

   260 		e_dbg("Failed to initialize PHY flow\n");

   261 		goto out;

   262 	}

   263 

   264 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is

   265 	 * inaccessible and resetting the PHY is not blocked, toggle the

   266 	 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   267 	 */

   268 	switch (hw->mac.type) {

   269 	case e1000_pch_lpt:

   270 		if (e1000_phy_is_accessible_pchlan(hw))

   271 			break;

   272 

   273 		/* Before toggling LANPHYPC, see if PHY is accessible by

   274 		 * forcing MAC to SMBus mode first.

   275 		 */

   276 		mac_reg = er32(CTRL_EXT);

   277 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

   278 		ew32(CTRL_EXT, mac_reg);

   279 

   280 		/* Wait 50 milliseconds for MAC to finish any retries

   281 		 * that it might be trying to perform from previous

   282 		 * attempts to acknowledge any phy read requests.

   283 		 */

   284 		msleep(50);

   285 

   286 		/* fall-through */

   287 	case e1000_pch2lan:

   288 		if (e1000_phy_is_accessible_pchlan(hw))

   289 			break;

   290 

   291 		/* fall-through */

   292 	case e1000_pchlan:

   293 		if ((hw->mac.type == e1000_pchlan) &&

   294 		    (fwsm & E1000_ICH_FWSM_FW_VALID))

   295 			break;

   296 

   297 		if (hw->phy.ops.check_reset_block(hw)) {

   298 			e_dbg("Required LANPHYPC toggle blocked by ME\n");

   299 			ret_val = -E1000_ERR_PHY;

   300 			break;

   301 		}

   302 

   303 		e_dbg("Toggling LANPHYPC\n");

   304 

   305 		/* Set Phy Config Counter to 50msec */

   306 		mac_reg = er32(FEXTNVM3);

   307 		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

   308 		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

   309 		ew32(FEXTNVM3, mac_reg);

   310 

   311 		/* Toggle LANPHYPC Value bit */

   312 		mac_reg = er32(CTRL);

   313 		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;

   314 		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

   315 		ew32(CTRL, mac_reg);

   316 		e1e_flush();

   317 		usleep_range(10, 20);

   318 		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   319 		ew32(CTRL, mac_reg);

   320 		e1e_flush();

   321 		if (hw->mac.type < e1000_pch_lpt) {

   322 			msleep(50);

   323 		} else {

   324 			u16 count = 20;

   325 			do {

   326 				usleep_range(5000, 10000);

   327 			} while (!(er32(CTRL_EXT) &

   328 				   E1000_CTRL_EXT_LPCD) && count--);

   329 			usleep_range(30000, 60000);

   330 			if (e1000_phy_is_accessible_pchlan(hw))

   331 				break;

   332 

   333 			/* Toggling LANPHYPC brings the PHY out of SMBus mode

   334 			 * so ensure that the MAC is also out of SMBus mode

   335 			 */

   336 			mac_reg = er32(CTRL_EXT);

   337 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   338 			ew32(CTRL_EXT, mac_reg);

   339 

   340 			if (e1000_phy_is_accessible_pchlan(hw))

   341 				break;

   342 

   343 			ret_val = -E1000_ERR_PHY;

   344 		}

   345 		break;

   346 	default:

   347 		break;

   348 	}

   349 

   350 	hw->phy.ops.release(hw);

   351 	if (!ret_val) {

   352 		/* Reset the PHY before any access to it.  Doing so, ensures

   353 		 * that the PHY is in a known good state before we read/write

   354 		 * PHY registers.  The generic reset is sufficient here,

   355 		 * because we haven't determined the PHY type yet.

   356 		 */

   357 		ret_val = e1000e_phy_hw_reset_generic(hw);

   358 	}

   359 

   360 out:

   361 	/* Ungate automatic PHY configuration on non-managed 82579 */

   362 	if ((hw->mac.type == e1000_pch2lan) &&

   363 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   364 		usleep_range(10000, 20000);

   365 		e1000_gate_hw_phy_config_ich8lan(hw, false);

   366 	}

   367 

   368 	return ret_val;

   369 }

   370 

   371 /**

   372  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   373  *  @hw: pointer to the HW structure

   374  *

   375  *  Initialize family-specific PHY parameters and function pointers.

   376  **/

   377 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   378 {

   379 	struct e1000_phy_info *phy = &hw->phy;

   380 	s32 ret_val;

   381 

   382 	phy->addr = 1;

   383 	phy->reset_delay_us = 100;

   384 

   385 	phy->ops.set_page = e1000_set_page_igp;

   386 	phy->ops.read_reg = e1000_read_phy_reg_hv;

   387 	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;

   388 	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;

   389 	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;

   390 	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;

   391 	phy->ops.write_reg = e1000_write_phy_reg_hv;

   392 	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;

   393 	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;

   394 	phy->ops.power_up = e1000_power_up_phy_copper;

   395 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

   396 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   397 

   398 	phy->id = e1000_phy_unknown;

   399 

   400 	ret_val = e1000_init_phy_workarounds_pchlan(hw);

   401 	if (ret_val)

   402 		return ret_val;

   403 

   404 	if (phy->id == e1000_phy_unknown)

   405 		switch (hw->mac.type) {

   406 		default:

   407 			ret_val = e1000e_get_phy_id(hw);

   408 			if (ret_val)

   409 				return ret_val;

   410 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   411 				break;

   412 			/* fall-through */

   413 		case e1000_pch2lan:

   414 		case e1000_pch_lpt:

   415 			/* In case the PHY needs to be in mdio slow mode,

   416 			 * set slow mode and try to get the PHY id again.

   417 			 */

   418 			ret_val = e1000_set_mdio_slow_mode_hv(hw);

   419 			if (ret_val)

   420 				return ret_val;

   421 			ret_val = e1000e_get_phy_id(hw);

   422 			if (ret_val)

   423 				return ret_val;

   424 			break;

   425 		}

   426 	phy->type = e1000e_get_phy_type_from_id(phy->id);

   427 

   428 	switch (phy->type) {

   429 	case e1000_phy_82577:

   430 	case e1000_phy_82579:

   431 	case e1000_phy_i217:

   432 		phy->ops.check_polarity = e1000_check_polarity_82577;

   433 		phy->ops.force_speed_duplex =

   434 		    e1000_phy_force_speed_duplex_82577;

   435 		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   436 		phy->ops.get_info = e1000_get_phy_info_82577;

   437 		phy->ops.commit = e1000e_phy_sw_reset;

   438 		break;

   439 	case e1000_phy_82578:

   440 		phy->ops.check_polarity = e1000_check_polarity_m88;

   441 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   442 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   443 		phy->ops.get_info = e1000e_get_phy_info_m88;

   444 		break;

   445 	default:

   446 		ret_val = -E1000_ERR_PHY;

   447 		break;

   448 	}

   449 

   450 	return ret_val;

   451 }

   452 

   453 /**

   454  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   455  *  @hw: pointer to the HW structure

   456  *

   457  *  Initialize family-specific PHY parameters and function pointers.

   458  **/

   459 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   460 {

   461 	struct e1000_phy_info *phy = &hw->phy;

   462 	s32 ret_val;

   463 	u16 i = 0;

   464 

   465 	phy->addr = 1;

   466 	phy->reset_delay_us = 100;

   467 

   468 	phy->ops.power_up = e1000_power_up_phy_copper;

   469 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

   470 

   471 	/* We may need to do this twice - once for IGP and if that fails,

   472 	 * we'll set BM func pointers and try again

   473 	 */

   474 	ret_val = e1000e_determine_phy_address(hw);

   475 	if (ret_val) {

   476 		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   477 		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   478 		ret_val = e1000e_determine_phy_address(hw);

   479 		if (ret_val) {

   480 			e_dbg("Cannot determine PHY addr. Erroring out\n");

   481 			return ret_val;

   482 		}

   483 	}

   484 

   485 	phy->id = 0;

   486 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   487 	       (i++ < 100)) {

   488 		usleep_range(1000, 2000);

   489 		ret_val = e1000e_get_phy_id(hw);

   490 		if (ret_val)

   491 			return ret_val;

   492 	}

   493 

   494 	/* Verify phy id */

   495 	switch (phy->id) {

   496 	case IGP03E1000_E_PHY_ID:

   497 		phy->type = e1000_phy_igp_3;

   498 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   499 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   500 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   501 		phy->ops.get_info = e1000e_get_phy_info_igp;

   502 		phy->ops.check_polarity = e1000_check_polarity_igp;

   503 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   504 		break;

   505 	case IFE_E_PHY_ID:

   506 	case IFE_PLUS_E_PHY_ID:

   507 	case IFE_C_E_PHY_ID:

   508 		phy->type = e1000_phy_ife;

   509 		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   510 		phy->ops.get_info = e1000_get_phy_info_ife;

   511 		phy->ops.check_polarity = e1000_check_polarity_ife;

   512 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   513 		break;

   514 	case BME1000_E_PHY_ID:

   515 		phy->type = e1000_phy_bm;

   516 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   517 		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   518 		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   519 		phy->ops.commit = e1000e_phy_sw_reset;

   520 		phy->ops.get_info = e1000e_get_phy_info_m88;

   521 		phy->ops.check_polarity = e1000_check_polarity_m88;

   522 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   523 		break;

   524 	default:

   525 		return -E1000_ERR_PHY;

   526 		break;

   527 	}

   528 

   529 	return 0;

   530 }

   531 

   532 /**

   533  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   534  *  @hw: pointer to the HW structure

   535  *

   536  *  Initialize family-specific NVM parameters and function

   537  *  pointers.

   538  **/

   539 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   540 {

   541 	struct e1000_nvm_info *nvm = &hw->nvm;

   542 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   543 	u32 gfpreg, sector_base_addr, sector_end_addr;

   544 	u16 i;

   545 

   546 	/* Can't read flash registers if the register set isn't mapped. */

   547 	if (!hw->flash_address) {

   548 		e_dbg("ERROR: Flash registers not mapped\n");

   549 		return -E1000_ERR_CONFIG;

   550 	}

   551 

   552 	nvm->type = e1000_nvm_flash_sw;

   553 

   554 	gfpreg = er32flash(ICH_FLASH_GFPREG);

   555 

   556 	/* sector_X_addr is a "sector"-aligned address (4096 bytes)

   557 	 * Add 1 to sector_end_addr since this sector is included in

   558 	 * the overall size.

   559 	 */

   560 	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   561 	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   562 

   563 	/* flash_base_addr is byte-aligned */

   564 	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   565 

   566 	/* find total size of the NVM, then cut in half since the total

   567 	 * size represents two separate NVM banks.

   568 	 */

   569 	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)

   570 				<< FLASH_SECTOR_ADDR_SHIFT);

   571 	nvm->flash_bank_size /= 2;

   572 	/* Adjust to word count */

   573 	nvm->flash_bank_size /= sizeof(u16);

   574 

   575 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;

   576 

   577 	/* Clear shadow ram */

   578 	for (i = 0; i < nvm->word_size; i++) {

   579 		dev_spec->shadow_ram[i].modified = false;

   580 		dev_spec->shadow_ram[i].value = 0xFFFF;

   581 	}

   582 

   583 	return 0;

   584 }

   585 

   586 /**

   587  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers

   588  *  @hw: pointer to the HW structure

   589  *

   590  *  Initialize family-specific MAC parameters and function

   591  *  pointers.

   592  **/

   593 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)

   594 {

   595 	struct e1000_mac_info *mac = &hw->mac;

   596 

   597 	/* Set media type function pointer */

   598 	hw->phy.media_type = e1000_media_type_copper;

   599 

   600 	/* Set mta register count */

   601 	mac->mta_reg_count = 32;

   602 	/* Set rar entry count */

   603 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;

   604 	if (mac->type == e1000_ich8lan)

   605 		mac->rar_entry_count--;

   606 	/* FWSM register */

   607 	mac->has_fwsm = true;

   608 	/* ARC subsystem not supported */

   609 	mac->arc_subsystem_valid = false;

   610 	/* Adaptive IFS supported */

   611 	mac->adaptive_ifs = true;

   612 

   613 	/* LED and other operations */

   614 	switch (mac->type) {

   615 	case e1000_ich8lan:

   616 	case e1000_ich9lan:

   617 	case e1000_ich10lan:

   618 		/* check management mode */

   619 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;

   620 		/* ID LED init */

   621 		mac->ops.id_led_init = e1000e_id_led_init_generic;

   622 		/* blink LED */

   623 		mac->ops.blink_led = e1000e_blink_led_generic;

   624 		/* setup LED */

   625 		mac->ops.setup_led = e1000e_setup_led_generic;

   626 		/* cleanup LED */

   627 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;

   628 		/* turn on/off LED */

   629 		mac->ops.led_on = e1000_led_on_ich8lan;

   630 		mac->ops.led_off = e1000_led_off_ich8lan;

   631 		break;

   632 	case e1000_pch2lan:

   633 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;

   634 		mac->ops.rar_set = e1000_rar_set_pch2lan;

   635 		/* fall-through */

   636 	case e1000_pch_lpt:

   637 	case e1000_pchlan:

   638 		/* check management mode */

   639 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;

   640 		/* ID LED init */

   641 		mac->ops.id_led_init = e1000_id_led_init_pchlan;

   642 		/* setup LED */

   643 		mac->ops.setup_led = e1000_setup_led_pchlan;

   644 		/* cleanup LED */

   645 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;

   646 		/* turn on/off LED */

   647 		mac->ops.led_on = e1000_led_on_pchlan;

   648 		mac->ops.led_off = e1000_led_off_pchlan;

   649 		break;

   650 	default:

   651 		break;

   652 	}

   653 

   654 	if (mac->type == e1000_pch_lpt) {

   655 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;

   656 		mac->ops.rar_set = e1000_rar_set_pch_lpt;

   657 		mac->ops.setup_physical_interface =

   658 		    e1000_setup_copper_link_pch_lpt;

   659 	}

   660 

   661 	/* Enable PCS Lock-loss workaround for ICH8 */

   662 	if (mac->type == e1000_ich8lan)

   663 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);

   664 

   665 	return 0;

   666 }

   667 

   668 /**

   669  *  __e1000_access_emi_reg_locked - Read/write EMI register

   670  *  @hw: pointer to the HW structure

   671  *  @addr: EMI address to program

   672  *  @data: pointer to value to read/write from/to the EMI address

   673  *  @read: boolean flag to indicate read or write

   674  *

   675  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.

   676  **/

   677 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,

   678 					 u16 *data, bool read)

   679 {

   680 	s32 ret_val;

   681 

   682 	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);

   683 	if (ret_val)

   684 		return ret_val;

   685 

   686 	if (read)

   687 		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);

   688 	else

   689 		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);

   690 

   691 	return ret_val;

   692 }

   693 

   694 /**

   695  *  e1000_read_emi_reg_locked - Read Extended Management Interface register

   696  *  @hw: pointer to the HW structure

   697  *  @addr: EMI address to program

   698  *  @data: value to be read from the EMI address

   699  *

   700  *  Assumes the SW/FW/HW Semaphore is already acquired.

   701  **/

   702 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)

   703 {

   704 	return __e1000_access_emi_reg_locked(hw, addr, data, true);

   705 }

   706 

   707 /**

   708  *  e1000_write_emi_reg_locked - Write Extended Management Interface register

   709  *  @hw: pointer to the HW structure

   710  *  @addr: EMI address to program

   711  *  @data: value to be written to the EMI address

   712  *

   713  *  Assumes the SW/FW/HW Semaphore is already acquired.

   714  **/

   715 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)

   716 {

   717 	return __e1000_access_emi_reg_locked(hw, addr, &data, false);

   718 }

   719 

   720 /**

   721  *  e1000_set_eee_pchlan - Enable/disable EEE support

   722  *  @hw: pointer to the HW structure

   723  *

   724  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of

   725  *  the link and the EEE capabilities of the link partner.  The LPI Control

   726  *  register bits will remain set only if/when link is up.

   727  **/

   728 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)

   729 {

   730 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   731 	s32 ret_val;

   732 	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;

   733 

   734 	switch (hw->phy.type) {

   735 	case e1000_phy_82579:

   736 		lpa = I82579_EEE_LP_ABILITY;

   737 		pcs_status = I82579_EEE_PCS_STATUS;

   738 		adv_addr = I82579_EEE_ADVERTISEMENT;

   739 		break;

   740 	case e1000_phy_i217:

   741 		lpa = I217_EEE_LP_ABILITY;

   742 		pcs_status = I217_EEE_PCS_STATUS;

   743 		adv_addr = I217_EEE_ADVERTISEMENT;

   744 		break;

   745 	default:

   746 		return 0;

   747 	}

   748 

   749 	ret_val = hw->phy.ops.acquire(hw);

   750 	if (ret_val)

   751 		return ret_val;

   752 

   753 	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);

   754 	if (ret_val)

   755 		goto release;

   756 

   757 	/* Clear bits that enable EEE in various speeds */

   758 	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;

   759 

   760 	/* Enable EEE if not disabled by user */

   761 	if (!dev_spec->eee_disable) {

   762 		/* Save off link partner's EEE ability */

   763 		ret_val = e1000_read_emi_reg_locked(hw, lpa,

   764 						    &dev_spec->eee_lp_ability);

   765 		if (ret_val)

   766 			goto release;

   767 

   768 		/* Read EEE advertisement */

   769 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);

   770 		if (ret_val)

   771 			goto release;

   772 

   773 		/* Enable EEE only for speeds in which the link partner is

   774 		 * EEE capable and for which we advertise EEE.

   775 		 */

   776 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)

   777 			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;

   778 

   779 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {

   780 			e1e_rphy_locked(hw, MII_LPA, &data);

   781 			if (data & LPA_100FULL)

   782 				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;

   783 			else

   784 				/* EEE is not supported in 100Half, so ignore

   785 				 * partner's EEE in 100 ability if full-duplex

   786 				 * is not advertised.

   787 				 */

   788 				dev_spec->eee_lp_ability &=

   789 				    ~I82579_EEE_100_SUPPORTED;

   790 		}

   791 	}

   792 

   793 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */

   794 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);

   795 	if (ret_val)

   796 		goto release;

   797 

   798 	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);

   799 release:

   800 	hw->phy.ops.release(hw);

   801 

   802 	return ret_val;

   803 }

   804 

   805 /**

   806  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP

   807  *  @hw:   pointer to the HW structure

   808  *  @link: link up bool flag

   809  *

   810  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications

   811  *  preventing further DMA write requests.  Workaround the issue by disabling

   812  *  the de-assertion of the clock request when in 1Gpbs mode.

   813  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link

   814  *  speeds in order to avoid Tx hangs.

   815  **/

   816 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)

   817 {

   818 	u32 fextnvm6 = er32(FEXTNVM6);

   819 	u32 status = er32(STATUS);

   820 	s32 ret_val = 0;

   821 	u16 reg;

   822 

   823 	if (link && (status & E1000_STATUS_SPEED_1000)) {

   824 		ret_val = hw->phy.ops.acquire(hw);

   825 		if (ret_val)

   826 			return ret_val;

   827 

   828 		ret_val =

   829 		    e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,

   830 						&reg);

   831 		if (ret_val)

   832 			goto release;

   833 

   834 		ret_val =

   835 		    e1000e_write_kmrn_reg_locked(hw,

   836 						 E1000_KMRNCTRLSTA_K1_CONFIG,

   837 						 reg &

   838 						 ~E1000_KMRNCTRLSTA_K1_ENABLE);

   839 		if (ret_val)

   840 			goto release;

   841 

   842 		usleep_range(10, 20);

   843 

   844 		ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);

   845 

   846 		ret_val =

   847 		    e1000e_write_kmrn_reg_locked(hw,

   848 						 E1000_KMRNCTRLSTA_K1_CONFIG,

   849 						 reg);

   850 release:

   851 		hw->phy.ops.release(hw);

   852 	} else {

   853 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */

   854 		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;

   855 

   856 		if (!link || ((status & E1000_STATUS_SPEED_100) &&

   857 			      (status & E1000_STATUS_FD)))

   858 			goto update_fextnvm6;

   859 

   860 		ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);

   861 		if (ret_val)

   862 			return ret_val;

   863 

   864 		/* Clear link status transmit timeout */

   865 		reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;

   866 

   867 		if (status & E1000_STATUS_SPEED_100) {

   868 			/* Set inband Tx timeout to 5x10us for 100Half */

   869 			reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;

   870 

   871 			/* Do not extend the K1 entry latency for 100Half */

   872 			fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;

   873 		} else {

   874 			/* Set inband Tx timeout to 50x10us for 10Full/Half */

   875 			reg |= 50 <<

   876 			    I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;

   877 

   878 			/* Extend the K1 entry latency for 10 Mbps */

   879 			fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;

   880 		}

   881 

   882 		ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);

   883 		if (ret_val)

   884 			return ret_val;

   885 

   886 update_fextnvm6:

   887 		ew32(FEXTNVM6, fextnvm6);

   888 	}

   889 

   890 	return ret_val;

   891 }

   892 

   893 /**

   894  *  e1000_platform_pm_pch_lpt - Set platform power management values

   895  *  @hw: pointer to the HW structure

   896  *  @link: bool indicating link status

   897  *

   898  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"

   899  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed

   900  *  when link is up (which must not exceed the maximum latency supported

   901  *  by the platform), otherwise specify there is no LTR requirement.

   902  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop

   903  *  latencies in the LTR Extended Capability Structure in the PCIe Extended

   904  *  Capability register set, on this device LTR is set by writing the

   905  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and

   906  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)

   907  *  message to the PMC.

   908  **/

   909 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)

   910 {

   911 	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |

   912 	    link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;

   913 	u16 lat_enc = 0;	/* latency encoded */

   914 

   915 	if (link) {

   916 		u16 speed, duplex, scale = 0;

   917 		u16 max_snoop, max_nosnoop;

   918 		u16 max_ltr_enc;	/* max LTR latency encoded */

   919 		s64 lat_ns;	/* latency (ns) */

   920 		s64 value;

   921 		u32 rxa;

   922 

   923 		if (!hw->adapter->max_frame_size) {

   924 			e_dbg("max_frame_size not set.\n");

   925 			return -E1000_ERR_CONFIG;

   926 		}

   927 

   928 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);

   929 		if (!speed) {

   930 			e_dbg("Speed not set.\n");

   931 			return -E1000_ERR_CONFIG;

   932 		}

   933 

   934 		/* Rx Packet Buffer Allocation size (KB) */

   935 		rxa = er32(PBA) & E1000_PBA_RXA_MASK;

   936 

   937 		/* Determine the maximum latency tolerated by the device.

   938 		 *

   939 		 * Per the PCIe spec, the tolerated latencies are encoded as

   940 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by

   941 		 * a 10-bit value (0-1023) to provide a range from 1 ns to

   942 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,

   943 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.

   944 		 */

   945 		lat_ns = ((s64)rxa * 1024 -

   946 			  (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;

   947 		if (lat_ns < 0)

   948 			lat_ns = 0;

   949 		else

   950 			do_div(lat_ns, speed);

   951 

   952 		value = lat_ns;

   953 		while (value > PCI_LTR_VALUE_MASK) {

   954 			scale++;

   955 			value = DIV_ROUND_UP(value, (1 << 5));

   956 		}

   957 		if (scale > E1000_LTRV_SCALE_MAX) {

   958 			e_dbg("Invalid LTR latency scale %d\n", scale);

   959 			return -E1000_ERR_CONFIG;

   960 		}

   961 		lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);

   962 

   963 		/* Determine the maximum latency tolerated by the platform */

   964 		pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,

   965 				     &max_snoop);

   966 		pci_read_config_word(hw->adapter->pdev,

   967 				     E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);

   968 		max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);

   969 

   970 		if (lat_enc > max_ltr_enc)

   971 			lat_enc = max_ltr_enc;

   972 	}

   973 

   974 	/* Set Snoop and No-Snoop latencies the same */

   975 	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);

   976 	ew32(LTRV, reg);

   977 

   978 	return 0;

   979 }

   980 

   981 /**

   982  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)

   983  *  @hw: pointer to the HW structure

   984  *

   985  *  Checks to see of the link status of the hardware has changed.  If a

   986  *  change in link status has been detected, then we read the PHY registers

   987  *  to get the current speed/duplex if link exists.

   988  **/

   989 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)

   990 {

   991 	struct e1000_mac_info *mac = &hw->mac;

   992 	s32 ret_val;

   993 	bool link;

   994 	u16 phy_reg;

   995 

   996 	/* We only want to go out to the PHY registers to see if Auto-Neg

   997 	 * has completed and/or if our link status has changed.  The

   998 	 * get_link_status flag is set upon receiving a Link Status

   999 	 * Change or Rx Sequence Error interrupt.

  1000 	 */

  1001 	if (!mac->get_link_status)

  1002 		return 0;

  1003 

  1004 	/* First we want to see if the MII Status Register reports

  1005 	 * link.  If so, then we want to get the current speed/duplex

  1006 	 * of the PHY.

  1007 	 */

  1008 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

  1009 	if (ret_val)

  1010 		return ret_val;

  1011 

  1012 	if (hw->mac.type == e1000_pchlan) {

  1013 		ret_val = e1000_k1_gig_workaround_hv(hw, link);

  1014 		if (ret_val)

  1015 			return ret_val;

  1016 	}

  1017 

  1018 	/* When connected at 10Mbps half-duplex, 82579 parts are excessively

  1019 	 * aggressive resulting in many collisions. To avoid this, increase

  1020 	 * the IPG and reduce Rx latency in the PHY.

  1021 	 */

  1022 	if ((hw->mac.type == e1000_pch2lan) && link) {

  1023 		u32 reg;

  1024 		reg = er32(STATUS);

  1025 		if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {

  1026 			reg = er32(TIPG);

  1027 			reg &= ~E1000_TIPG_IPGT_MASK;

  1028 			reg |= 0xFF;

  1029 			ew32(TIPG, reg);

  1030 

  1031 			/* Reduce Rx latency in analog PHY */

  1032 			ret_val = hw->phy.ops.acquire(hw);

  1033 			if (ret_val)

  1034 				return ret_val;

  1035 

  1036 			ret_val =

  1037 			    e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);

  1038 

  1039 			hw->phy.ops.release(hw);

  1040 

  1041 			if (ret_val)

  1042 				return ret_val;

  1043 		}

  1044 	}

  1045 

  1046 	/* Work-around I218 hang issue */

  1047 	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||

  1048 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||

  1049 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||

  1050 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {

  1051 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);

  1052 		if (ret_val)

  1053 			return ret_val;

  1054 	}

  1055 

  1056 	if (hw->mac.type == e1000_pch_lpt) {

  1057 		/* Set platform power management values for

  1058 		 * Latency Tolerance Reporting (LTR)

  1059 		 */

  1060 		ret_val = e1000_platform_pm_pch_lpt(hw, link);

  1061 		if (ret_val)

  1062 			return ret_val;

  1063 	}

  1064 

  1065 	/* Clear link partner's EEE ability */

  1066 	hw->dev_spec.ich8lan.eee_lp_ability = 0;

  1067 

  1068 	if (!link)

  1069 		return 0;	/* No link detected */

  1070 

  1071 	mac->get_link_status = false;

  1072 

  1073 	switch (hw->mac.type) {

  1074 	case e1000_pch2lan:

  1075 		ret_val = e1000_k1_workaround_lv(hw);

  1076 		if (ret_val)

  1077 			return ret_val;

  1078 		/* fall-thru */

  1079 	case e1000_pchlan:

  1080 		if (hw->phy.type == e1000_phy_82578) {

  1081 			ret_val = e1000_link_stall_workaround_hv(hw);

  1082 			if (ret_val)

  1083 				return ret_val;

  1084 		}

  1085 

  1086 		/* Workaround for PCHx parts in half-duplex:

  1087 		 * Set the number of preambles removed from the packet

  1088 		 * when it is passed from the PHY to the MAC to prevent

  1089 		 * the MAC from misinterpreting the packet type.

  1090 		 */

  1091 		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);

  1092 		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;

  1093 

  1094 		if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)

  1095 			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);

  1096 

  1097 		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);

  1098 		break;

  1099 	default:

  1100 		break;

  1101 	}

  1102 

  1103 	/* Check if there was DownShift, must be checked

  1104 	 * immediately after link-up

  1105 	 */

  1106 	e1000e_check_downshift(hw);

  1107 

  1108 	/* Enable/Disable EEE after link up */

  1109 	ret_val = e1000_set_eee_pchlan(hw);

  1110 	if (ret_val)

  1111 		return ret_val;

  1112 

  1113 	/* If we are forcing speed/duplex, then we simply return since

  1114 	 * we have already determined whether we have link or not.

  1115 	 */

  1116 	if (!mac->autoneg)

  1117 		return -E1000_ERR_CONFIG;

  1118 

  1119 	/* Auto-Neg is enabled.  Auto Speed Detection takes care

  1120 	 * of MAC speed/duplex configuration.  So we only need to

  1121 	 * configure Collision Distance in the MAC.

  1122 	 */

  1123 	mac->ops.config_collision_dist(hw);

  1124 

  1125 	/* Configure Flow Control now that Auto-Neg has completed.

  1126 	 * First, we need to restore the desired flow control

  1127 	 * settings because we may have had to re-autoneg with a

  1128 	 * different link partner.

  1129 	 */

  1130 	ret_val = e1000e_config_fc_after_link_up(hw);

  1131 	if (ret_val)

  1132 		e_dbg("Error configuring flow control\n");

  1133 

  1134 	return ret_val;

  1135 }

  1136