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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2013 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #ifndef _E1000_HW_H_ |
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30 #define _E1000_HW_H_ |
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31 |
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32 #include "regs.h" |
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33 #include "defines.h" |
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34 |
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35 struct e1000_hw; |
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36 |
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37 #define E1000_DEV_ID_82571EB_COPPER 0x105E |
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38 #define E1000_DEV_ID_82571EB_FIBER 0x105F |
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39 #define E1000_DEV_ID_82571EB_SERDES 0x1060 |
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40 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 |
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41 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 |
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42 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 |
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43 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC |
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44 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 |
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45 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA |
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46 #define E1000_DEV_ID_82572EI_COPPER 0x107D |
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47 #define E1000_DEV_ID_82572EI_FIBER 0x107E |
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48 #define E1000_DEV_ID_82572EI_SERDES 0x107F |
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49 #define E1000_DEV_ID_82572EI 0x10B9 |
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50 #define E1000_DEV_ID_82573E 0x108B |
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51 #define E1000_DEV_ID_82573E_IAMT 0x108C |
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52 #define E1000_DEV_ID_82573L 0x109A |
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53 #define E1000_DEV_ID_82574L 0x10D3 |
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54 #define E1000_DEV_ID_82574LA 0x10F6 |
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55 #define E1000_DEV_ID_82583V 0x150C |
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56 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 |
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57 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 |
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58 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA |
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59 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB |
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60 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 |
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61 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 |
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62 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A |
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63 #define E1000_DEV_ID_ICH8_IGP_C 0x104B |
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64 #define E1000_DEV_ID_ICH8_IFE 0x104C |
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65 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 |
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66 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 |
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67 #define E1000_DEV_ID_ICH8_IGP_M 0x104D |
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68 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD |
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69 #define E1000_DEV_ID_ICH9_BM 0x10E5 |
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70 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 |
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71 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF |
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72 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB |
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73 #define E1000_DEV_ID_ICH9_IGP_C 0x294C |
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74 #define E1000_DEV_ID_ICH9_IFE 0x10C0 |
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75 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 |
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76 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 |
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77 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC |
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78 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD |
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79 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE |
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80 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE |
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81 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF |
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82 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 |
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83 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA |
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84 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB |
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85 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF |
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86 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 |
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87 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 |
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88 #define E1000_DEV_ID_PCH2_LV_V 0x1503 |
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89 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A |
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90 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B |
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91 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A |
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92 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 |
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93 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 |
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94 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 |
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95 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ |
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96 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ |
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97 |
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98 #define E1000_REVISION_4 4 |
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99 |
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100 #define E1000_FUNC_1 1 |
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101 |
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102 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 |
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103 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 |
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104 |
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105 enum e1000_mac_type { |
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106 e1000_82571, |
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107 e1000_82572, |
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108 e1000_82573, |
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109 e1000_82574, |
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110 e1000_82583, |
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111 e1000_80003es2lan, |
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112 e1000_ich8lan, |
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113 e1000_ich9lan, |
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114 e1000_ich10lan, |
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115 e1000_pchlan, |
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116 e1000_pch2lan, |
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117 e1000_pch_lpt, |
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118 }; |
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119 |
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120 enum e1000_media_type { |
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121 e1000_media_type_unknown = 0, |
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122 e1000_media_type_copper = 1, |
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123 e1000_media_type_fiber = 2, |
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124 e1000_media_type_internal_serdes = 3, |
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125 e1000_num_media_types |
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126 }; |
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127 |
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128 enum e1000_nvm_type { |
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129 e1000_nvm_unknown = 0, |
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130 e1000_nvm_none, |
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131 e1000_nvm_eeprom_spi, |
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132 e1000_nvm_flash_hw, |
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133 e1000_nvm_flash_sw |
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134 }; |
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135 |
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136 enum e1000_nvm_override { |
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137 e1000_nvm_override_none = 0, |
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138 e1000_nvm_override_spi_small, |
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139 e1000_nvm_override_spi_large |
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140 }; |
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141 |
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142 enum e1000_phy_type { |
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143 e1000_phy_unknown = 0, |
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144 e1000_phy_none, |
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145 e1000_phy_m88, |
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146 e1000_phy_igp, |
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147 e1000_phy_igp_2, |
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148 e1000_phy_gg82563, |
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149 e1000_phy_igp_3, |
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150 e1000_phy_ife, |
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151 e1000_phy_bm, |
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152 e1000_phy_82578, |
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153 e1000_phy_82577, |
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154 e1000_phy_82579, |
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155 e1000_phy_i217, |
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156 }; |
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157 |
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158 enum e1000_bus_width { |
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159 e1000_bus_width_unknown = 0, |
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160 e1000_bus_width_pcie_x1, |
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161 e1000_bus_width_pcie_x2, |
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162 e1000_bus_width_pcie_x4 = 4, |
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163 e1000_bus_width_32, |
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164 e1000_bus_width_64, |
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165 e1000_bus_width_reserved |
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166 }; |
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167 |
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168 enum e1000_1000t_rx_status { |
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169 e1000_1000t_rx_status_not_ok = 0, |
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170 e1000_1000t_rx_status_ok, |
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171 e1000_1000t_rx_status_undefined = 0xFF |
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172 }; |
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173 |
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174 enum e1000_rev_polarity { |
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175 e1000_rev_polarity_normal = 0, |
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176 e1000_rev_polarity_reversed, |
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177 e1000_rev_polarity_undefined = 0xFF |
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178 }; |
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179 |
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180 enum e1000_fc_mode { |
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181 e1000_fc_none = 0, |
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182 e1000_fc_rx_pause, |
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183 e1000_fc_tx_pause, |
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184 e1000_fc_full, |
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185 e1000_fc_default = 0xFF |
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186 }; |
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187 |
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188 enum e1000_ms_type { |
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189 e1000_ms_hw_default = 0, |
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190 e1000_ms_force_master, |
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191 e1000_ms_force_slave, |
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192 e1000_ms_auto |
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193 }; |
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194 |
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195 enum e1000_smart_speed { |
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196 e1000_smart_speed_default = 0, |
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197 e1000_smart_speed_on, |
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198 e1000_smart_speed_off |
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199 }; |
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200 |
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201 enum e1000_serdes_link_state { |
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202 e1000_serdes_link_down = 0, |
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203 e1000_serdes_link_autoneg_progress, |
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204 e1000_serdes_link_autoneg_complete, |
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205 e1000_serdes_link_forced_up |
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206 }; |
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207 |
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208 /* Receive Descriptor - Extended */ |
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209 union e1000_rx_desc_extended { |
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210 struct { |
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211 __le64 buffer_addr; |
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212 __le64 reserved; |
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213 } read; |
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214 struct { |
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215 struct { |
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216 __le32 mrq; /* Multiple Rx Queues */ |
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217 union { |
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218 __le32 rss; /* RSS Hash */ |
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219 struct { |
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220 __le16 ip_id; /* IP id */ |
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221 __le16 csum; /* Packet Checksum */ |
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222 } csum_ip; |
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223 } hi_dword; |
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224 } lower; |
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225 struct { |
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226 __le32 status_error; /* ext status/error */ |
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227 __le16 length; |
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228 __le16 vlan; /* VLAN tag */ |
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229 } upper; |
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230 } wb; /* writeback */ |
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231 }; |
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232 |
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233 #define MAX_PS_BUFFERS 4 |
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234 |
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235 /* Number of packet split data buffers (not including the header buffer) */ |
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236 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) |
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237 |
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238 /* Receive Descriptor - Packet Split */ |
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239 union e1000_rx_desc_packet_split { |
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240 struct { |
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241 /* one buffer for protocol header(s), three data buffers */ |
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242 __le64 buffer_addr[MAX_PS_BUFFERS]; |
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243 } read; |
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244 struct { |
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245 struct { |
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246 __le32 mrq; /* Multiple Rx Queues */ |
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247 union { |
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248 __le32 rss; /* RSS Hash */ |
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249 struct { |
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250 __le16 ip_id; /* IP id */ |
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251 __le16 csum; /* Packet Checksum */ |
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252 } csum_ip; |
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253 } hi_dword; |
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254 } lower; |
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255 struct { |
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256 __le32 status_error; /* ext status/error */ |
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257 __le16 length0; /* length of buffer 0 */ |
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258 __le16 vlan; /* VLAN tag */ |
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259 } middle; |
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260 struct { |
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261 __le16 header_status; |
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262 /* length of buffers 1-3 */ |
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263 __le16 length[PS_PAGE_BUFFERS]; |
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264 } upper; |
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265 __le64 reserved; |
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266 } wb; /* writeback */ |
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267 }; |
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268 |
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269 /* Transmit Descriptor */ |
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270 struct e1000_tx_desc { |
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271 __le64 buffer_addr; /* Address of the descriptor's data buffer */ |
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272 union { |
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273 __le32 data; |
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274 struct { |
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275 __le16 length; /* Data buffer length */ |
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276 u8 cso; /* Checksum offset */ |
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277 u8 cmd; /* Descriptor control */ |
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278 } flags; |
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279 } lower; |
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280 union { |
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281 __le32 data; |
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282 struct { |
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283 u8 status; /* Descriptor status */ |
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284 u8 css; /* Checksum start */ |
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285 __le16 special; |
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286 } fields; |
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287 } upper; |
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288 }; |
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289 |
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290 /* Offload Context Descriptor */ |
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291 struct e1000_context_desc { |
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292 union { |
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293 __le32 ip_config; |
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294 struct { |
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295 u8 ipcss; /* IP checksum start */ |
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296 u8 ipcso; /* IP checksum offset */ |
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297 __le16 ipcse; /* IP checksum end */ |
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298 } ip_fields; |
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299 } lower_setup; |
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300 union { |
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301 __le32 tcp_config; |
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302 struct { |
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303 u8 tucss; /* TCP checksum start */ |
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304 u8 tucso; /* TCP checksum offset */ |
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305 __le16 tucse; /* TCP checksum end */ |
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306 } tcp_fields; |
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307 } upper_setup; |
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308 __le32 cmd_and_length; |
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309 union { |
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310 __le32 data; |
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311 struct { |
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312 u8 status; /* Descriptor status */ |
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313 u8 hdr_len; /* Header length */ |
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314 __le16 mss; /* Maximum segment size */ |
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315 } fields; |
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316 } tcp_seg_setup; |
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317 }; |
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318 |
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319 /* Offload data descriptor */ |
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320 struct e1000_data_desc { |
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321 __le64 buffer_addr; /* Address of the descriptor's buffer address */ |
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322 union { |
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323 __le32 data; |
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324 struct { |
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325 __le16 length; /* Data buffer length */ |
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326 u8 typ_len_ext; |
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327 u8 cmd; |
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328 } flags; |
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329 } lower; |
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330 union { |
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331 __le32 data; |
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332 struct { |
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333 u8 status; /* Descriptor status */ |
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334 u8 popts; /* Packet Options */ |
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335 __le16 special; |
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336 } fields; |
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337 } upper; |
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338 }; |
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339 |
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340 /* Statistics counters collected by the MAC */ |
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341 struct e1000_hw_stats { |
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342 u64 crcerrs; |
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343 u64 algnerrc; |
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344 u64 symerrs; |
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345 u64 rxerrc; |
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346 u64 mpc; |
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347 u64 scc; |
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348 u64 ecol; |
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349 u64 mcc; |
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350 u64 latecol; |
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351 u64 colc; |
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352 u64 dc; |
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353 u64 tncrs; |
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354 u64 sec; |
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355 u64 cexterr; |
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356 u64 rlec; |
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357 u64 xonrxc; |
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358 u64 xontxc; |
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359 u64 xoffrxc; |
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360 u64 xofftxc; |
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361 u64 fcruc; |
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362 u64 prc64; |
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363 u64 prc127; |
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364 u64 prc255; |
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365 u64 prc511; |
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366 u64 prc1023; |
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367 u64 prc1522; |
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368 u64 gprc; |
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369 u64 bprc; |
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370 u64 mprc; |
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371 u64 gptc; |
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372 u64 gorc; |
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373 u64 gotc; |
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374 u64 rnbc; |
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375 u64 ruc; |
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376 u64 rfc; |
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377 u64 roc; |
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378 u64 rjc; |
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379 u64 mgprc; |
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380 u64 mgpdc; |
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381 u64 mgptc; |
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382 u64 tor; |
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383 u64 tot; |
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384 u64 tpr; |
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385 u64 tpt; |
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386 u64 ptc64; |
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387 u64 ptc127; |
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388 u64 ptc255; |
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389 u64 ptc511; |
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390 u64 ptc1023; |
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391 u64 ptc1522; |
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392 u64 mptc; |
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393 u64 bptc; |
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394 u64 tsctc; |
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395 u64 tsctfc; |
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396 u64 iac; |
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397 u64 icrxptc; |
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398 u64 icrxatc; |
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399 u64 ictxptc; |
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400 u64 ictxatc; |
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401 u64 ictxqec; |
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402 u64 ictxqmtc; |
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403 u64 icrxdmtc; |
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404 u64 icrxoc; |
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405 }; |
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406 |
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407 struct e1000_phy_stats { |
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408 u32 idle_errors; |
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409 u32 receive_errors; |
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410 }; |
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411 |
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412 struct e1000_host_mng_dhcp_cookie { |
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413 u32 signature; |
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414 u8 status; |
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415 u8 reserved0; |
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416 u16 vlan_id; |
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417 u32 reserved1; |
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418 u16 reserved2; |
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419 u8 reserved3; |
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420 u8 checksum; |
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421 }; |
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422 |
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423 /* Host Interface "Rev 1" */ |
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424 struct e1000_host_command_header { |
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425 u8 command_id; |
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426 u8 command_length; |
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427 u8 command_options; |
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428 u8 checksum; |
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429 }; |
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430 |
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431 #define E1000_HI_MAX_DATA_LENGTH 252 |
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432 struct e1000_host_command_info { |
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433 struct e1000_host_command_header command_header; |
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434 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; |
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435 }; |
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436 |
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437 /* Host Interface "Rev 2" */ |
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438 struct e1000_host_mng_command_header { |
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439 u8 command_id; |
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440 u8 checksum; |
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441 u16 reserved1; |
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442 u16 reserved2; |
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443 u16 command_length; |
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444 }; |
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445 |
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446 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 |
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447 struct e1000_host_mng_command_info { |
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448 struct e1000_host_mng_command_header command_header; |
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449 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; |
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450 }; |
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451 |
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452 #include "mac.h" |
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453 #include "phy.h" |
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454 #include "nvm.h" |
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455 #include "manage.h" |
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456 |
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457 /* Function pointers for the MAC. */ |
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458 struct e1000_mac_operations { |
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459 s32 (*id_led_init)(struct e1000_hw *); |
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460 s32 (*blink_led)(struct e1000_hw *); |
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461 bool (*check_mng_mode)(struct e1000_hw *); |
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462 s32 (*check_for_link)(struct e1000_hw *); |
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463 s32 (*cleanup_led)(struct e1000_hw *); |
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464 void (*clear_hw_cntrs)(struct e1000_hw *); |
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465 void (*clear_vfta)(struct e1000_hw *); |
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466 s32 (*get_bus_info)(struct e1000_hw *); |
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467 void (*set_lan_id)(struct e1000_hw *); |
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468 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); |
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469 s32 (*led_on)(struct e1000_hw *); |
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470 s32 (*led_off)(struct e1000_hw *); |
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471 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); |
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472 s32 (*reset_hw)(struct e1000_hw *); |
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473 s32 (*init_hw)(struct e1000_hw *); |
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474 s32 (*setup_link)(struct e1000_hw *); |
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475 s32 (*setup_physical_interface)(struct e1000_hw *); |
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476 s32 (*setup_led)(struct e1000_hw *); |
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477 void (*write_vfta)(struct e1000_hw *, u32, u32); |
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478 void (*config_collision_dist)(struct e1000_hw *); |
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479 void (*rar_set)(struct e1000_hw *, u8 *, u32); |
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480 s32 (*read_mac_addr)(struct e1000_hw *); |
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481 }; |
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482 |
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483 /* When to use various PHY register access functions: |
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484 * |
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485 * Func Caller |
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486 * Function Does Does When to use |
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487 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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488 * X_reg L,P,A n/a for simple PHY reg accesses |
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489 * X_reg_locked P,A L for multiple accesses of different regs |
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490 * on different pages |
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491 * X_reg_page A L,P for multiple accesses of different regs |
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492 * on the same page |
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493 * |
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494 * Where X=[read|write], L=locking, P=sets page, A=register access |
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495 * |
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496 */ |
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497 struct e1000_phy_operations { |
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498 s32 (*acquire)(struct e1000_hw *); |
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499 s32 (*cfg_on_link_up)(struct e1000_hw *); |
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500 s32 (*check_polarity)(struct e1000_hw *); |
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501 s32 (*check_reset_block)(struct e1000_hw *); |
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502 s32 (*commit)(struct e1000_hw *); |
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503 s32 (*force_speed_duplex)(struct e1000_hw *); |
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504 s32 (*get_cfg_done)(struct e1000_hw *hw); |
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505 s32 (*get_cable_length)(struct e1000_hw *); |
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506 s32 (*get_info)(struct e1000_hw *); |
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507 s32 (*set_page)(struct e1000_hw *, u16); |
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508 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); |
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509 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); |
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510 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); |
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511 void (*release)(struct e1000_hw *); |
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512 s32 (*reset)(struct e1000_hw *); |
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513 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); |
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514 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); |
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515 s32 (*write_reg)(struct e1000_hw *, u32, u16); |
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516 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); |
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517 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); |
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518 void (*power_up)(struct e1000_hw *); |
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519 void (*power_down)(struct e1000_hw *); |
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520 }; |
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521 |
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522 /* Function pointers for the NVM. */ |
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523 struct e1000_nvm_operations { |
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524 s32 (*acquire)(struct e1000_hw *); |
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525 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); |
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526 void (*release)(struct e1000_hw *); |
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527 void (*reload)(struct e1000_hw *); |
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528 s32 (*update)(struct e1000_hw *); |
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529 s32 (*valid_led_default)(struct e1000_hw *, u16 *); |
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530 s32 (*validate)(struct e1000_hw *); |
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531 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); |
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532 }; |
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533 |
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534 struct e1000_mac_info { |
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535 struct e1000_mac_operations ops; |
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536 u8 addr[ETH_ALEN]; |
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537 u8 perm_addr[ETH_ALEN]; |
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538 |
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539 enum e1000_mac_type type; |
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540 |
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541 u32 collision_delta; |
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542 u32 ledctl_default; |
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543 u32 ledctl_mode1; |
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544 u32 ledctl_mode2; |
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545 u32 mc_filter_type; |
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546 u32 tx_packet_delta; |
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547 u32 txcw; |
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548 |
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549 u16 current_ifs_val; |
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550 u16 ifs_max_val; |
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551 u16 ifs_min_val; |
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552 u16 ifs_ratio; |
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553 u16 ifs_step_size; |
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554 u16 mta_reg_count; |
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555 |
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556 /* Maximum size of the MTA register table in all supported adapters */ |
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557 #define MAX_MTA_REG 128 |
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558 u32 mta_shadow[MAX_MTA_REG]; |
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559 u16 rar_entry_count; |
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560 |
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561 u8 forced_speed_duplex; |
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562 |
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563 bool adaptive_ifs; |
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564 bool has_fwsm; |
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565 bool arc_subsystem_valid; |
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566 bool autoneg; |
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567 bool autoneg_failed; |
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568 bool get_link_status; |
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569 bool in_ifs_mode; |
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570 bool serdes_has_link; |
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571 bool tx_pkt_filtering; |
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572 enum e1000_serdes_link_state serdes_link_state; |
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573 }; |
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574 |
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575 struct e1000_phy_info { |
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576 struct e1000_phy_operations ops; |
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577 |
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578 enum e1000_phy_type type; |
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579 |
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580 enum e1000_1000t_rx_status local_rx; |
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581 enum e1000_1000t_rx_status remote_rx; |
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582 enum e1000_ms_type ms_type; |
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583 enum e1000_ms_type original_ms_type; |
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584 enum e1000_rev_polarity cable_polarity; |
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585 enum e1000_smart_speed smart_speed; |
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586 |
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587 u32 addr; |
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588 u32 id; |
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589 u32 reset_delay_us; /* in usec */ |
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590 u32 revision; |
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591 |
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592 enum e1000_media_type media_type; |
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593 |
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594 u16 autoneg_advertised; |
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595 u16 autoneg_mask; |
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596 u16 cable_length; |
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597 u16 max_cable_length; |
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598 u16 min_cable_length; |
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599 |
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600 u8 mdix; |
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601 |
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602 bool disable_polarity_correction; |
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603 bool is_mdix; |
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604 bool polarity_correction; |
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605 bool speed_downgraded; |
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606 bool autoneg_wait_to_complete; |
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607 }; |
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608 |
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609 struct e1000_nvm_info { |
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610 struct e1000_nvm_operations ops; |
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611 |
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612 enum e1000_nvm_type type; |
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613 enum e1000_nvm_override override; |
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614 |
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615 u32 flash_bank_size; |
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616 u32 flash_base_addr; |
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617 |
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618 u16 word_size; |
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619 u16 delay_usec; |
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620 u16 address_bits; |
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621 u16 opcode_bits; |
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622 u16 page_size; |
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623 }; |
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624 |
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625 struct e1000_bus_info { |
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626 enum e1000_bus_width width; |
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627 |
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628 u16 func; |
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629 }; |
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630 |
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631 struct e1000_fc_info { |
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632 u32 high_water; /* Flow control high-water mark */ |
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633 u32 low_water; /* Flow control low-water mark */ |
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634 u16 pause_time; /* Flow control pause timer */ |
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635 u16 refresh_time; /* Flow control refresh timer */ |
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636 bool send_xon; /* Flow control send XON */ |
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637 bool strict_ieee; /* Strict IEEE mode */ |
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638 enum e1000_fc_mode current_mode; /* FC mode in effect */ |
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639 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ |
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640 }; |
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641 |
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642 struct e1000_dev_spec_82571 { |
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643 bool laa_is_present; |
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644 u32 smb_counter; |
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645 }; |
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646 |
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647 struct e1000_dev_spec_80003es2lan { |
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648 bool mdic_wa_enable; |
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649 }; |
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650 |
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651 struct e1000_shadow_ram { |
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652 u16 value; |
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653 bool modified; |
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654 }; |
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655 |
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656 #define E1000_ICH8_SHADOW_RAM_WORDS 2048 |
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657 |
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658 struct e1000_dev_spec_ich8lan { |
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659 bool kmrn_lock_loss_workaround_enabled; |
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660 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; |
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661 bool nvm_k1_enabled; |
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662 bool eee_disable; |
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663 u16 eee_lp_ability; |
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664 }; |
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665 |
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666 struct e1000_hw { |
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667 struct e1000_adapter *adapter; |
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668 |
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669 void __iomem *hw_addr; |
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670 void __iomem *flash_address; |
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671 |
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672 struct e1000_mac_info mac; |
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673 struct e1000_fc_info fc; |
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674 struct e1000_phy_info phy; |
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675 struct e1000_nvm_info nvm; |
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676 struct e1000_bus_info bus; |
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677 struct e1000_host_mng_dhcp_cookie mng_cookie; |
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678 |
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679 union { |
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680 struct e1000_dev_spec_82571 e82571; |
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681 struct e1000_dev_spec_80003es2lan e80003es2lan; |
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682 struct e1000_dev_spec_ich8lan ich8lan; |
|
683 } dev_spec; |
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684 }; |
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685 |
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686 #include "82571.h" |
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687 #include "80003es2lan.h" |
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688 #include "ich8lan.h" |
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689 |
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690 #endif |