1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2012 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /*

    30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)

    31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    32  */

    33 

    34 #include "e1000.h"

    35 

    36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00

    37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02

    38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10

    39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F

    40 

    41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008

    42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800

    43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010

    44 

    45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

    46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000

    47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000

    48 

    49 #define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C

    50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004

    51 

    52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

    53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000

    54 

    55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8

    56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9

    57 

    58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */

    59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */

    60 #define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060

    61 #define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */

    62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */

    63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */

    64 

    65 /* PHY Specific Control Register 2 (Page 0, Register 26) */

    66 #define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000

    67 						/* 1=Reverse Auto-Negotiation */

    68 

    69 /* MAC Specific Control Register (Page 2, Register 21) */

    70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

    71 #define GG82563_MSCR_TX_CLK_MASK		 0x0007

    72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004

    73 #define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005

    74 #define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007

    75 

    76 #define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */

    77 

    78 /* DSP Distance Register (Page 5, Register 26) */

    79 #define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M

    80 							   1 = 50-80M

    81 							   2 = 80-110M

    82 							   3 = 110-140M

    83 							   4 = >140M */

    84 

    85 /* Kumeran Mode Control Register (Page 193, Register 16) */

    86 #define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800

    87 

    88 /* Max number of times Kumeran read/write should be validated */

    89 #define GG82563_MAX_KMRN_RETRY  0x5

    90 

    91 /* Power Management Control Register (Page 193, Register 20) */

    92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001

    93 					   /* 1=Enable SERDES Electrical Idle */

    94 

    95 /* In-Band Control Register (Page 194, Register 18) */

    96 #define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */

    97 

    98 /*

    99  * A table for the GG82563 cable length where the range is defined

   100  * with a lower bound at "index" and the upper bound at

   101  * "index + 5".

   102  */

   103 static const u16 e1000_gg82563_cable_length_table[] = {

   104 	 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };

   105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \

   106 		ARRAY_SIZE(e1000_gg82563_cable_length_table)

   107 

   108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

   109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

   112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

   113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

   114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

   115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);

   116 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   117                                             u16 *data);

   118 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   119                                              u16 data);

   120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);

   121 

   122 /**

   123  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

   124  *  @hw: pointer to the HW structure

   125  **/

   126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

   127 {

   128 	struct e1000_phy_info *phy = &hw->phy;

   129 	s32 ret_val;

   130 

   131 	if (hw->phy.media_type != e1000_media_type_copper) {

   132 		phy->type	= e1000_phy_none;

   133 		return 0;

   134 	} else {

   135 		phy->ops.power_up = e1000_power_up_phy_copper;

   136 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

   137 	}

   138 

   139 	phy->addr		= 1;

   140 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

   141 	phy->reset_delay_us      = 100;

   142 	phy->type		= e1000_phy_gg82563;

   143 

   144 	/* This can only be done after all function pointers are setup. */

   145 	ret_val = e1000e_get_phy_id(hw);

   146 

   147 	/* Verify phy id */

   148 	if (phy->id != GG82563_E_PHY_ID)

   149 		return -E1000_ERR_PHY;

   150 

   151 	return ret_val;

   152 }

   153 

   154 /**

   155  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

   156  *  @hw: pointer to the HW structure

   157  **/

   158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

   159 {

   160 	struct e1000_nvm_info *nvm = &hw->nvm;

   161 	u32 eecd = er32(EECD);

   162 	u16 size;

   163 

   164 	nvm->opcode_bits	= 8;

   165 	nvm->delay_usec	 = 1;

   166 	switch (nvm->override) {

   167 	case e1000_nvm_override_spi_large:

   168 		nvm->page_size    = 32;

   169 		nvm->address_bits = 16;

   170 		break;

   171 	case e1000_nvm_override_spi_small:

   172 		nvm->page_size    = 8;

   173 		nvm->address_bits = 8;

   174 		break;

   175 	default:

   176 		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   177 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   178 		break;

   179 	}

   180 

   181 	nvm->type = e1000_nvm_eeprom_spi;

   182 

   183 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   184 			  E1000_EECD_SIZE_EX_SHIFT);

   185 

   186 	/*

   187 	 * Added to a constant, "size" becomes the left-shift value

   188 	 * for setting word_size.

   189 	 */

   190 	size += NVM_WORD_SIZE_BASE_SHIFT;

   191 

   192 	/* EEPROM access above 16k is unsupported */

   193 	if (size > 14)

   194 		size = 14;

   195 	nvm->word_size	= 1 << size;

   196 

   197 	return 0;

   198 }

   199 

   200 /**

   201  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   202  *  @hw: pointer to the HW structure

   203  **/

   204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)

   205 {

   206 	struct e1000_mac_info *mac = &hw->mac;

   207 

   208 	/* Set media type and media-dependent function pointers */

   209 	switch (hw->adapter->pdev->device) {

   210 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   211 		hw->phy.media_type = e1000_media_type_internal_serdes;

   212 		mac->ops.check_for_link = e1000e_check_for_serdes_link;

   213 		mac->ops.setup_physical_interface =

   214 		    e1000e_setup_fiber_serdes_link;

   215 		break;

   216 	default:

   217 		hw->phy.media_type = e1000_media_type_copper;

   218 		mac->ops.check_for_link = e1000e_check_for_copper_link;

   219 		mac->ops.setup_physical_interface =

   220 		    e1000_setup_copper_link_80003es2lan;

   221 		break;

   222 	}

   223 

   224 	/* Set mta register count */

   225 	mac->mta_reg_count = 128;

   226 	/* Set rar entry count */

   227 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   228 	/* FWSM register */

   229 	mac->has_fwsm = true;

   230 	/* ARC supported; valid only if manageability features are enabled. */

   231 	mac->arc_subsystem_valid =

   232 	        (er32(FWSM) & E1000_FWSM_MODE_MASK)

   233 	                ? true : false;

   234 	/* Adaptive IFS not supported */

   235 	mac->adaptive_ifs = false;

   236 

   237 	/* set lan id for port to determine which phy lock to use */

   238 	hw->mac.ops.set_lan_id(hw);

   239 

   240 	return 0;

   241 }

   242 

   243 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   244 {

   245 	struct e1000_hw *hw = &adapter->hw;

   246 	s32 rc;

   247 

   248 	rc = e1000_init_mac_params_80003es2lan(hw);

   249 	if (rc)

   250 		return rc;

   251 

   252 	rc = e1000_init_nvm_params_80003es2lan(hw);

   253 	if (rc)

   254 		return rc;

   255 

   256 	rc = e1000_init_phy_params_80003es2lan(hw);

   257 	if (rc)

   258 		return rc;

   259 

   260 	return 0;

   261 }

   262 

   263 /**

   264  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   265  *  @hw: pointer to the HW structure

   266  *

   267  *  A wrapper to acquire access rights to the correct PHY.

   268  **/

   269 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   270 {

   271 	u16 mask;

   272 

   273 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   274 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   275 }

   276 

   277 /**

   278  *  e1000_release_phy_80003es2lan - Release rights to access PHY

   279  *  @hw: pointer to the HW structure

   280  *

   281  *  A wrapper to release access rights to the correct PHY.

   282  **/

   283 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   284 {

   285 	u16 mask;

   286 

   287 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   288 	e1000_release_swfw_sync_80003es2lan(hw, mask);

   289 }

   290 

   291 /**

   292  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register

   293  *  @hw: pointer to the HW structure

   294  *

   295  *  Acquire the semaphore to access the Kumeran interface.

   296  *

   297  **/

   298 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   299 {

   300 	u16 mask;

   301 

   302 	mask = E1000_SWFW_CSR_SM;

   303 

   304 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   305 }

   306 

   307 /**

   308  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register

   309  *  @hw: pointer to the HW structure

   310  *

   311  *  Release the semaphore used to access the Kumeran interface

   312  **/

   313 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   314 {

   315 	u16 mask;

   316 

   317 	mask = E1000_SWFW_CSR_SM;

   318 

   319 	e1000_release_swfw_sync_80003es2lan(hw, mask);

   320 }

   321 

   322 /**

   323  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   324  *  @hw: pointer to the HW structure

   325  *

   326  *  Acquire the semaphore to access the EEPROM.

   327  **/

   328 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   329 {

   330 	s32 ret_val;

   331 

   332 	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   333 	if (ret_val)

   334 		return ret_val;

   335 

   336 	ret_val = e1000e_acquire_nvm(hw);

   337 

   338 	if (ret_val)

   339 		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   340 

   341 	return ret_val;

   342 }

   343 

   344 /**

   345  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   346  *  @hw: pointer to the HW structure

   347  *

   348  *  Release the semaphore used to access the EEPROM.

   349  **/

   350 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   351 {

   352 	e1000e_release_nvm(hw);

   353 	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   354 }

   355 

   356 /**

   357  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   358  *  @hw: pointer to the HW structure

   359  *  @mask: specifies which semaphore to acquire

   360  *

   361  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   362  *  will also specify which port we're acquiring the lock for.

   363  **/

   364 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   365 {

   366 	u32 swfw_sync;

   367 	u32 swmask = mask;

   368 	u32 fwmask = mask << 16;

   369 	s32 i = 0;

   370 	s32 timeout = 50;

   371 

   372 	while (i < timeout) {

   373 		if (e1000e_get_hw_semaphore(hw))

   374 			return -E1000_ERR_SWFW_SYNC;

   375 

   376 		swfw_sync = er32(SW_FW_SYNC);

   377 		if (!(swfw_sync & (fwmask | swmask)))

   378 			break;

   379 

   380 		/*

   381 		 * Firmware currently using resource (fwmask)

   382 		 * or other software thread using resource (swmask)

   383 		 */

   384 		e1000e_put_hw_semaphore(hw);

   385 		mdelay(5);

   386 		i++;

   387 	}

   388 

   389 	if (i == timeout) {

   390 		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");

   391 		return -E1000_ERR_SWFW_SYNC;

   392 	}

   393 

   394 	swfw_sync |= swmask;

   395 	ew32(SW_FW_SYNC, swfw_sync);

   396 

   397 	e1000e_put_hw_semaphore(hw);

   398 

   399 	return 0;

   400 }

   401 

   402 /**

   403  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   404  *  @hw: pointer to the HW structure

   405  *  @mask: specifies which semaphore to acquire

   406  *

   407  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   408  *  will also specify which port we're releasing the lock for.

   409  **/

   410 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   411 {

   412 	u32 swfw_sync;

   413 

   414 	while (e1000e_get_hw_semaphore(hw) != 0)

   415 		; /* Empty */

   416 

   417 	swfw_sync = er32(SW_FW_SYNC);

   418 	swfw_sync &= ~mask;

   419 	ew32(SW_FW_SYNC, swfw_sync);

   420 

   421 	e1000e_put_hw_semaphore(hw);

   422 }

   423 

   424 /**

   425  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   426  *  @hw: pointer to the HW structure

   427  *  @offset: offset of the register to read

   428  *  @data: pointer to the data returned from the operation

   429  *

   430  *  Read the GG82563 PHY register.

   431  **/

   432 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   433 						  u32 offset, u16 *data)

   434 {

   435 	s32 ret_val;

   436 	u32 page_select;

   437 	u16 temp;

   438 

   439 	ret_val = e1000_acquire_phy_80003es2lan(hw);

   440 	if (ret_val)

   441 		return ret_val;

   442 

   443 	/* Select Configuration Page */

   444 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   445 		page_select = GG82563_PHY_PAGE_SELECT;

   446 	} else {

   447 		/*

   448 		 * Use Alternative Page Select register to access

   449 		 * registers 30 and 31

   450 		 */

   451 		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   452 	}

   453 

   454 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   455 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   456 	if (ret_val) {

   457 		e1000_release_phy_80003es2lan(hw);

   458 		return ret_val;

   459 	}

   460 

   461 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   462 		/*

   463 		 * The "ready" bit in the MDIC register may be incorrectly set

   464 		 * before the device has completed the "Page Select" MDI

   465 		 * transaction.  So we wait 200us after each MDI command...

   466 		 */

   467 		udelay(200);

   468 

   469 		/* ...and verify the command was successful. */

   470 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   471 

   472 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   473 			e1000_release_phy_80003es2lan(hw);

   474 			return -E1000_ERR_PHY;

   475 		}

   476 

   477 		udelay(200);

   478 

   479 		ret_val = e1000e_read_phy_reg_mdic(hw,

   480 		                                  MAX_PHY_REG_ADDRESS & offset,

   481 		                                  data);

   482 

   483 		udelay(200);

   484 	} else {

   485 		ret_val = e1000e_read_phy_reg_mdic(hw,

   486 		                                  MAX_PHY_REG_ADDRESS & offset,

   487 		                                  data);

   488 	}

   489 

   490 	e1000_release_phy_80003es2lan(hw);

   491 

   492 	return ret_val;

   493 }

   494 

   495 /**

   496  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   497  *  @hw: pointer to the HW structure

   498  *  @offset: offset of the register to read

   499  *  @data: value to write to the register

   500  *

   501  *  Write to the GG82563 PHY register.

   502  **/

   503 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   504 						   u32 offset, u16 data)

   505 {

   506 	s32 ret_val;

   507 	u32 page_select;

   508 	u16 temp;

   509 

   510 	ret_val = e1000_acquire_phy_80003es2lan(hw);

   511 	if (ret_val)

   512 		return ret_val;

   513 

   514 	/* Select Configuration Page */

   515 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   516 		page_select = GG82563_PHY_PAGE_SELECT;

   517 	} else {

   518 		/*

   519 		 * Use Alternative Page Select register to access

   520 		 * registers 30 and 31

   521 		 */

   522 		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   523 	}

   524 

   525 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   526 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   527 	if (ret_val) {

   528 		e1000_release_phy_80003es2lan(hw);

   529 		return ret_val;

   530 	}

   531 

   532 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   533 		/*

   534 		 * The "ready" bit in the MDIC register may be incorrectly set

   535 		 * before the device has completed the "Page Select" MDI

   536 		 * transaction.  So we wait 200us after each MDI command...

   537 		 */

   538 		udelay(200);

   539 

   540 		/* ...and verify the command was successful. */

   541 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   542 

   543 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   544 			e1000_release_phy_80003es2lan(hw);

   545 			return -E1000_ERR_PHY;

   546 		}

   547 

   548 		udelay(200);

   549 

   550 		ret_val = e1000e_write_phy_reg_mdic(hw,

   551 		                                  MAX_PHY_REG_ADDRESS & offset,

   552 		                                  data);

   553 

   554 		udelay(200);

   555 	} else {

   556 		ret_val = e1000e_write_phy_reg_mdic(hw,

   557 		                                  MAX_PHY_REG_ADDRESS & offset,

   558 		                                  data);

   559 	}

   560 

   561 	e1000_release_phy_80003es2lan(hw);

   562 

   563 	return ret_val;

   564 }

   565 

   566 /**

   567  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM

   568  *  @hw: pointer to the HW structure

   569  *  @offset: offset of the register to read

   570  *  @words: number of words to write

   571  *  @data: buffer of data to write to the NVM

   572  *

   573  *  Write "words" of data to the ESB2 NVM.

   574  **/

   575 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,

   576 				       u16 words, u16 *data)

   577 {

   578 	return e1000e_write_nvm_spi(hw, offset, words, data);

   579 }

   580 

   581 /**

   582  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete

   583  *  @hw: pointer to the HW structure

   584  *

   585  *  Wait a specific amount of time for manageability processes to complete.

   586  *  This is a function pointer entry point called by the phy module.

   587  **/

   588 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)

   589 {

   590 	s32 timeout = PHY_CFG_TIMEOUT;

   591 	u32 mask = E1000_NVM_CFG_DONE_PORT_0;

   592 

   593 	if (hw->bus.func == 1)

   594 		mask = E1000_NVM_CFG_DONE_PORT_1;

   595 

   596 	while (timeout) {

   597 		if (er32(EEMNGCTL) & mask)

   598 			break;

   599 		usleep_range(1000, 2000);

   600 		timeout--;

   601 	}

   602 	if (!timeout) {

   603 		e_dbg("MNG configuration cycle has not completed.\n");

   604 		return -E1000_ERR_RESET;

   605 	}

   606 

   607 	return 0;

   608 }

   609 

   610 /**

   611  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex

   612  *  @hw: pointer to the HW structure

   613  *

   614  *  Force the speed and duplex settings onto the PHY.  This is a

   615  *  function pointer entry point called by the phy module.

   616  **/

   617 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)

   618 {

   619 	s32 ret_val;

   620 	u16 phy_data;

   621 	bool link;

   622 

   623 	/*

   624 	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI

   625 	 * forced whenever speed and duplex are forced.

   626 	 */

   627 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

   628 	if (ret_val)

   629 		return ret_val;

   630 

   631 	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;

   632 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);

   633 	if (ret_val)

   634 		return ret_val;

   635 

   636 	e_dbg("GG82563 PSCR: %X\n", phy_data);

   637 

   638 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);

   639 	if (ret_val)

   640 		return ret_val;

   641 

   642 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);

   643 

   644 	/* Reset the phy to commit changes. */

   645 	phy_data |= MII_CR_RESET;

   646 

   647 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);

   648 	if (ret_val)

   649 		return ret_val;

   650 

   651 	udelay(1);

   652 

   653 	if (hw->phy.autoneg_wait_to_complete) {

   654 		e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");

   655 

   656 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,

   657 						     100000, &link);

   658 		if (ret_val)

   659 			return ret_val;

   660 

   661 		if (!link) {

   662 			/*

   663 			 * We didn't get link.

   664 			 * Reset the DSP and cross our fingers.

   665 			 */

   666 			ret_val = e1000e_phy_reset_dsp(hw);

   667 			if (ret_val)

   668 				return ret_val;

   669 		}

   670 

   671 		/* Try once more */

   672 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,

   673 						     100000, &link);

   674 		if (ret_val)

   675 			return ret_val;

   676 	}

   677 

   678 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);

   679 	if (ret_val)

   680 		return ret_val;

   681 

   682 	/*

   683 	 * Resetting the phy means we need to verify the TX_CLK corresponds

   684 	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.

   685 	 */

   686 	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;

   687 	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)

   688 		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;

   689 	else

   690 		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;

   691 

   692 	/*

   693 	 * In addition, we must re-enable CRS on Tx for both half and full

   694 	 * duplex.

   695 	 */

   696 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;

   697 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);

   698 

   699 	return ret_val;

   700 }

   701 

   702 /**

   703  *  e1000_get_cable_length_80003es2lan - Set approximate cable length

   704  *  @hw: pointer to the HW structure

   705  *

   706  *  Find the approximate cable length as measured by the GG82563 PHY.

   707  *  This is a function pointer entry point called by the phy module.

   708  **/

   709 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)

   710 {

   711 	struct e1000_phy_info *phy = &hw->phy;

   712 	s32 ret_val = 0;

   713 	u16 phy_data, index;

   714 

   715 	ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);

   716 	if (ret_val)

   717 		return ret_val;

   718 

   719 	index = phy_data & GG82563_DSPD_CABLE_LENGTH;

   720 

   721 	if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)

   722 		return -E1000_ERR_PHY;

   723 

   724 	phy->min_cable_length = e1000_gg82563_cable_length_table[index];

   725 	phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];

   726 

   727 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;

   728 

   729 	return 0;

   730 }

   731 

   732 /**

   733  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex

   734  *  @hw: pointer to the HW structure

   735  *  @speed: pointer to speed buffer

   736  *  @duplex: pointer to duplex buffer

   737  *

   738  *  Retrieve the current speed and duplex configuration.

   739  **/

   740 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,

   741 					      u16 *duplex)

   742 {

   743 	s32 ret_val;

   744 

   745 	if (hw->phy.media_type == e1000_media_type_copper) {

   746 		ret_val = e1000e_get_speed_and_duplex_copper(hw,

   747 								    speed,

   748 								    duplex);

   749 		hw->phy.ops.cfg_on_link_up(hw);

   750 	} else {

   751 		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,

   752 								  speed,

   753 								  duplex);

   754 	}

   755 

   756 	return ret_val;

   757 }

   758 

   759 /**

   760  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller

   761  *  @hw: pointer to the HW structure

   762  *

   763  *  Perform a global reset to the ESB2 controller.

   764  **/

   765 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)

   766 {

   767 	u32 ctrl;

   768 	s32 ret_val;

   769 

   770 	/*

   771 	 * Prevent the PCI-E bus from sticking if there is no TLP connection

   772 	 * on the last TLP read/write transaction when MAC is reset.

   773 	 */

   774 	ret_val = e1000e_disable_pcie_master(hw);

   775 	if (ret_val)

   776 		e_dbg("PCI-E Master disable polling has failed.\n");

   777 

   778 	e_dbg("Masking off all interrupts\n");

   779 	ew32(IMC, 0xffffffff);

   780 

   781 	ew32(RCTL, 0);

   782 	ew32(TCTL, E1000_TCTL_PSP);

   783 	e1e_flush();

   784 

   785 	usleep_range(10000, 20000);

   786 

   787 	ctrl = er32(CTRL);

   788 

   789 	ret_val = e1000_acquire_phy_80003es2lan(hw);

   790 	e_dbg("Issuing a global reset to MAC\n");

   791 	ew32(CTRL, ctrl | E1000_CTRL_RST);

   792 	e1000_release_phy_80003es2lan(hw);

   793 

   794 	ret_val = e1000e_get_auto_rd_done(hw);

   795 	if (ret_val)

   796 		/* We don't want to continue accessing MAC registers. */

   797 		return ret_val;

   798 

   799 	/* Clear any pending interrupt events. */

   800 	ew32(IMC, 0xffffffff);

   801 	er32(ICR);

   802 

   803 	return e1000_check_alt_mac_addr_generic(hw);

   804 }

   805 

   806 /**

   807  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller

   808  *  @hw: pointer to the HW structure

   809  *

   810  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.

   811  **/

   812 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)

   813 {

   814 	struct e1000_mac_info *mac = &hw->mac;

   815 	u32 reg_data;

   816 	s32 ret_val;

   817 	u16 kum_reg_data;

   818 	u16 i;

   819 

   820 	e1000_initialize_hw_bits_80003es2lan(hw);

   821 

   822 	/* Initialize identification LED */

   823 	ret_val = mac->ops.id_led_init(hw);

   824 	if (ret_val)

   825 		e_dbg("Error initializing identification LED\n");

   826 		/* This is not fatal and we should not stop init due to this */

   827 

   828 	/* Disabling VLAN filtering */

   829 	e_dbg("Initializing the IEEE VLAN\n");

   830 	mac->ops.clear_vfta(hw);

   831 

   832 	/* Setup the receive address. */

   833 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);

   834 

   835 	/* Zero out the Multicast HASH table */

   836 	e_dbg("Zeroing the MTA\n");

   837 	for (i = 0; i < mac->mta_reg_count; i++)

   838 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

   839 

   840 	/* Setup link and flow control */

   841 	ret_val = mac->ops.setup_link(hw);

   842 

   843 	/* Disable IBIST slave mode (far-end loopback) */

   844 	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

   845 					&kum_reg_data);

   846 	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;

   847 	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

   848 					 kum_reg_data);

   849 

   850 	/* Set the transmit descriptor write-back policy */

   851 	reg_data = er32(TXDCTL(0));

   852 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

   853 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;

   854 	ew32(TXDCTL(0), reg_data);

   855 

   856 	/* ...for both queues. */

   857 	reg_data = er32(TXDCTL(1));

   858 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

   859 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;

   860 	ew32(TXDCTL(1), reg_data);

   861 

   862 	/* Enable retransmit on late collisions */

   863 	reg_data = er32(TCTL);

   864 	reg_data |= E1000_TCTL_RTLC;

   865 	ew32(TCTL, reg_data);

   866 

   867 	/* Configure Gigabit Carry Extend Padding */

   868 	reg_data = er32(TCTL_EXT);

   869 	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;

   870 	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;

   871 	ew32(TCTL_EXT, reg_data);

   872 

   873 	/* Configure Transmit Inter-Packet Gap */

   874 	reg_data = er32(TIPG);

   875 	reg_data &= ~E1000_TIPG_IPGT_MASK;

   876 	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;

   877 	ew32(TIPG, reg_data);

   878 

   879 	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);

   880 	reg_data &= ~0x00100000;

   881 	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);

   882 

   883 	/* default to true to enable the MDIC W/A */

   884 	hw->dev_spec.e80003es2lan.mdic_wa_enable = true;

   885 

   886 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

   887 	                              E1000_KMRNCTRLSTA_OFFSET >>

   888 	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,

   889 	                              &i);

   890 	if (!ret_val) {

   891 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==

   892 		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)

   893 			hw->dev_spec.e80003es2lan.mdic_wa_enable = false;

   894 	}

   895 

   896 	/*

   897 	 * Clear all of the statistics registers (clear on read).  It is

   898 	 * important that we do this after we have tried to establish link

   899 	 * because the symbol error count will increment wildly if there

   900 	 * is no link.

   901 	 */

   902 	e1000_clear_hw_cntrs_80003es2lan(hw);

   903 

   904 	return ret_val;

   905 }

   906 

   907 /**

   908  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2

   909  *  @hw: pointer to the HW structure

   910  *

   911  *  Initializes required hardware-dependent bits needed for normal operation.

   912  **/

   913 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)

   914 {

   915 	u32 reg;

   916 

   917 	/* Transmit Descriptor Control 0 */

   918 	reg = er32(TXDCTL(0));

   919 	reg |= (1 << 22);

   920 	ew32(TXDCTL(0), reg);

   921 

   922 	/* Transmit Descriptor Control 1 */

   923 	reg = er32(TXDCTL(1));

   924 	reg |= (1 << 22);

   925 	ew32(TXDCTL(1), reg);

   926 

   927 	/* Transmit Arbitration Control 0 */

   928 	reg = er32(TARC(0));

   929 	reg &= ~(0xF << 27); /* 30:27 */

   930 	if (hw->phy.media_type != e1000_media_type_copper)

   931 		reg &= ~(1 << 20);

   932 	ew32(TARC(0), reg);

   933 

   934 	/* Transmit Arbitration Control 1 */

   935 	reg = er32(TARC(1));

   936 	if (er32(TCTL) & E1000_TCTL_MULR)

   937 		reg &= ~(1 << 28);

   938 	else

   939 		reg |= (1 << 28);

   940 	ew32(TARC(1), reg);

   941 }

   942 

   943 /**

   944  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link

   945  *  @hw: pointer to the HW structure

   946  *

   947  *  Setup some GG82563 PHY registers for obtaining link

   948  **/

   949 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)

   950 {

   951 	struct e1000_phy_info *phy = &hw->phy;

   952 	s32 ret_val;

   953 	u32 ctrl_ext;

   954 	u16 data;

   955 

   956 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);

   957 	if (ret_val)

   958 		return ret_val;

   959 

   960 	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;

   961 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */

   962 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;

   963 

   964 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);

   965 	if (ret_val)

   966 		return ret_val;

   967 

   968 	/*

   969 	 * Options:

   970 	 *   MDI/MDI-X = 0 (default)

   971 	 *   0 - Auto for all speeds

   972 	 *   1 - MDI mode

   973 	 *   2 - MDI-X mode

   974 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)

   975 	 */

   976 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);

   977 	if (ret_val)

   978 		return ret_val;

   979 

   980 	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;

   981 

   982 	switch (phy->mdix) {

   983 	case 1:

   984 		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;

   985 		break;

   986 	case 2:

   987 		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;

   988 		break;

   989 	case 0:

   990 	default:

   991 		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;

   992 		break;

   993 	}

   994 

   995 	/*

   996 	 * Options:

   997 	 *   disable_polarity_correction = 0 (default)

   998 	 *       Automatic Correction for Reversed Cable Polarity

   999 	 *   0 - Disabled

  1000 	 *   1 - Enabled

  1001 	 */

  1002 	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;

  1003 	if (phy->disable_polarity_correction)

  1004 		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;

  1005 

  1006 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);

  1007 	if (ret_val)

  1008 		return ret_val;

  1009 

  1010 	/* SW Reset the PHY so all changes take effect */

  1011 	ret_val = e1000e_commit_phy(hw);

  1012 	if (ret_val) {

  1013 		e_dbg("Error Resetting the PHY\n");

  1014 		return ret_val;

  1015 	}

  1016 

  1017 	/* Bypass Rx and Tx FIFO's */

  1018 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

  1019 					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,

  1020 					E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |

  1021 					E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);

  1022 	if (ret_val)

  1023 		return ret_val;

  1024 

  1025 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

  1026 				       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,

  1027 				       &data);

  1028 	if (ret_val)

  1029 		return ret_val;

  1030 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;

  1031 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

  1032 					E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,

  1033 					data);

  1034 	if (ret_val)

  1035 		return ret_val;

  1036 

  1037 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);

  1038 	if (ret_val)

  1039 		return ret_val;

  1040 

  1041 	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;

  1042 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);

  1043 	if (ret_val)

  1044 		return ret_val;

  1045 

  1046 	ctrl_ext = er32(CTRL_EXT);

  1047 	ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);

  1048 	ew32(CTRL_EXT, ctrl_ext);

  1049 

  1050 	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);

  1051 	if (ret_val)

  1052 		return ret_val;

  1053 

  1054 	/*

  1055 	 * Do not init these registers when the HW is in IAMT mode, since the

  1056 	 * firmware will have already initialized them.  We only initialize

  1057 	 * them if the HW is not in IAMT mode.

  1058 	 */

  1059 	if (!hw->mac.ops.check_mng_mode(hw)) {

  1060 		/* Enable Electrical Idle on the PHY */

  1061 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;

  1062 		ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);

  1063 		if (ret_val)

  1064 			return ret_val;

  1065 

  1066 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);

  1067 		if (ret_val)

  1068 			return ret_val;

  1069 

  1070 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;

  1071 		ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);

  1072 		if (ret_val)

  1073 			return ret_val;

  1074 	}

  1075 

  1076 	/*

  1077 	 * Workaround: Disable padding in Kumeran interface in the MAC

  1078 	 * and in the PHY to avoid CRC errors.

  1079 	 */

  1080 	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);

  1081 	if (ret_val)

  1082 		return ret_val;

  1083 

  1084 	data |= GG82563_ICR_DIS_PADDING;

  1085 	ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);

  1086 	if (ret_val)

  1087 		return ret_val;

  1088 

  1089 	return 0;

  1090 }

  1091 

  1092 /**

  1093  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2

  1094  *  @hw: pointer to the HW structure

  1095  *

  1096  *  Essentially a wrapper for setting up all things "copper" related.

  1097  *  This is a function pointer entry point called by the mac module.

  1098  **/

  1099 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)

  1100 {

  1101 	u32 ctrl;

  1102 	s32 ret_val;

  1103 	u16 reg_data;

  1104 

  1105 	ctrl = er32(CTRL);

  1106 	ctrl |= E1000_CTRL_SLU;

  1107 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1108 	ew32(CTRL, ctrl);

  1109 

  1110 	/*

  1111 	 * Set the mac to wait the maximum time between each

  1112 	 * iteration and increase the max iterations when

  1113 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.

  1114 	 */

  1115 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),

  1116 	                                           0xFFFF);

  1117 	if (ret_val)

  1118 		return ret_val;

  1119 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),

  1120 	                                          &reg_data);

  1121 	if (ret_val)

  1122 		return ret_val;

  1123 	reg_data |= 0x3F;

  1124 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),

  1125 	                                           reg_data);

  1126 	if (ret_val)

  1127 		return ret_val;

  1128 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

  1129 				      E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,

  1130 				      &reg_data);

  1131 	if (ret_val)

  1132 		return ret_val;

  1133 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;

  1134 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

  1135 					E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,

  1136 					reg_data);