1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27  */

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000.h"

    34 

    35 static s32 e1000_check_downshift(struct e1000_hw *hw);

    36 static s32 e1000_check_polarity(struct e1000_hw *hw,

    37 				e1000_rev_polarity *polarity);

    38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39 static void e1000_clear_vfta(struct e1000_hw *hw);

    40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41 					      bool link_up);

    42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46 				  u16 *max_length);

    47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48 static s32 e1000_id_led_init(struct e1000_hw *hw);

    49 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51 				  struct e1000_phy_info *phy_info);

    52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53 				  struct e1000_phy_info *phy_info);

    54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58 static void e1000_phy_init_script(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70 				  u16 words, u16 *data);

    71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72 					u16 words, u16 *data);

    73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78 				  u16 phy_data);

    79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80 				 u16 *phy_data);

    81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83 static void e1000_release_eeprom(struct e1000_hw *hw);

    84 static void e1000_standby_eeprom(struct e1000_hw *hw);

    85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89 				u16 *data);

    90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91 				 u16 *data);

    92 

    93 /* IGP cable length table */

    94 static const

    95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102 	    100,

   103 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104 	    110, 110,

   105 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106 	    120, 120

   107 };

   108 

   109 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110 static DEFINE_SPINLOCK(e1000_phy_lock);

   111 

   112 /**

   113  * e1000_set_phy_type - Set the phy type member in the hw struct.

   114  * @hw: Struct containing variables accessed by shared code

   115  */

   116 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   117 {

   118 	if (hw->mac_type == e1000_undefined)

   119 		return -E1000_ERR_PHY_TYPE;

   120 

   121 	switch (hw->phy_id) {

   122 	case M88E1000_E_PHY_ID:

   123 	case M88E1000_I_PHY_ID:

   124 	case M88E1011_I_PHY_ID:

   125 	case M88E1111_I_PHY_ID:

   126 	case M88E1118_E_PHY_ID:

   127 		hw->phy_type = e1000_phy_m88;

   128 		break;

   129 	case IGP01E1000_I_PHY_ID:

   130 		if (hw->mac_type == e1000_82541 ||

   131 		    hw->mac_type == e1000_82541_rev_2 ||

   132 		    hw->mac_type == e1000_82547 ||

   133 		    hw->mac_type == e1000_82547_rev_2)

   134 			hw->phy_type = e1000_phy_igp;

   135 		break;

   136 	case RTL8211B_PHY_ID:

   137 		hw->phy_type = e1000_phy_8211;

   138 		break;

   139 	case RTL8201N_PHY_ID:

   140 		hw->phy_type = e1000_phy_8201;

   141 		break;

   142 	default:

   143 		/* Should never have loaded on this device */

   144 		hw->phy_type = e1000_phy_undefined;

   145 		return -E1000_ERR_PHY_TYPE;

   146 	}

   147 

   148 	return E1000_SUCCESS;

   149 }

   150 

   151 /**

   152  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   153  * @hw: Struct containing variables accessed by shared code

   154  */

   155 static void e1000_phy_init_script(struct e1000_hw *hw)

   156 {

   157 	u32 ret_val;

   158 	u16 phy_saved_data;

   159 

   160 	if (hw->phy_init_script) {

   161 		msleep(20);

   162 

   163 		/* Save off the current value of register 0x2F5B to be restored

   164 		 * at the end of this routine.

   165 		 */

   166 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   167 

   168 		/* Disabled the PHY transmitter */

   169 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   170 		msleep(20);

   171 

   172 		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   173 		msleep(5);

   174 

   175 		switch (hw->mac_type) {

   176 		case e1000_82541:

   177 		case e1000_82547:

   178 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   179 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   180 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   181 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   182 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   183 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   184 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   185 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   186 			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   187 			break;

   188 

   189 		case e1000_82541_rev_2:

   190 		case e1000_82547_rev_2:

   191 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   192 			break;

   193 		default:

   194 			break;

   195 		}

   196 

   197 		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   198 		msleep(20);

   199 

   200 		/* Now enable the transmitter */

   201 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   202 

   203 		if (hw->mac_type == e1000_82547) {

   204 			u16 fused, fine, coarse;

   205 

   206 			/* Move to analog registers page */

   207 			e1000_read_phy_reg(hw,

   208 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   209 					   &fused);

   210 

   211 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   212 				e1000_read_phy_reg(hw,

   213 						   IGP01E1000_ANALOG_FUSE_STATUS,

   214 						   &fused);

   215 

   216 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   217 				coarse =

   218 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   219 

   220 				if (coarse >

   221 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   222 					coarse -=

   223 					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   224 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   225 				} else if (coarse ==

   226 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   227 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   228 

   229 				fused =

   230 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   231 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   232 				    (coarse &

   233 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   234 

   235 				e1000_write_phy_reg(hw,

   236 						    IGP01E1000_ANALOG_FUSE_CONTROL,

   237 						    fused);

   238 				e1000_write_phy_reg(hw,

   239 						    IGP01E1000_ANALOG_FUSE_BYPASS,

   240 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   241 			}

   242 		}

   243 	}

   244 }

   245 

   246 /**

   247  * e1000_set_mac_type - Set the mac type member in the hw struct.

   248  * @hw: Struct containing variables accessed by shared code

   249  */

   250 s32 e1000_set_mac_type(struct e1000_hw *hw)

   251 {

   252 	switch (hw->device_id) {

   253 	case E1000_DEV_ID_82542:

   254 		switch (hw->revision_id) {

   255 		case E1000_82542_2_0_REV_ID:

   256 			hw->mac_type = e1000_82542_rev2_0;

   257 			break;

   258 		case E1000_82542_2_1_REV_ID:

   259 			hw->mac_type = e1000_82542_rev2_1;

   260 			break;

   261 		default:

   262 			/* Invalid 82542 revision ID */

   263 			return -E1000_ERR_MAC_TYPE;

   264 		}

   265 		break;

   266 	case E1000_DEV_ID_82543GC_FIBER:

   267 	case E1000_DEV_ID_82543GC_COPPER:

   268 		hw->mac_type = e1000_82543;

   269 		break;

   270 	case E1000_DEV_ID_82544EI_COPPER:

   271 	case E1000_DEV_ID_82544EI_FIBER:

   272 	case E1000_DEV_ID_82544GC_COPPER:

   273 	case E1000_DEV_ID_82544GC_LOM:

   274 		hw->mac_type = e1000_82544;

   275 		break;

   276 	case E1000_DEV_ID_82540EM:

   277 	case E1000_DEV_ID_82540EM_LOM:

   278 	case E1000_DEV_ID_82540EP:

   279 	case E1000_DEV_ID_82540EP_LOM:

   280 	case E1000_DEV_ID_82540EP_LP:

   281 		hw->mac_type = e1000_82540;

   282 		break;

   283 	case E1000_DEV_ID_82545EM_COPPER:

   284 	case E1000_DEV_ID_82545EM_FIBER:

   285 		hw->mac_type = e1000_82545;

   286 		break;

   287 	case E1000_DEV_ID_82545GM_COPPER:

   288 	case E1000_DEV_ID_82545GM_FIBER:

   289 	case E1000_DEV_ID_82545GM_SERDES:

   290 		hw->mac_type = e1000_82545_rev_3;

   291 		break;

   292 	case E1000_DEV_ID_82546EB_COPPER:

   293 	case E1000_DEV_ID_82546EB_FIBER:

   294 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   295 		hw->mac_type = e1000_82546;

   296 		break;

   297 	case E1000_DEV_ID_82546GB_COPPER:

   298 	case E1000_DEV_ID_82546GB_FIBER:

   299 	case E1000_DEV_ID_82546GB_SERDES:

   300 	case E1000_DEV_ID_82546GB_PCIE:

   301 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   302 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   303 		hw->mac_type = e1000_82546_rev_3;

   304 		break;

   305 	case E1000_DEV_ID_82541EI:

   306 	case E1000_DEV_ID_82541EI_MOBILE:

   307 	case E1000_DEV_ID_82541ER_LOM:

   308 		hw->mac_type = e1000_82541;

   309 		break;

   310 	case E1000_DEV_ID_82541ER:

   311 	case E1000_DEV_ID_82541GI:

   312 	case E1000_DEV_ID_82541GI_LF:

   313 	case E1000_DEV_ID_82541GI_MOBILE:

   314 		hw->mac_type = e1000_82541_rev_2;

   315 		break;

   316 	case E1000_DEV_ID_82547EI:

   317 	case E1000_DEV_ID_82547EI_MOBILE:

   318 		hw->mac_type = e1000_82547;

   319 		break;

   320 	case E1000_DEV_ID_82547GI:

   321 		hw->mac_type = e1000_82547_rev_2;

   322 		break;

   323 	case E1000_DEV_ID_INTEL_CE4100_GBE:

   324 		hw->mac_type = e1000_ce4100;

   325 		break;

   326 	default:

   327 		/* Should never have loaded on this device */

   328 		return -E1000_ERR_MAC_TYPE;

   329 	}

   330 

   331 	switch (hw->mac_type) {

   332 	case e1000_82541:

   333 	case e1000_82547:

   334 	case e1000_82541_rev_2:

   335 	case e1000_82547_rev_2:

   336 		hw->asf_firmware_present = true;

   337 		break;

   338 	default:

   339 		break;

   340 	}

   341 

   342 	/* The 82543 chip does not count tx_carrier_errors properly in

   343 	 * FD mode

   344 	 */

   345 	if (hw->mac_type == e1000_82543)

   346 		hw->bad_tx_carr_stats_fd = true;

   347 

   348 	if (hw->mac_type > e1000_82544)

   349 		hw->has_smbus = true;

   350 

   351 	return E1000_SUCCESS;

   352 }

   353 

   354 /**

   355  * e1000_set_media_type - Set media type and TBI compatibility.

   356  * @hw: Struct containing variables accessed by shared code

   357  */

   358 void e1000_set_media_type(struct e1000_hw *hw)

   359 {

   360 	u32 status;

   361 

   362 	if (hw->mac_type != e1000_82543) {

   363 		/* tbi_compatibility is only valid on 82543 */

   364 		hw->tbi_compatibility_en = false;

   365 	}

   366 

   367 	switch (hw->device_id) {

   368 	case E1000_DEV_ID_82545GM_SERDES:

   369 	case E1000_DEV_ID_82546GB_SERDES:

   370 		hw->media_type = e1000_media_type_internal_serdes;

   371 		break;

   372 	default:

   373 		switch (hw->mac_type) {

   374 		case e1000_82542_rev2_0:

   375 		case e1000_82542_rev2_1:

   376 			hw->media_type = e1000_media_type_fiber;

   377 			break;

   378 		case e1000_ce4100:

   379 			hw->media_type = e1000_media_type_copper;

   380 			break;

   381 		default:

   382 			status = er32(STATUS);

   383 			if (status & E1000_STATUS_TBIMODE) {

   384 				hw->media_type = e1000_media_type_fiber;

   385 				/* tbi_compatibility not valid on fiber */

   386 				hw->tbi_compatibility_en = false;

   387 			} else {

   388 				hw->media_type = e1000_media_type_copper;

   389 			}

   390 			break;

   391 		}

   392 	}

   393 }

   394 

   395 /**

   396  * e1000_reset_hw - reset the hardware completely

   397  * @hw: Struct containing variables accessed by shared code

   398  *

   399  * Reset the transmit and receive units; mask and clear all interrupts.

   400  */

   401 s32 e1000_reset_hw(struct e1000_hw *hw)

   402 {

   403 	u32 ctrl;

   404 	u32 ctrl_ext;

   405 	u32 icr;

   406 	u32 manc;

   407 	u32 led_ctrl;

   408 	s32 ret_val;

   409 

   410 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   411 	if (hw->mac_type == e1000_82542_rev2_0) {

   412 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   413 		e1000_pci_clear_mwi(hw);

   414 	}

   415 

   416 	/* Clear interrupt mask to stop board from generating interrupts */

   417 	e_dbg("Masking off all interrupts\n");

   418 	ew32(IMC, 0xffffffff);

   419 

   420 	/* Disable the Transmit and Receive units.  Then delay to allow

   421 	 * any pending transactions to complete before we hit the MAC with

   422 	 * the global reset.

   423 	 */

   424 	ew32(RCTL, 0);

   425 	ew32(TCTL, E1000_TCTL_PSP);

   426 	E1000_WRITE_FLUSH();

   427 

   428 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   429 	hw->tbi_compatibility_on = false;

   430 

   431 	/* Delay to allow any outstanding PCI transactions to complete before

   432 	 * resetting the device

   433 	 */

   434 	msleep(10);

   435 

   436 	ctrl = er32(CTRL);

   437 

   438 	/* Must reset the PHY before resetting the MAC */

   439 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   440 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   441 		E1000_WRITE_FLUSH();

   442 		msleep(5);

   443 	}

   444 

   445 	/* Issue a global reset to the MAC.  This will reset the chip's

   446 	 * transmit, receive, DMA, and link units.  It will not effect

   447 	 * the current PCI configuration.  The global reset bit is self-

   448 	 * clearing, and should clear within a microsecond.

   449 	 */

   450 	e_dbg("Issuing a global reset to MAC\n");

   451 

   452 	switch (hw->mac_type) {

   453 	case e1000_82544:

   454 	case e1000_82540:

   455 	case e1000_82545:

   456 	case e1000_82546:

   457 	case e1000_82541:

   458 	case e1000_82541_rev_2:

   459 		/* These controllers can't ack the 64-bit write when issuing the

   460 		 * reset, so use IO-mapping as a workaround to issue the reset

   461 		 */

   462 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   463 		break;

   464 	case e1000_82545_rev_3:

   465 	case e1000_82546_rev_3:

   466 		/* Reset is performed on a shadow of the control register */

   467 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   468 		break;

   469 	case e1000_ce4100:

   470 	default:

   471 		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   472 		break;

   473 	}

   474 

   475 	/* After MAC reset, force reload of EEPROM to restore power-on settings

   476 	 * to device.  Later controllers reload the EEPROM automatically, so

   477 	 * just wait for reload to complete.

   478 	 */

   479 	switch (hw->mac_type) {

   480 	case e1000_82542_rev2_0:

   481 	case e1000_82542_rev2_1:

   482 	case e1000_82543:

   483 	case e1000_82544:

   484 		/* Wait for reset to complete */

   485 		udelay(10);

   486 		ctrl_ext = er32(CTRL_EXT);

   487 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   488 		ew32(CTRL_EXT, ctrl_ext);

   489 		E1000_WRITE_FLUSH();

   490 		/* Wait for EEPROM reload */

   491 		msleep(2);

   492 		break;

   493 	case e1000_82541:

   494 	case e1000_82541_rev_2:

   495 	case e1000_82547:

   496 	case e1000_82547_rev_2:

   497 		/* Wait for EEPROM reload */

   498 		msleep(20);

   499 		break;

   500 	default:

   501 		/* Auto read done will delay 5ms or poll based on mac type */

   502 		ret_val = e1000_get_auto_rd_done(hw);

   503 		if (ret_val)

   504 			return ret_val;

   505 		break;

   506 	}

   507 

   508 	/* Disable HW ARPs on ASF enabled adapters */

   509 	if (hw->mac_type >= e1000_82540) {

   510 		manc = er32(MANC);

   511 		manc &= ~(E1000_MANC_ARP_EN);

   512 		ew32(MANC, manc);

   513 	}

   514 

   515 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   516 		e1000_phy_init_script(hw);

   517 

   518 		/* Configure activity LED after PHY reset */

   519 		led_ctrl = er32(LEDCTL);

   520 		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   521 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   522 		ew32(LEDCTL, led_ctrl);

   523 	}

   524 

   525 	/* Clear interrupt mask to stop board from generating interrupts */

   526 	e_dbg("Masking off all interrupts\n");

   527 	ew32(IMC, 0xffffffff);

   528 

   529 	/* Clear any pending interrupt events. */

   530 	icr = er32(ICR);

   531 

   532 	/* If MWI was previously enabled, reenable it. */

   533 	if (hw->mac_type == e1000_82542_rev2_0) {

   534 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   535 			e1000_pci_set_mwi(hw);

   536 	}

   537 

   538 	return E1000_SUCCESS;

   539 }

   540 

   541 /**

   542  * e1000_init_hw - Performs basic configuration of the adapter.

   543  * @hw: Struct containing variables accessed by shared code

   544  *

   545  * Assumes that the controller has previously been reset and is in a

   546  * post-reset uninitialized state. Initializes the receive address registers,

   547  * multicast table, and VLAN filter table. Calls routines to setup link

   548  * configuration and flow control settings. Clears all on-chip counters. Leaves

   549  * the transmit and receive units disabled and uninitialized.

   550  */

   551 s32 e1000_init_hw(struct e1000_hw *hw)

   552 {

   553 	u32 ctrl;

   554 	u32 i;

   555 	s32 ret_val;

   556 	u32 mta_size;

   557 	u32 ctrl_ext;

   558 

   559 	/* Initialize Identification LED */

   560 	ret_val = e1000_id_led_init(hw);

   561 	if (ret_val) {

   562 		e_dbg("Error Initializing Identification LED\n");

   563 		return ret_val;

   564 	}

   565 

   566 	/* Set the media type and TBI compatibility */

   567 	e1000_set_media_type(hw);

   568 

   569 	/* Disabling VLAN filtering. */

   570 	e_dbg("Initializing the IEEE VLAN\n");

   571 	if (hw->mac_type < e1000_82545_rev_3)

   572 		ew32(VET, 0);

   573 	e1000_clear_vfta(hw);

   574 

   575 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   576 	if (hw->mac_type == e1000_82542_rev2_0) {

   577 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   578 		e1000_pci_clear_mwi(hw);

   579 		ew32(RCTL, E1000_RCTL_RST);

   580 		E1000_WRITE_FLUSH();

   581 		msleep(5);

   582 	}

   583 

   584 	/* Setup the receive address. This involves initializing all of the

   585 	 * Receive Address Registers (RARs 0 - 15).

   586 	 */

   587 	e1000_init_rx_addrs(hw);

   588 

   589 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   590 	if (hw->mac_type == e1000_82542_rev2_0) {

   591 		ew32(RCTL, 0);

   592 		E1000_WRITE_FLUSH();

   593 		msleep(1);

   594 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   595 			e1000_pci_set_mwi(hw);

   596 	}

   597 

   598 	/* Zero out the Multicast HASH table */

   599 	e_dbg("Zeroing the MTA\n");

   600 	mta_size = E1000_MC_TBL_SIZE;

   601 	for (i = 0; i < mta_size; i++) {

   602 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   603 		/* use write flush to prevent Memory Write Block (MWB) from

   604 		 * occurring when accessing our register space

   605 		 */

   606 		E1000_WRITE_FLUSH();

   607 	}

   608 

   609 	/* Set the PCI priority bit correctly in the CTRL register.  This

   610 	 * determines if the adapter gives priority to receives, or if it

   611 	 * gives equal priority to transmits and receives.  Valid only on

   612 	 * 82542 and 82543 silicon.

   613 	 */

   614 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   615 		ctrl = er32(CTRL);

   616 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   617 	}

   618 

   619 	switch (hw->mac_type) {

   620 	case e1000_82545_rev_3:

   621 	case e1000_82546_rev_3:

   622 		break;

   623 	default:

   624 		/* Workaround for PCI-X problem when BIOS sets MMRBC

   625 		 * incorrectly.

   626 		 */

   627 		if (hw->bus_type == e1000_bus_type_pcix

   628 		    && e1000_pcix_get_mmrbc(hw) > 2048)

   629 			e1000_pcix_set_mmrbc(hw, 2048);

   630 		break;

   631 	}

   632 

   633 	/* Call a subroutine to configure the link and setup flow control. */

   634 	ret_val = e1000_setup_link(hw);

   635 

   636 	/* Set the transmit descriptor write-back policy */

   637 	if (hw->mac_type > e1000_82544) {

   638 		ctrl = er32(TXDCTL);

   639 		ctrl =

   640 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |

   641 		    E1000_TXDCTL_FULL_TX_DESC_WB;

   642 		ew32(TXDCTL, ctrl);

   643 	}

   644 

   645 	/* Clear all of the statistics registers (clear on read).  It is

   646 	 * important that we do this after we have tried to establish link

   647 	 * because the symbol error count will increment wildly if there

   648 	 * is no link.

   649 	 */

   650 	e1000_clear_hw_cntrs(hw);

   651 

   652 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   653 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   654 		ctrl_ext = er32(CTRL_EXT);

   655 		/* Relaxed ordering must be disabled to avoid a parity

   656 		 * error crash in a PCI slot.

   657 		 */

   658 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   659 		ew32(CTRL_EXT, ctrl_ext);

   660 	}

   661 

   662 	return ret_val;

   663 }

   664 

   665 /**

   666  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.

   667  * @hw: Struct containing variables accessed by shared code.

   668  */

   669 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   670 {

   671 	u16 eeprom_data;

   672 	s32 ret_val;

   673 

   674 	if (hw->media_type != e1000_media_type_internal_serdes)

   675 		return E1000_SUCCESS;

   676 

   677 	switch (hw->mac_type) {

   678 	case e1000_82545_rev_3:

   679 	case e1000_82546_rev_3:

   680 		break;

   681 	default:

   682 		return E1000_SUCCESS;

   683 	}

   684 

   685 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,

   686 	                            &eeprom_data);

   687 	if (ret_val) {

   688 		return ret_val;

   689 	}

   690 

   691 	if (eeprom_data != EEPROM_RESERVED_WORD) {

   692 		/* Adjust SERDES output amplitude only. */

   693 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   694 		ret_val =

   695 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   696 		if (ret_val)

   697 			return ret_val;

   698 	}

   699 

   700 	return E1000_SUCCESS;

   701 }

   702 

   703 /**

   704  * e1000_setup_link - Configures flow control and link settings.

   705  * @hw: Struct containing variables accessed by shared code

   706  *

   707  * Determines which flow control settings to use. Calls the appropriate media-

   708  * specific link configuration function. Configures the flow control settings.

   709  * Assuming the adapter has a valid link partner, a valid link should be

   710  * established. Assumes the hardware has previously been reset and the

   711  * transmitter and receiver are not enabled.

   712  */

   713 s32 e1000_setup_link(struct e1000_hw *hw)

   714 {

   715 	u32 ctrl_ext;

   716 	s32 ret_val;

   717 	u16 eeprom_data;

   718 

   719 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   720 	 * that determine the hardware's default PAUSE (flow control) mode,

   721 	 * a bit that determines whether the HW defaults to enabling or

   722 	 * disabling auto-negotiation, and the direction of the

   723 	 * SW defined pins. If there is no SW over-ride of the flow

   724 	 * control setting, then the variable hw->fc will

   725 	 * be initialized based on a value in the EEPROM.

   726 	 */

   727 	if (hw->fc == E1000_FC_DEFAULT) {

   728 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   729 					    1, &eeprom_data);

   730 		if (ret_val) {

   731 			e_dbg("EEPROM Read Error\n");

   732 			return -E1000_ERR_EEPROM;

   733 		}

   734 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   735 			hw->fc = E1000_FC_NONE;

   736 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   737 			 EEPROM_WORD0F_ASM_DIR)

   738 			hw->fc = E1000_FC_TX_PAUSE;

   739 		else

   740 			hw->fc = E1000_FC_FULL;

   741 	}

   742 

   743 	/* We want to save off the original Flow Control configuration just

   744 	 * in case we get disconnected and then reconnected into a different

   745 	 * hub or switch with different Flow Control capabilities.

   746 	 */

   747 	if (hw->mac_type == e1000_82542_rev2_0)

   748 		hw->fc &= (~E1000_FC_TX_PAUSE);

   749 

   750 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   751 		hw->fc &= (~E1000_FC_RX_PAUSE);

   752 

   753 	hw->original_fc = hw->fc;

   754 

   755 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);

   756 

   757 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial

   758 	 * polarity value for the SW controlled pins, and setup the

   759 	 * Extended Device Control reg with that info.

   760 	 * This is needed because one of the SW controlled pins is used for

   761 	 * signal detection.  So this should be done before e1000_setup_pcs_link()

   762 	 * or e1000_phy_setup() is called.

   763 	 */

   764 	if (hw->mac_type == e1000_82543) {

   765 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   766 					    1, &eeprom_data);

   767 		if (ret_val) {

   768 			e_dbg("EEPROM Read Error\n");

   769 			return -E1000_ERR_EEPROM;

   770 		}

   771 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   772 			    SWDPIO__EXT_SHIFT);

   773 		ew32(CTRL_EXT, ctrl_ext);

   774 	}

   775 

   776 	/* Call the necessary subroutine to configure the link. */

   777 	ret_val = (hw->media_type == e1000_media_type_copper) ?

   778 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);

   779 

   780 	/* Initialize the flow control address, type, and PAUSE timer

   781 	 * registers to their default values.  This is done even if flow

   782 	 * control is disabled, because it does not hurt anything to

   783 	 * initialize these registers.

   784 	 */

   785 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   786 

   787 	ew32(FCT, FLOW_CONTROL_TYPE);

   788 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   789 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   790 

   791 	ew32(FCTTV, hw->fc_pause_time);

   792 

   793 	/* Set the flow control receive threshold registers.  Normally,

   794 	 * these registers will be set to a default threshold that may be

   795 	 * adjusted later by the driver's runtime code.  However, if the

   796 	 * ability to transmit pause frames in not enabled, then these

   797 	 * registers will be set to 0.

   798 	 */

   799 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {

   800 		ew32(FCRTL, 0);

   801 		ew32(FCRTH, 0);

   802 	} else {

   803 		/* We need to set up the Receive Threshold high and low water

   804 		 * marks as well as (optionally) enabling the transmission of

   805 		 * XON frames.

   806 		 */

   807 		if (hw->fc_send_xon) {

   808 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   809 			ew32(FCRTH, hw->fc_high_water);

   810 		} else {

   811 			ew32(FCRTL, hw->fc_low_water);

   812 			ew32(FCRTH, hw->fc_high_water);

   813 		}

   814 	}

   815 	return ret_val;

   816 }

   817 

   818 /**

   819  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link

   820  * @hw: Struct containing variables accessed by shared code

   821  *

   822  * Manipulates Physical Coding Sublayer functions in order to configure

   823  * link. Assumes the hardware has been previously reset and the transmitter

   824  * and receiver are not enabled.

   825  */

   826 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   827 {

   828 	u32 ctrl;

   829 	u32 status;

   830 	u32 txcw = 0;

   831 	u32 i;

   832 	u32 signal = 0;

   833 	s32 ret_val;

   834 

   835 	/* On adapters with a MAC newer than 82544, SWDP 1 will be

   836 	 * set when the optics detect a signal. On older adapters, it will be

   837 	 * cleared when there is a signal.  This applies to fiber media only.

   838 	 * If we're on serdes media, adjust the output amplitude to value

   839 	 * set in the EEPROM.

   840 	 */

   841 	ctrl = er32(CTRL);

   842 	if (hw->media_type == e1000_media_type_fiber)

   843 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   844 

   845 	ret_val = e1000_adjust_serdes_amplitude(hw);

   846 	if (ret_val)

   847 		return ret_val;

   848 

   849 	/* Take the link out of reset */

   850 	ctrl &= ~(E1000_CTRL_LRST);

   851 

   852 	/* Adjust VCO speed to improve BER performance */

   853 	ret_val = e1000_set_vco_speed(hw);

   854 	if (ret_val)

   855 		return ret_val;

   856 

   857 	e1000_config_collision_dist(hw);

   858 

   859 	/* Check for a software override of the flow control settings, and setup

   860 	 * the device accordingly.  If auto-negotiation is enabled, then

   861 	 * software will have to set the "PAUSE" bits to the correct value in

   862 	 * the Tranmsit Config Word Register (TXCW) and re-start

   863 	 * auto-negotiation.  However, if auto-negotiation is disabled, then

   864 	 * software will have to manually configure the two flow control enable

   865 	 * bits in the CTRL register.

   866 	 *

   867 	 * The possible values of the "fc" parameter are:

   868 	 *  0:  Flow control is completely disabled

   869 	 *  1:  Rx flow control is enabled (we can receive pause frames, but

   870 	 *      not send pause frames).

   871 	 *  2:  Tx flow control is enabled (we can send pause frames but we do

   872 	 *      not support receiving pause frames).

   873 	 *  3:  Both Rx and TX flow control (symmetric) are enabled.

   874 	 */

   875 	switch (hw->fc) {

   876 	case E1000_FC_NONE:

   877 		/* Flow ctrl is completely disabled by a software over-ride */

   878 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   879 		break;

   880 	case E1000_FC_RX_PAUSE:

   881 		/* Rx Flow control is enabled and Tx Flow control is disabled by

   882 		 * a software over-ride. Since there really isn't a way to

   883 		 * advertise that we are capable of Rx Pause ONLY, we will

   884 		 * advertise that we support both symmetric and asymmetric Rx

   885 		 * PAUSE. Later, we will disable the adapter's ability to send

   886 		 * PAUSE frames.

   887 		 */

   888 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   889 		break;

   890 	case E1000_FC_TX_PAUSE:

   891 		/* Tx Flow control is enabled, and Rx Flow control is disabled,

   892 		 * by a software over-ride.

   893 		 */

   894 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   895 		break;

   896 	case E1000_FC_FULL:

   897 		/* Flow control (both Rx and Tx) is enabled by a software

   898 		 * over-ride.

   899 		 */

   900 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   901 		break;

   902 	default:

   903 		e_dbg("Flow control param set incorrectly\n");

   904 		return -E1000_ERR_CONFIG;

   905 		break;

   906 	}

   907 

   908 	/* Since auto-negotiation is enabled, take the link out of reset (the

   909 	 * link will be in reset, because we previously reset the chip). This

   910 	 * will restart auto-negotiation.  If auto-negotiation is successful

   911 	 * then the link-up status bit will be set and the flow control enable

   912 	 * bits (RFCE and TFCE) will be set according to their negotiated value.

   913 	 */

   914 	e_dbg("Auto-negotiation enabled\n");

   915 

   916 	ew32(TXCW, txcw);

   917 	ew32(CTRL, ctrl);

   918 	E1000_WRITE_FLUSH();

   919 

   920 	hw->txcw = txcw;

   921 	msleep(1);

   922 

   923 	/* If we have a signal (the cable is plugged in) then poll for a

   924 	 * "Link-Up" indication in the Device Status Register.  Time-out if a

   925 	 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should

   926 	 * complete in less than 500 milliseconds even if the other end is doing

   927 	 * it in SW). For internal serdes, we just assume a signal is present,

   928 	 * then poll.

   929 	 */

   930 	if (hw->media_type == e1000_media_type_internal_serdes ||

   931 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   932 		e_dbg("Looking for Link\n");

   933 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   934 			msleep(10);

   935 			status = er32(STATUS);

   936 			if (status & E1000_STATUS_LU)

   937 				break;

   938 		}

   939 		if (i == (LINK_UP_TIMEOUT / 10)) {

   940 			e_dbg("Never got a valid link from auto-neg!!!\n");

   941 			hw->autoneg_failed = 1;

   942 			/* AutoNeg failed to achieve a link, so we'll call

   943 			 * e1000_check_for_link. This routine will force the

   944 			 * link up if we detect a signal. This will allow us to

   945 			 * communicate with non-autonegotiating link partners.

   946 			 */

   947 			ret_val = e1000_check_for_link(hw);

   948 			if (ret_val) {

   949 				e_dbg("Error while checking for link\n");

   950 				return ret_val;

   951 			}

   952 			hw->autoneg_failed = 0;

   953 		} else {

   954 			hw->autoneg_failed = 0;

   955 			e_dbg("Valid Link Found\n");

   956 		}

   957 	} else {

   958 		e_dbg("No Signal Detected\n");

   959 	}

   960 	return E1000_SUCCESS;

   961 }

   962 

   963 /**

   964  * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.

   965  * @hw: Struct containing variables accessed by shared code

   966  *

   967  * Commits changes to PHY configuration by calling e1000_phy_reset().

   968  */

   969 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)

   970 {

   971 	s32 ret_val;

   972 

   973 	/* SW reset the PHY so all changes take effect */

   974 	ret_val = e1000_phy_reset(hw);

   975 	if (ret_val) {

   976 		e_dbg("Error Resetting the PHY\n");

   977 		return ret_val;

   978 	}

   979 

   980 	return E1000_SUCCESS;

   981 }

   982 

   983 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)

   984 {

   985 	s32 ret_val;

   986 	u32 ctrl_aux;

   987 

   988 	switch (hw->phy_type) {

   989 	case e1000_phy_8211:

   990 		ret_val = e1000_copper_link_rtl_setup(hw);

   991 		if (ret_val) {

   992 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

   993 			return ret_val;

   994 		}

   995 		break;

   996 	case e1000_phy_8201:

   997 		/* Set RMII mode */

   998 		ctrl_aux = er32(CTL_AUX);

   999 		ctrl_aux |= E1000_CTL_AUX_RMII;

  1000 		ew32(CTL_AUX, ctrl_aux);

  1001 		E1000_WRITE_FLUSH();

  1002 

  1003 		/* Disable the J/K bits required for receive */

  1004 		ctrl_aux = er32(CTL_AUX);

  1005 		ctrl_aux |= 0x4;

  1006 		ctrl_aux &= ~0x2;

  1007 		ew32(CTL_AUX, ctrl_aux);

  1008 		E1000_WRITE_FLUSH();

  1009 		ret_val = e1000_copper_link_rtl_setup(hw);

  1010 

  1011 		if (ret_val) {

  1012 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

  1013 			return ret_val;

  1014 		}

  1015 		break;

  1016 	default:

  1017 		e_dbg("Error Resetting the PHY\n");

  1018 		return E1000_ERR_PHY_TYPE;

  1019 	}

  1020 

  1021 	return E1000_SUCCESS;

  1022 }

  1023 

  1024 /**

  1025  * e1000_copper_link_preconfig - early configuration for copper

  1026  * @hw: Struct containing variables accessed by shared code

  1027  *

  1028  * Make sure we have a valid PHY and change PHY mode before link setup.

  1029  */

  1030 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)

  1031 {

  1032 	u32 ctrl;

  1033 	s32 ret_val;

  1034 	u16 phy_data;

  1035 

  1036 	ctrl = er32(CTRL);

  1037 	/* With 82543, we need to force speed and duplex on the MAC equal to

  1038 	 * what the PHY speed and duplex configuration is. In addition, we need

  1039 	 * to perform a hardware reset on the PHY to take it out of reset.

  1040 	 */

  1041 	if (hw->mac_type > e1000_82543) {

  1042 		ctrl |= E1000_CTRL_SLU;

  1043 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1044 		ew32(CTRL, ctrl);

  1045 	} else {

  1046 		ctrl |=

  1047 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

  1048 		ew32(CTRL, ctrl);

  1049 		ret_val = e1000_phy_hw_reset(hw);

  1050 		if (ret_val)

  1051 			return ret_val;

  1052 	}

  1053 

  1054 	/* Make sure we have a valid PHY */

  1055 	ret_val = e1000_detect_gig_phy(hw);

  1056 	if (ret_val) {

  1057 		e_dbg("Error, did not detect valid phy.\n");

  1058 		return ret_val;

  1059 	}

  1060 	e_dbg("Phy ID = %x\n", hw->phy_id);

  1061 

  1062 	/* Set PHY to class A mode (if necessary) */

  1063 	ret_val = e1000_set_phy_mode(hw);

  1064 	if (ret_val)

  1065 		return ret_val;

  1066 

  1067 	if ((hw->mac_type == e1000_82545_rev_3) ||

  1068 	    (hw->mac_type == e1000_82546_rev_3)) {

  1069 		ret_val =

  1070 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1071 		phy_data |= 0x00000008;

  1072 		ret_val =

  1073 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1074 	}

  1075 

  1076 	if (hw->mac_type <= e1000_82543 ||

  1077 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1078 	    hw->mac_type == e1000_82541_rev_2

  1079 	    || hw->mac_type == e1000_82547_rev_2)

  1080 		hw->phy_reset_disable = false;

  1081 

  1082 	return E1000_SUCCESS;

  1083 }

  1084 

  1085 /**

  1086  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.

  1087  * @hw: Struct containing variables accessed by shared code

  1088  */

  1089 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1090 {

  1091 	u32 led_ctrl;

  1092 	s32 ret_val;

  1093 	u16 phy_data;

  1094 

  1095 	if (hw->phy_reset_disable)

  1096 		return E1000_SUCCESS;

  1097 

  1098 	ret_val = e1000_phy_reset(hw);

  1099 	if (ret_val) {

  1100 		e_dbg("Error Resetting the PHY\n");

  1101 		return ret_val;

  1102 	}

  1103 

  1104 	/* Wait 15ms for MAC to configure PHY from eeprom settings */

  1105 	msleep(15);

  1106 	/* Configure activity LED after PHY reset */

  1107 	led_ctrl = er32(LEDCTL);

  1108 	led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1109 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1110 	ew32(LEDCTL, led_ctrl);

  1111 

  1112 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */

  1113 	if (hw->phy_type == e1000_phy_igp) {

  1114 		/* disable lplu d3 during driver init */

  1115 		ret_val = e1000_set_d3_lplu_state(hw, false);

  1116 		if (ret_val) {

  1117 			e_dbg("Error Disabling LPLU D3\n");

  1118 			return ret_val;

  1119 		}

  1120 	}

  1121 

  1122 	/* Configure mdi-mdix settings */

  1123 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

  1124 	if (ret_val)

  1125 		return ret_val;

  1126 

  1127 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

  1128 		hw->dsp_config_state = e1000_dsp_config_disabled;

  1129 		/* Force MDI for earlier revs of the IGP PHY */

  1130 		phy_data &=

  1131 		    ~(IGP01E1000_PSCR_AUTO_MDIX |

  1132 		      IGP01E1000_PSCR_FORCE_MDI_MDIX);

  1133 		hw->mdix = 1;

  1134 

  1135 	} else {

  1136 		hw->dsp_config_state = e1000_dsp_config_enabled;