1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *****************************************************************************/

    29 

    30 /**

    31    \file

    32    EtherCAT driver for RTL8139-compatible NICs.

    33 */

    34 

    35 /*****************************************************************************/

    36 

    37 /*

    38   Former documentation:

    39 

    40 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41 

    42 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43 	Copyright 2000-2002 Jeff Garzik

    44 

    45 	Much code comes from Donald Becker's rtl8139.c driver,

    46 	versions 1.13 and older.  This driver was originally based

    47 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48 

    49 	-----<snip>-----

    50 

    51         	Written 1997-2001 by Donald Becker.

    52 		This software may be used and distributed according to the

    53 		terms of the GNU General Public License (GPL), incorporated

    54 		herein by reference.  Drivers based on or derived from this

    55 		code fall under the GPL and must retain the authorship,

    56 		copyright and license notice.  This file is not a complete

    57 		program and may only be used when the entire operating

    58 		system is licensed under the GPL.

    59 

    60 		This driver is for boards based on the RTL8129 and RTL8139

    61 		PCI ethernet chips.

    62 

    63 		The author may be reached as becker@scyld.com, or C/O Scyld

    64 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65 		MD 21403

    66 

    67 		Support and updates available at

    68 		http://www.scyld.com/network/rtl8139.html

    69 

    70 		Twister-tuning table provided by Kinston

    71 		<shangh@realtek.com.tw>.

    72 

    73 	-----<snip>-----

    74 

    75 	This software may be used and distributed according to the terms

    76 	of the GNU General Public License, incorporated herein by reference.

    77 

    78 	Contributors:

    79 

    80 		Donald Becker - he wrote the original driver, kudos to him!

    81 		(but please don't e-mail him for support, this isn't his driver)

    82 

    83 		Tigran Aivazian - bug fixes, skbuff free cleanup

    84 

    85 		Martin Mares - suggestions for PCI cleanup

    86 

    87 		David S. Miller - PCI DMA and softnet updates

    88 

    89 		Ernst Gill - fixes ported from BSD driver

    90 

    91 		Daniel Kobras - identified specific locations of

    92 			posted MMIO write bugginess

    93 

    94 		Gerard Sharp - bug fix, testing and feedback

    95 

    96 		David Ford - Rx ring wrap fix

    97 

    98 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    99 		to find and fix a crucial bug on older chipsets.

   100 

   101 		Donald Becker/Chris Butterworth/Marcus Westergren -

   102 		Noticed various Rx packet size-related buglets.

   103 

   104 		Santiago Garcia Mantinan - testing and feedback

   105 

   106 		Jens David - 2.2.x kernel backports

   107 

   108 		Martin Dennett - incredibly helpful insight on undocumented

   109 		features of the 8139 chips

   110 

   111 		Jean-Jacques Michel - bug fix

   112 

   113 		Tobias Ringström - Rx interrupt status checking suggestion

   114 

   115 		Andrew Morton - Clear blocked signals, avoid

   116 		buffer overrun setting current->comm.

   117 

   118 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   119 

   120 		Robert Kuebel - Save kernel thread from dying on any signal.

   121 

   122 	Submitting bug reports:

   123 

   124 		"rtl8139-diag -mmmaaavvveefN" output

   125 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   126 

   127 */

   128 

   129 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

   130 

   131 #define DRV_NAME	"ec_8139too"

   132 #define DRV_VERSION	"0.9.28"

   133 

   134 

   135 #include <linux/module.h>

   136 #include <linux/kernel.h>

   137 #include <linux/compiler.h>

   138 #include <linux/pci.h>

   139 #include <linux/init.h>

   140 #include <linux/interrupt.h>

   141 #include <linux/netdevice.h>

   142 #include <linux/etherdevice.h>

   143 #include <linux/rtnetlink.h>

   144 #include <linux/delay.h>

   145 #include <linux/ethtool.h>

   146 #include <linux/mii.h>

   147 #include <linux/completion.h>

   148 #include <linux/crc32.h>

   149 #include <linux/io.h>

   150 #include <linux/uaccess.h>

   151 #include <linux/gfp.h>

   152 #include <asm/irq.h>

   153 

   154 #include "../globals.h"

   155 #include "ecdev.h"

   156 

   157 #define RTL8139_DRIVER_NAME DRV_NAME \

   158                             " EtherCAT-capable Fast Ethernet driver " \

   159                             DRV_VERSION ", master " EC_MASTER_VERSION

   160 

   161 #define PFX DRV_NAME ": "

   162 

   163 /* Default Message level */

   164 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   165                                  NETIF_MSG_PROBE  | \

   166                                  NETIF_MSG_LINK)

   167 

   168 

   169 /* define to 1, 2 or 3 to enable copious debugging info */

   170 #define RTL8139_DEBUG 0

   171 

   172 /* define to 1 to disable lightweight runtime debugging checks */

   173 #undef RTL8139_NDEBUG

   174 

   175 

   176 #ifdef RTL8139_NDEBUG

   177 #  define assert(expr) do {} while (0)

   178 #else

   179 #  define assert(expr) \

   180         if (unlikely(!(expr))) {				\

   181 		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   182 		       #expr, __FILE__, __func__, __LINE__);	\

   183         }

   184 #endif

   185 

   186 

   187 /* A few user-configurable values. */

   188 /* media options */

   189 #define MAX_UNITS 8

   190 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   191 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   192 

   193 /* Whether to use MMIO or PIO. Default to MMIO. */

   194 #ifdef CONFIG_8139TOO_PIO

   195 static int use_io = 1;

   196 #else

   197 static int use_io = 0;

   198 #endif

   199 

   200 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   201    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   202 static int multicast_filter_limit = 32;

   203 

   204 /* bitmapped message enable number */

   205 static int debug = -1;

   206 

   207 /*

   208  * Receive ring size

   209  * Warning: 64K ring has hardware issues and may lock up.

   210  */

   211 #if defined(CONFIG_SH_DREAMCAST)

   212 #define RX_BUF_IDX 0	/* 8K ring */

   213 #else

   214 #define RX_BUF_IDX	2	/* 32K ring */

   215 #endif

   216 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   217 #define RX_BUF_PAD	16

   218 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   219 

   220 #if RX_BUF_LEN == 65536

   221 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   222 #else

   223 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   224 #endif

   225 

   226 /* Number of Tx descriptor registers. */

   227 #define NUM_TX_DESC	4

   228 

   229 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   230 #define MAX_ETH_FRAME_SIZE	1536

   231 

   232 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   233 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   234 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   235 

   236 /* PCI Tuning Parameters

   237    Threshold is bytes transferred to chip before transmission starts. */

   238 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   239 

   240 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   241 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   242 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   243 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   244 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   245 

   246 /* Operational parameters that usually are not changed. */

   247 /* Time in jiffies before concluding the transmitter is hung. */

   248 #define TX_TIMEOUT  (6*HZ)

   249 

   250 

   251 enum {

   252 	HAS_MII_XCVR = 0x010000,

   253 	HAS_CHIP_XCVR = 0x020000,

   254 	HAS_LNK_CHNG = 0x040000,

   255 };

   256 

   257 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   258 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   259 #define RTL_MIN_IO_SIZE 0x80

   260 #define RTL8139B_IO_SIZE 256

   261 

   262 #define RTL8129_CAPS	HAS_MII_XCVR

   263 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   264 

   265 typedef enum {

   266 	RTL8139 = 0,

   267 	RTL8129,

   268 } board_t;

   269 

   270 

   271 /* indexed by board_t, above */

   272 static const struct {

   273 	const char *name;

   274 	u32 hw_flags;

   275 } board_info[] __devinitdata = {

   276 	{ "RealTek RTL8139", RTL8139_CAPS },

   277 	{ "RealTek RTL8129", RTL8129_CAPS },

   278 };

   279 

   280 

   281 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   282 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 

   302 #ifdef CONFIG_SH_SECUREEDGE5410

   303 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   304 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305 #endif

   306 #ifdef CONFIG_8139TOO_8129

   307 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   308 #endif

   309 

   310 	/* some crazy cards report invalid vendor ids like

   311 	 * 0x0001 here.  The other ids are valid and constant,

   312 	 * so we simply don't match on the main vendor id.

   313 	 */

   314 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   315 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   316 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   317 

   318 	{0,}

   319 };

   320 

   321 /* prevent driver from being loaded automatically */

   322 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   323 

   324 static struct {

   325 	const char str[ETH_GSTRING_LEN];

   326 } ethtool_stats_keys[] = {

   327 	{ "early_rx" },

   328 	{ "tx_buf_mapped" },

   329 	{ "tx_timeouts" },

   330 	{ "rx_lost_in_ring" },

   331 };

   332 

   333 /* The rest of these values should never change. */

   334 

   335 /* Symbolic offsets to registers. */

   336 enum RTL8139_registers {

   337 	MAC0		= 0,	 /* Ethernet hardware address. */

   338 	MAR0		= 8,	 /* Multicast filter. */

   339 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   340 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   341 	RxBuf		= 0x30,

   342 	ChipCmd		= 0x37,

   343 	RxBufPtr	= 0x38,

   344 	RxBufAddr	= 0x3A,

   345 	IntrMask	= 0x3C,

   346 	IntrStatus	= 0x3E,

   347 	TxConfig	= 0x40,

   348 	RxConfig	= 0x44,

   349 	Timer		= 0x48,	 /* A general-purpose counter. */

   350 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   351 	Cfg9346		= 0x50,

   352 	Config0		= 0x51,

   353 	Config1		= 0x52,

   354 	TimerInt	= 0x54,

   355 	MediaStatus	= 0x58,

   356 	Config3		= 0x59,

   357 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   358 	HltClk		= 0x5B,

   359 	MultiIntr	= 0x5C,

   360 	TxSummary	= 0x60,

   361 	BasicModeCtrl	= 0x62,

   362 	BasicModeStatus	= 0x64,

   363 	NWayAdvert	= 0x66,

   364 	NWayLPAR	= 0x68,

   365 	NWayExpansion	= 0x6A,

   366 	/* Undocumented registers, but required for proper operation. */

   367 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   368 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   369 	PARA78		= 0x78,

   370 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   371 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   372 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   373 };

   374 

   375 enum ClearBitMasks {

   376 	MultiIntrClear	= 0xF000,

   377 	ChipCmdClear	= 0xE2,

   378 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   379 };

   380 

   381 enum ChipCmdBits {

   382 	CmdReset	= 0x10,

   383 	CmdRxEnb	= 0x08,

   384 	CmdTxEnb	= 0x04,

   385 	RxBufEmpty	= 0x01,

   386 };

   387 

   388 /* Interrupt register bits, using my own meaningful names. */

   389 enum IntrStatusBits {

   390 	PCIErr		= 0x8000,

   391 	PCSTimeout	= 0x4000,

   392 	RxFIFOOver	= 0x40,

   393 	RxUnderrun	= 0x20,

   394 	RxOverflow	= 0x10,

   395 	TxErr		= 0x08,

   396 	TxOK		= 0x04,

   397 	RxErr		= 0x02,

   398 	RxOK		= 0x01,

   399 

   400 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   401 };

   402 

   403 enum TxStatusBits {

   404 	TxHostOwns	= 0x2000,

   405 	TxUnderrun	= 0x4000,

   406 	TxStatOK	= 0x8000,

   407 	TxOutOfWindow	= 0x20000000,

   408 	TxAborted	= 0x40000000,

   409 	TxCarrierLost	= 0x80000000,

   410 };

   411 enum RxStatusBits {

   412 	RxMulticast	= 0x8000,

   413 	RxPhysical	= 0x4000,

   414 	RxBroadcast	= 0x2000,

   415 	RxBadSymbol	= 0x0020,

   416 	RxRunt		= 0x0010,

   417 	RxTooLong	= 0x0008,

   418 	RxCRCErr	= 0x0004,

   419 	RxBadAlign	= 0x0002,

   420 	RxStatusOK	= 0x0001,

   421 };

   422 

   423 /* Bits in RxConfig. */

   424 enum rx_mode_bits {

   425 	AcceptErr	= 0x20,

   426 	AcceptRunt	= 0x10,

   427 	AcceptBroadcast	= 0x08,

   428 	AcceptMulticast	= 0x04,

   429 	AcceptMyPhys	= 0x02,

   430 	AcceptAllPhys	= 0x01,

   431 };

   432 

   433 /* Bits in TxConfig. */

   434 enum tx_config_bits {

   435         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   436         TxIFGShift	= 24,

   437         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   438         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   439         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   440         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   441 

   442 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   443 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   444 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   445 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   446 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   447 

   448 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   449 };

   450 

   451 /* Bits in Config1 */

   452 enum Config1Bits {

   453 	Cfg1_PM_Enable	= 0x01,

   454 	Cfg1_VPD_Enable	= 0x02,

   455 	Cfg1_PIO	= 0x04,

   456 	Cfg1_MMIO	= 0x08,

   457 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   458 	Cfg1_Driver_Load = 0x20,

   459 	Cfg1_LED0	= 0x40,

   460 	Cfg1_LED1	= 0x80,

   461 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   462 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   463 };

   464 

   465 /* Bits in Config3 */

   466 enum Config3Bits {

   467 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   468 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   469 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   470 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   471 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   472 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   473 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   474 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   475 };

   476 

   477 /* Bits in Config4 */

   478 enum Config4Bits {

   479 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   480 };

   481 

   482 /* Bits in Config5 */

   483 enum Config5Bits {

   484 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   485 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   486 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   487 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   488 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   489 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   490 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   491 };

   492 

   493 enum RxConfigBits {

   494 	/* rx fifo threshold */

   495 	RxCfgFIFOShift	= 13,

   496 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   497 

   498 	/* Max DMA burst */

   499 	RxCfgDMAShift	= 8,

   500 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   501 

   502 	/* rx ring buffer length */

   503 	RxCfgRcv8K	= 0,

   504 	RxCfgRcv16K	= (1 << 11),

   505 	RxCfgRcv32K	= (1 << 12),

   506 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   507 

   508 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   509 	RxNoWrap	= (1 << 7),

   510 };

   511 

   512 /* Twister tuning parameters from RealTek.

   513    Completely undocumented, but required to tune bad links on some boards. */

   514 enum CSCRBits {

   515 	CSCR_LinkOKBit		= 0x0400,

   516 	CSCR_LinkChangeBit	= 0x0800,

   517 	CSCR_LinkStatusBits	= 0x0f000,

   518 	CSCR_LinkDownOffCmd	= 0x003c0,

   519 	CSCR_LinkDownCmd	= 0x0f3c0,

   520 };

   521 

   522 enum Cfg9346Bits {

   523 	Cfg9346_Lock	= 0x00,

   524 	Cfg9346_Unlock	= 0xC0,

   525 };

   526 

   527 typedef enum {

   528 	CH_8139	= 0,

   529 	CH_8139_K,

   530 	CH_8139A,

   531 	CH_8139A_G,

   532 	CH_8139B,

   533 	CH_8130,

   534 	CH_8139C,

   535 	CH_8100,

   536 	CH_8100B_8139D,

   537 	CH_8101,

   538 } chip_t;

   539 

   540 enum chip_flags {

   541 	HasHltClk	= (1 << 0),

   542 	HasLWake	= (1 << 1),

   543 };

   544 

   545 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   546 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   547 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   548 

   549 /* directly indexed by chip_t, above */

   550 static const struct {

   551 	const char *name;

   552 	u32 version; /* from RTL8139C/RTL8139D docs */

   553 	u32 flags;

   554 } rtl_chip_info[] = {

   555 	{ "RTL-8139",

   556 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   557 	  HasHltClk,

   558 	},

   559 

   560 	{ "RTL-8139 rev K",

   561 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   562 	  HasHltClk,

   563 	},

   564 

   565 	{ "RTL-8139A",

   566 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   567 	  HasHltClk, /* XXX undocumented? */

   568 	},

   569 

   570 	{ "RTL-8139A rev G",

   571 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   572 	  HasHltClk, /* XXX undocumented? */

   573 	},

   574 

   575 	{ "RTL-8139B",

   576 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   577 	  HasLWake,

   578 	},

   579 

   580 	{ "RTL-8130",

   581 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   582 	  HasLWake,

   583 	},

   584 

   585 	{ "RTL-8139C",

   586 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   587 	  HasLWake,

   588 	},

   589 

   590 	{ "RTL-8100",

   591 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   592  	  HasLWake,

   593  	},

   594 

   595 	{ "RTL-8100B/8139D",

   596 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   597 	  HasHltClk /* XXX undocumented? */

   598 	| HasLWake,

   599 	},

   600 

   601 	{ "RTL-8101",

   602 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   603 	  HasLWake,

   604 	},

   605 };

   606 

   607 struct rtl_extra_stats {

   608 	unsigned long early_rx;

   609 	unsigned long tx_buf_mapped;

   610 	unsigned long tx_timeouts;

   611 	unsigned long rx_lost_in_ring;

   612 };

   613 

   614 struct rtl8139_stats {

   615 	u64	packets;

   616 	u64	bytes;

   617 	struct u64_stats_sync	syncp;

   618 };

   619 

   620 struct rtl8139_private {

   621 	void __iomem		*mmio_addr;

   622 	int			drv_flags;

   623 	struct pci_dev		*pci_dev;

   624 	u32			msg_enable;

   625 	struct napi_struct	napi;

   626 	struct net_device	*dev;

   627 

   628 	unsigned char		*rx_ring;

   629 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   630 	struct rtl8139_stats	rx_stats;

   631 	dma_addr_t		rx_ring_dma;

   632 

   633 	unsigned int		tx_flag;

   634 	unsigned long		cur_tx;

   635 	unsigned long		dirty_tx;

   636 	struct rtl8139_stats	tx_stats;

   637 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   638 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   639 	dma_addr_t		tx_bufs_dma;

   640 

   641 	signed char		phys[4];	/* MII device addresses. */

   642 

   643 				/* Twister tune state. */

   644 	char			twistie, twist_row, twist_col;

   645 

   646 	unsigned int		watchdog_fired : 1;

   647 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   648 	unsigned int		have_thread : 1;

   649 

   650 	spinlock_t		lock;

   651 	spinlock_t		rx_lock;

   652 

   653 	chip_t			chipset;

   654 	u32			rx_config;

   655 	struct rtl_extra_stats	xstats;

   656 

   657 	struct delayed_work	thread;

   658 

   659 	struct mii_if_info	mii;

   660 	unsigned int		regs_len;

   661 	unsigned long		fifo_copy_timeout;

   662 

   663 	ec_device_t *ecdev;

   664 };

   665 

   666 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   667 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   668 MODULE_LICENSE("GPL");

   669 MODULE_VERSION(EC_MASTER_VERSION);

   670 

   671 module_param(use_io, int, 0);

   672 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   673 module_param(multicast_filter_limit, int, 0);

   674 module_param_array(media, int, NULL, 0);

   675 module_param_array(full_duplex, int, NULL, 0);

   676 module_param(debug, int, 0);

   677 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   678 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   679 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   680 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   681 

   682 void ec_poll(struct net_device *);

   683 

   684 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   685 static int rtl8139_open (struct net_device *dev);

   686 static int mdio_read (struct net_device *dev, int phy_id, int location);

   687 static void mdio_write (struct net_device *dev, int phy_id, int location,

   688 			int val);

   689 static void rtl8139_start_thread(struct rtl8139_private *tp);

   690 static void rtl8139_tx_timeout (struct net_device *dev);

   691 static void rtl8139_init_ring (struct net_device *dev);

   692 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,

   693 				       struct net_device *dev);

   694 #ifdef CONFIG_NET_POLL_CONTROLLER

   695 static void rtl8139_poll_controller(struct net_device *dev);

   696 #endif

   697 static int rtl8139_set_mac_address(struct net_device *dev, void *p);

   698 static int rtl8139_poll(struct napi_struct *napi, int budget);

   699 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   700 static int rtl8139_close (struct net_device *dev);

   701 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   702 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,

   703 						    struct rtnl_link_stats64

   704 						    *stats);

   705 static void rtl8139_set_rx_mode (struct net_device *dev);

   706 static void __set_rx_mode (struct net_device *dev);

   707 static void rtl8139_hw_start (struct net_device *dev);

   708 static void rtl8139_thread (struct work_struct *work);

   709 static void rtl8139_tx_timeout_task(struct work_struct *work);

   710 static const struct ethtool_ops rtl8139_ethtool_ops;

   711 

   712 /* write MMIO register, with flush */

   713 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   714 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   715 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   716 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   717 

   718 /* write MMIO register */

   719 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   720 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   721 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   722 

   723 /* read MMIO register */

   724 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   725 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   726 #define RTL_R32(reg)		ioread32 (ioaddr + (reg))

   727 

   728 

   729 static const u16 rtl8139_intr_mask =

   730 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   731 	TxErr | TxOK | RxErr | RxOK;

   732 

   733 static const u16 rtl8139_norx_intr_mask =

   734 	PCIErr | PCSTimeout | RxUnderrun |

   735 	TxErr | TxOK | RxErr ;

   736 

   737 #if RX_BUF_IDX == 0

   738 static const unsigned int rtl8139_rx_config =

   739 	RxCfgRcv8K | RxNoWrap |

   740 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   741 	(RX_DMA_BURST << RxCfgDMAShift);

   742 #elif RX_BUF_IDX == 1

   743 static const unsigned int rtl8139_rx_config =

   744 	RxCfgRcv16K | RxNoWrap |

   745 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   746 	(RX_DMA_BURST << RxCfgDMAShift);

   747 #elif RX_BUF_IDX == 2

   748 static const unsigned int rtl8139_rx_config =

   749 	RxCfgRcv32K | RxNoWrap |

   750 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   751 	(RX_DMA_BURST << RxCfgDMAShift);

   752 #elif RX_BUF_IDX == 3

   753 static const unsigned int rtl8139_rx_config =

   754 	RxCfgRcv64K |

   755 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   756 	(RX_DMA_BURST << RxCfgDMAShift);

   757 #else

   758 #error "Invalid configuration for 8139_RXBUF_IDX"

   759 #endif

   760 

   761 static const unsigned int rtl8139_tx_config =

   762 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   763 

   764 static void __rtl8139_cleanup_dev (struct net_device *dev)

   765 {

   766 	struct rtl8139_private *tp = netdev_priv(dev);

   767 	struct pci_dev *pdev;

   768 

   769 	assert (dev != NULL);

   770 	assert (tp->pci_dev != NULL);

   771 	pdev = tp->pci_dev;

   772 

   773 	if (tp->mmio_addr)

   774 		pci_iounmap (pdev, tp->mmio_addr);

   775 

   776 	/* it's ok to call this even if we have no regions to free */

   777 	pci_release_regions (pdev);

   778 

   779 	free_netdev(dev);

   780 	pci_set_drvdata (pdev, NULL);

   781 }

   782 

   783 

   784 static void rtl8139_chip_reset (void __iomem *ioaddr)

   785 {

   786 	int i;

   787 

   788 	/* Soft reset the chip. */

   789 	RTL_W8 (ChipCmd, CmdReset);

   790 

   791 	/* Check that the chip has finished the reset. */

   792 	for (i = 1000; i > 0; i--) {

   793 		barrier();

   794 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   795 			break;

   796 		udelay (10);

   797 	}

   798 }

   799 

   800 

   801 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)

   802 {

   803 	void __iomem *ioaddr;

   804 	struct net_device *dev;

   805 	struct rtl8139_private *tp;

   806 	u8 tmp8;

   807 	int rc, disable_dev_on_err = 0;

   808 	unsigned int i;

   809 	unsigned long pio_start, pio_end __attribute__ ((unused)), pio_flags,

   810                   pio_len;

   811 	unsigned long mmio_start __attribute__ ((unused)),

   812                   mmio_end __attribute__ ((unused)), mmio_flags, mmio_len;

   813 	u32 version;

   814 

   815 	assert (pdev != NULL);

   816 

   817 	/* dev and priv zeroed in alloc_etherdev */

   818 	dev = alloc_etherdev (sizeof (*tp));

   819 	if (dev == NULL)

   820 		return ERR_PTR(-ENOMEM);

   821 

   822 	SET_NETDEV_DEV(dev, &pdev->dev);

   823 

   824 	tp = netdev_priv(dev);

   825 	tp->pci_dev = pdev;

   826 

   827 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   828 	rc = pci_enable_device (pdev);

   829 	if (rc)

   830 		goto err_out;

   831 

   832 	pio_start = pci_resource_start (pdev, 0);

   833 	pio_end = pci_resource_end (pdev, 0);

   834 	pio_flags = pci_resource_flags (pdev, 0);

   835 	pio_len = pci_resource_len (pdev, 0);

   836 

   837 	mmio_start = pci_resource_start (pdev, 1);

   838 	mmio_end = pci_resource_end (pdev, 1);

   839 	mmio_flags = pci_resource_flags (pdev, 1);

   840 	mmio_len = pci_resource_len (pdev, 1);

   841 

   842 	/* set this immediately, we need to know before

   843 	 * we talk to the chip directly */

   844 	pr_debug("PIO region size == 0x%02lX\n", pio_len);

   845 	pr_debug("MMIO region size == 0x%02lX\n", mmio_len);

   846 

   847 retry:

   848 	if (use_io) {

   849 		/* make sure PCI base addr 0 is PIO */

   850 		if (!(pio_flags & IORESOURCE_IO)) {

   851 			dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   852 			rc = -ENODEV;

   853 			goto err_out;

   854 		}

   855 		/* check for weird/broken PCI region reporting */

   856 		if (pio_len < RTL_MIN_IO_SIZE) {

   857 			dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   858 			rc = -ENODEV;

   859 			goto err_out;

   860 		}

   861 	} else {

   862 		/* make sure PCI base addr 1 is MMIO */

   863 		if (!(mmio_flags & IORESOURCE_MEM)) {

   864 			dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   865 			rc = -ENODEV;

   866 			goto err_out;

   867 		}

   868 		if (mmio_len < RTL_MIN_IO_SIZE) {

   869 			dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   870 			rc = -ENODEV;

   871 			goto err_out;

   872 		}

   873 	}

   874 

   875 	rc = pci_request_regions (pdev, DRV_NAME);

   876 	if (rc)

   877 		goto err_out;

   878 	disable_dev_on_err = 1;

   879 

   880 	/* enable PCI bus-mastering */

   881 	pci_set_master (pdev);

   882 

   883 	if (use_io) {

   884 		ioaddr = pci_iomap(pdev, 0, 0);

   885 		if (!ioaddr) {

   886 			dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   887 			rc = -EIO;

   888 			goto err_out;

   889 		}

   890 		dev->base_addr = pio_start;

   891 		tp->regs_len = pio_len;

   892 	} else {

   893 		/* ioremap MMIO region */

   894 		ioaddr = pci_iomap(pdev, 1, 0);

   895 		if (ioaddr == NULL) {

   896 			dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");

   897 			pci_release_regions(pdev);

   898 			use_io = 1;

   899 			goto retry;

   900 		}

   901 		dev->base_addr = (long) ioaddr;

   902 		tp->regs_len = mmio_len;

   903 	}

   904 	tp->mmio_addr = ioaddr;

   905 

   906 	/* Bring old chips out of low-power mode. */

   907 	RTL_W8 (HltClk, 'R');

   908 

   909 	/* check for missing/broken hardware */

   910 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   911 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   912 		rc = -EIO;

   913 		goto err_out;

   914 	}

   915 

   916 	/* identify chip attached to board */

   917 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   918 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   919 		if (version == rtl_chip_info[i].version) {

   920 			tp->chipset = i;

   921 			goto match;

   922 		}

   923 

   924 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   925 	i = 0;

   926 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");

   927 	dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));

   928 	tp->chipset = 0;

   929 

   930 match:

   931 	pr_debug("chipset id (%d) == index %d, '%s'\n",

   932 		 version, i, rtl_chip_info[i].name);

   933 

   934 	if (tp->chipset >= CH_8139B) {

   935 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   936 		pr_debug("PCI PM wakeup\n");

   937 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   938 		    (tmp8 & LWAKE))

   939 			new_tmp8 &= ~LWAKE;

   940 		new_tmp8 |= Cfg1_PM_Enable;

   941 		if (new_tmp8 != tmp8) {

   942 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   943 			RTL_W8 (Config1, tmp8);

   944 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   945 		}

   946 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   947 			tmp8 = RTL_R8 (Config4);

   948 			if (tmp8 & LWPTN) {

   949 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   950 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   951 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   952 			}

   953 		}

   954 	} else {

   955 		pr_debug("Old chip wakeup\n");

   956 		tmp8 = RTL_R8 (Config1);

   957 		tmp8 &= ~(SLEEP | PWRDN);

   958 		RTL_W8 (Config1, tmp8);

   959 	}

   960 

   961 	rtl8139_chip_reset (ioaddr);

   962 

   963 	return dev;

   964 

   965 err_out:

   966 	__rtl8139_cleanup_dev (dev);

   967 	if (disable_dev_on_err)

   968 		pci_disable_device (pdev);

   969 	return ERR_PTR(rc);

   970 }

   971 

   972 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)

   973 {

   974 	struct rtl8139_private *tp = netdev_priv(dev);

   975 	unsigned long flags;

   976 	netdev_features_t changed = features ^ dev->features;

   977 	void __iomem *ioaddr = tp->mmio_addr;

   978 

   979 	if (!(changed & (NETIF_F_RXALL)))

   980 		return 0;

   981 

   982 	spin_lock_irqsave(&tp->lock, flags);

   983 

   984 	if (changed & NETIF_F_RXALL) {

   985 		int rx_mode = tp->rx_config;

   986 		if (features & NETIF_F_RXALL)

   987 			rx_mode |= (AcceptErr | AcceptRunt);

   988 		else

   989 			rx_mode &= ~(AcceptErr | AcceptRunt);

   990 		tp->rx_config = rtl8139_rx_config | rx_mode;

   991 		RTL_W32_F(RxConfig, tp->rx_config);

   992 	}

   993 

   994 	spin_unlock_irqrestore(&tp->lock, flags);

   995 

   996 	return 0;

   997 }

   998 

   999 static const struct net_device_ops rtl8139_netdev_ops = {

  1000 	.ndo_open		= rtl8139_open,

  1001 	.ndo_stop		= rtl8139_close,

  1002 	.ndo_get_stats64	= rtl8139_get_stats64,

  1003 	.ndo_change_mtu		= eth_change_mtu,

  1004 	.ndo_validate_addr	= eth_validate_addr,

  1005 	.ndo_set_mac_address 	= rtl8139_set_mac_address,

  1006 	.ndo_start_xmit		= rtl8139_start_xmit,

  1007 	.ndo_set_rx_mode	= rtl8139_set_rx_mode,

  1008 	.ndo_do_ioctl		= netdev_ioctl,

  1009 	.ndo_tx_timeout		= rtl8139_tx_timeout,

  1010 #ifdef CONFIG_NET_POLL_CONTROLLER

  1011 	.ndo_poll_controller	= rtl8139_poll_controller,

  1012 #endif

  1013 	.ndo_set_features	= rtl8139_set_features,

  1014 };

  1015 

  1016 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

  1017 				       const struct pci_device_id *ent)

  1018 {

  1019 	struct net_device *dev = NULL;

  1020 	struct rtl8139_private *tp;

  1021 	int i, addr_len, option;

  1022 	void __iomem *ioaddr;

  1023 	static int board_idx = -1;

  1024 

  1025 	assert (pdev != NULL);

  1026 	assert (ent != NULL);

  1027 

  1028 	board_idx++;

  1029 

  1030 	/* when we're built into the kernel, the driver version message

  1031 	 * is only printed if at least one 8139 board has been found

  1032 	 */

  1033 #ifndef MODULE

  1034 	{

  1035 		static int printed_version;

  1036 		if (!printed_version++)

  1037 			pr_info(RTL8139_DRIVER_NAME "\n");

  1038 	}

  1039 #endif

  1040 

  1041 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1042 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

  1043 		dev_info(&pdev->dev,

  1044 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",

  1045 		       	   pdev->vendor, pdev->device, pdev->revision);

  1046 		return -ENODEV;

  1047 	}

  1048 

  1049 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1050 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1051 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1052 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1053 		pr_info("OQO Model 2 detected. Forcing PIO\n");

  1054 		use_io = 1;

  1055 	}

  1056 

  1057 	dev = rtl8139_init_board (pdev);

  1058 	if (IS_ERR(dev))

  1059 		return PTR_ERR(dev);

  1060 

  1061 	assert (dev != NULL);

  1062 	tp = netdev_priv(dev);

  1063 	tp->dev = dev;

  1064 

  1065 	ioaddr = tp->mmio_addr;

  1066 	assert (ioaddr != NULL);

  1067 

  1068 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1069 	for (i = 0; i < 3; i++)

  1070 		((__le16 *) (dev->dev_addr))[i] =

  1071 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1072 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1073 

  1074 	/* The Rtl8139-specific entries in the device structure. */

  1075 	dev->netdev_ops = &rtl8139_netdev_ops;

  1076 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1077 	dev->watchdog_timeo = TX_TIMEOUT;

  1078 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1079 

  1080 	/* note: the hardware is not capable of sg/csum/highdma, however

  1081 	 * through the use of skb_copy_and_csum_dev we enable these

  1082 	 * features

  1083 	 */

  1084 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1085 	dev->vlan_features = dev->features;

  1086 

  1087 	dev->hw_features |= NETIF_F_RXALL;

  1088 	dev->hw_features |= NETIF_F_RXFCS;

  1089 

  1090 	dev->irq = pdev->irq;

  1091 

  1092 	/* tp zeroed and aligned in alloc_etherdev */

  1093 	tp = netdev_priv(dev);

  1094 

  1095 	/* note: tp->chipset set in rtl8139_init_board */

  1096 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1097 	tp->mmio_addr = ioaddr;

  1098 	tp->msg_enable =

  1099 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1100 	spin_lock_init (&tp->lock);

  1101 	spin_lock_init (&tp->rx_lock);

  1102 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1103 	tp->mii.dev = dev;

  1104 	tp->mii.mdio_read = mdio_read;

  1105 	tp->mii.mdio_write = mdio_write;

  1106 	tp->mii.phy_id_mask = 0x3f;

  1107 	tp->mii.reg_num_mask = 0x1f;

  1108 

  1109 	/* dev is fully set up and ready to use now */

  1110 	// offer device to EtherCAT master module

  1111 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1112 

  1113 	if (!tp->ecdev) {

  1114 		pr_debug("about to register device named %s (%p)...\n", dev->name, dev);

  1115 		i = register_netdev (dev);

  1116 		if (i) goto err_out;

  1117 	}

  1118 

  1119 	pci_set_drvdata (pdev, dev);

  1120 

  1121 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",

  1122 		dev->name,

  1123 		board_info[ent->driver_data].name,

  1124 		dev->base_addr,

  1125 		dev->dev_addr,

  1126 		dev->irq);

  1127 

  1128 	pr_debug("%s:  Identified 8139 chip type '%s'\n",

  1129 		dev->name, rtl_chip_info[tp->chipset].name);

  1130 

  1131 	/* Find the connected MII xcvrs.

  1132 	   Doing this in open() would allow detecting external xcvrs later, but

  1133 	   takes too much time. */

  1134 #ifdef CONFIG_8139TOO_8129

  1135 	if (tp->drv_flags & HAS_MII_XCVR) {

  1136 		int phy, phy_idx = 0;