devices/8139too-3.10-ethercat.c
changeset 2589 2b9c78543663
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     1 /******************************************************************************
       
     2  *
       
     3  *  $Id$
       
     4  *
       
     5  *  Copyright (C) 2006-2014  Florian Pose, Ingenieurgemeinschaft IgH
       
     6  *
       
     7  *  This file is part of the IgH EtherCAT Master.
       
     8  *
       
     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or
       
    10  *  modify it under the terms of the GNU General Public License version 2, as
       
    11  *  published by the Free Software Foundation.
       
    12  *
       
    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,
       
    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
       
    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
       
    16  *  Public License for more details.
       
    17  *
       
    18  *  You should have received a copy of the GNU General Public License along
       
    19  *  with the IgH EtherCAT Master; if not, write to the Free Software
       
    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
       
    21  *
       
    22  *  ---
       
    23  *
       
    24  *  The license mentioned above concerns the source code only. Using the
       
    25  *  EtherCAT technology and brand is only permitted in compliance with the
       
    26  *  industrial property and similar rights of Beckhoff Automation GmbH.
       
    27  *
       
    28  *  vim: noexpandtab
       
    29  *
       
    30  *****************************************************************************/
       
    31 
       
    32 /**
       
    33    \file
       
    34    EtherCAT driver for RTL8139-compatible NICs.
       
    35 */
       
    36 
       
    37 /*****************************************************************************/
       
    38 
       
    39 /*
       
    40   Former documentation:
       
    41 
       
    42 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
       
    43 
       
    44 	Maintained by Jeff Garzik <jgarzik@pobox.com>
       
    45 	Copyright 2000-2002 Jeff Garzik
       
    46 
       
    47 	Much code comes from Donald Becker's rtl8139.c driver,
       
    48 	versions 1.13 and older.  This driver was originally based
       
    49 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:
       
    50 
       
    51 	-----<snip>-----
       
    52 
       
    53         	Written 1997-2001 by Donald Becker.
       
    54 		This software may be used and distributed according to the
       
    55 		terms of the GNU General Public License (GPL), incorporated
       
    56 		herein by reference.  Drivers based on or derived from this
       
    57 		code fall under the GPL and must retain the authorship,
       
    58 		copyright and license notice.  This file is not a complete
       
    59 		program and may only be used when the entire operating
       
    60 		system is licensed under the GPL.
       
    61 
       
    62 		This driver is for boards based on the RTL8129 and RTL8139
       
    63 		PCI ethernet chips.
       
    64 
       
    65 		The author may be reached as becker@scyld.com, or C/O Scyld
       
    66 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis
       
    67 		MD 21403
       
    68 
       
    69 		Support and updates available at
       
    70 		http://www.scyld.com/network/rtl8139.html
       
    71 
       
    72 		Twister-tuning table provided by Kinston
       
    73 		<shangh@realtek.com.tw>.
       
    74 
       
    75 	-----<snip>-----
       
    76 
       
    77 	This software may be used and distributed according to the terms
       
    78 	of the GNU General Public License, incorporated herein by reference.
       
    79 
       
    80 	Contributors:
       
    81 
       
    82 		Donald Becker - he wrote the original driver, kudos to him!
       
    83 		(but please don't e-mail him for support, this isn't his driver)
       
    84 
       
    85 		Tigran Aivazian - bug fixes, skbuff free cleanup
       
    86 
       
    87 		Martin Mares - suggestions for PCI cleanup
       
    88 
       
    89 		David S. Miller - PCI DMA and softnet updates
       
    90 
       
    91 		Ernst Gill - fixes ported from BSD driver
       
    92 
       
    93 		Daniel Kobras - identified specific locations of
       
    94 			posted MMIO write bugginess
       
    95 
       
    96 		Gerard Sharp - bug fix, testing and feedback
       
    97 
       
    98 		David Ford - Rx ring wrap fix
       
    99 
       
   100 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
       
   101 		to find and fix a crucial bug on older chipsets.
       
   102 
       
   103 		Donald Becker/Chris Butterworth/Marcus Westergren -
       
   104 		Noticed various Rx packet size-related buglets.
       
   105 
       
   106 		Santiago Garcia Mantinan - testing and feedback
       
   107 
       
   108 		Jens David - 2.2.x kernel backports
       
   109 
       
   110 		Martin Dennett - incredibly helpful insight on undocumented
       
   111 		features of the 8139 chips
       
   112 
       
   113 		Jean-Jacques Michel - bug fix
       
   114 
       
   115 		Tobias Ringström - Rx interrupt status checking suggestion
       
   116 
       
   117 		Andrew Morton - Clear blocked signals, avoid
       
   118 		buffer overrun setting current->comm.
       
   119 
       
   120 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls
       
   121 
       
   122 		Robert Kuebel - Save kernel thread from dying on any signal.
       
   123 
       
   124 	Submitting bug reports:
       
   125 
       
   126 		"rtl8139-diag -mmmaaavvveefN" output
       
   127 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
       
   128 
       
   129 */
       
   130 
       
   131 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
       
   132 
       
   133 #define DRV_NAME	"ec_8139too"
       
   134 #define DRV_VERSION	"0.9.28"
       
   135 
       
   136 
       
   137 #include <linux/module.h>
       
   138 #include <linux/kernel.h>
       
   139 #include <linux/compiler.h>
       
   140 #include <linux/pci.h>
       
   141 #include <linux/init.h>
       
   142 #include <linux/interrupt.h>
       
   143 #include <linux/netdevice.h>
       
   144 #include <linux/etherdevice.h>
       
   145 #include <linux/rtnetlink.h>
       
   146 #include <linux/delay.h>
       
   147 #include <linux/ethtool.h>
       
   148 #include <linux/mii.h>
       
   149 #include <linux/completion.h>
       
   150 #include <linux/crc32.h>
       
   151 #include <linux/io.h>
       
   152 #include <linux/uaccess.h>
       
   153 #include <linux/gfp.h>
       
   154 #include <asm/irq.h>
       
   155 
       
   156 #include "../globals.h"
       
   157 #include "ecdev.h"
       
   158 
       
   159 #define RTL8139_DRIVER_NAME DRV_NAME \
       
   160 	" EtherCAT-capable Fast Ethernet driver " \
       
   161 	DRV_VERSION ", master " EC_MASTER_VERSION
       
   162 
       
   163 #define PFX DRV_NAME ": "
       
   164 
       
   165 /* Default Message level */
       
   166 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \
       
   167                                  NETIF_MSG_PROBE  | \
       
   168                                  NETIF_MSG_LINK)
       
   169 
       
   170 
       
   171 /* define to 1, 2 or 3 to enable copious debugging info */
       
   172 #define RTL8139_DEBUG 0
       
   173 
       
   174 /* define to 1 to disable lightweight runtime debugging checks */
       
   175 #undef RTL8139_NDEBUG
       
   176 
       
   177 
       
   178 #ifdef RTL8139_NDEBUG
       
   179 #  define assert(expr) do {} while (0)
       
   180 #else
       
   181 #  define assert(expr) \
       
   182         if (unlikely(!(expr))) {				\
       
   183 		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\
       
   184 		       #expr, __FILE__, __func__, __LINE__);	\
       
   185         }
       
   186 #endif
       
   187 
       
   188 
       
   189 /* A few user-configurable values. */
       
   190 /* media options */
       
   191 #define MAX_UNITS 8
       
   192 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
       
   193 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
       
   194 
       
   195 /* Whether to use MMIO or PIO. Default to MMIO. */
       
   196 #ifdef CONFIG_8139TOO_PIO
       
   197 static bool use_io = true;
       
   198 #else
       
   199 static bool use_io = false;
       
   200 #endif
       
   201 
       
   202 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
       
   203    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
       
   204 static int multicast_filter_limit = 32;
       
   205 
       
   206 /* bitmapped message enable number */
       
   207 static int debug = -1;
       
   208 
       
   209 /*
       
   210  * Receive ring size
       
   211  * Warning: 64K ring has hardware issues and may lock up.
       
   212  */
       
   213 #if defined(CONFIG_SH_DREAMCAST)
       
   214 #define RX_BUF_IDX 0	/* 8K ring */
       
   215 #else
       
   216 #define RX_BUF_IDX	2	/* 32K ring */
       
   217 #endif
       
   218 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)
       
   219 #define RX_BUF_PAD	16
       
   220 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
       
   221 
       
   222 #if RX_BUF_LEN == 65536
       
   223 #define RX_BUF_TOT_LEN	RX_BUF_LEN
       
   224 #else
       
   225 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
       
   226 #endif
       
   227 
       
   228 /* Number of Tx descriptor registers. */
       
   229 #define NUM_TX_DESC	4
       
   230 
       
   231 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
       
   232 #define MAX_ETH_FRAME_SIZE	1536
       
   233 
       
   234 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
       
   235 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE
       
   236 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)
       
   237 
       
   238 /* PCI Tuning Parameters
       
   239    Threshold is bytes transferred to chip before transmission starts. */
       
   240 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
       
   241 
       
   242 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
       
   243 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */
       
   244 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */
       
   245 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
       
   246 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */
       
   247 
       
   248 /* Operational parameters that usually are not changed. */
       
   249 /* Time in jiffies before concluding the transmitter is hung. */
       
   250 #define TX_TIMEOUT  (6*HZ)
       
   251 
       
   252 
       
   253 enum {
       
   254 	HAS_MII_XCVR = 0x010000,
       
   255 	HAS_CHIP_XCVR = 0x020000,
       
   256 	HAS_LNK_CHNG = 0x040000,
       
   257 };
       
   258 
       
   259 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */
       
   260 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */
       
   261 #define RTL_MIN_IO_SIZE 0x80
       
   262 #define RTL8139B_IO_SIZE 256
       
   263 
       
   264 #define RTL8129_CAPS	HAS_MII_XCVR
       
   265 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)
       
   266 
       
   267 typedef enum {
       
   268 	RTL8139 = 0,
       
   269 	RTL8129,
       
   270 } board_t;
       
   271 
       
   272 
       
   273 /* indexed by board_t, above */
       
   274 static const struct {
       
   275 	const char *name;
       
   276 	u32 hw_flags;
       
   277 } board_info[] = {
       
   278 	{ "RealTek RTL8139", RTL8139_CAPS },
       
   279 	{ "RealTek RTL8129", RTL8129_CAPS },
       
   280 };
       
   281 
       
   282 
       
   283 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
       
   284 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   285 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   286 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   287 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   288 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   289 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   290 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   291 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   292 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   293 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   294 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   295 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   296 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   297 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   298 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   299 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   300 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   301 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   302 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   303 
       
   304 #ifdef CONFIG_SH_SECUREEDGE5410
       
   305 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */
       
   306 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   307 #endif
       
   308 #ifdef CONFIG_8139TOO_8129
       
   309 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
       
   310 #endif
       
   311 
       
   312 	/* some crazy cards report invalid vendor ids like
       
   313 	 * 0x0001 here.  The other ids are valid and constant,
       
   314 	 * so we simply don't match on the main vendor id.
       
   315 	 */
       
   316 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
       
   317 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
       
   318 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
       
   319 
       
   320 	{0,}
       
   321 };
       
   322 
       
   323 /* prevent driver from being loaded automatically */
       
   324 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
       
   325 
       
   326 static struct {
       
   327 	const char str[ETH_GSTRING_LEN];
       
   328 } ethtool_stats_keys[] = {
       
   329 	{ "early_rx" },
       
   330 	{ "tx_buf_mapped" },
       
   331 	{ "tx_timeouts" },
       
   332 	{ "rx_lost_in_ring" },
       
   333 };
       
   334 
       
   335 /* The rest of these values should never change. */
       
   336 
       
   337 /* Symbolic offsets to registers. */
       
   338 enum RTL8139_registers {
       
   339 	MAC0		= 0,	 /* Ethernet hardware address. */
       
   340 	MAR0		= 8,	 /* Multicast filter. */
       
   341 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */
       
   342 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */
       
   343 	RxBuf		= 0x30,
       
   344 	ChipCmd		= 0x37,
       
   345 	RxBufPtr	= 0x38,
       
   346 	RxBufAddr	= 0x3A,
       
   347 	IntrMask	= 0x3C,
       
   348 	IntrStatus	= 0x3E,
       
   349 	TxConfig	= 0x40,
       
   350 	RxConfig	= 0x44,
       
   351 	Timer		= 0x48,	 /* A general-purpose counter. */
       
   352 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */
       
   353 	Cfg9346		= 0x50,
       
   354 	Config0		= 0x51,
       
   355 	Config1		= 0x52,
       
   356 	TimerInt	= 0x54,
       
   357 	MediaStatus	= 0x58,
       
   358 	Config3		= 0x59,
       
   359 	Config4		= 0x5A,	 /* absent on RTL-8139A */
       
   360 	HltClk		= 0x5B,
       
   361 	MultiIntr	= 0x5C,
       
   362 	TxSummary	= 0x60,
       
   363 	BasicModeCtrl	= 0x62,
       
   364 	BasicModeStatus	= 0x64,
       
   365 	NWayAdvert	= 0x66,
       
   366 	NWayLPAR	= 0x68,
       
   367 	NWayExpansion	= 0x6A,
       
   368 	/* Undocumented registers, but required for proper operation. */
       
   369 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */
       
   370 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */
       
   371 	PARA78		= 0x78,
       
   372 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */
       
   373 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */
       
   374 	Config5		= 0xD8,	 /* absent on RTL-8139A */
       
   375 };
       
   376 
       
   377 enum ClearBitMasks {
       
   378 	MultiIntrClear	= 0xF000,
       
   379 	ChipCmdClear	= 0xE2,
       
   380 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
       
   381 };
       
   382 
       
   383 enum ChipCmdBits {
       
   384 	CmdReset	= 0x10,
       
   385 	CmdRxEnb	= 0x08,
       
   386 	CmdTxEnb	= 0x04,
       
   387 	RxBufEmpty	= 0x01,
       
   388 };
       
   389 
       
   390 /* Interrupt register bits, using my own meaningful names. */
       
   391 enum IntrStatusBits {
       
   392 	PCIErr		= 0x8000,
       
   393 	PCSTimeout	= 0x4000,
       
   394 	RxFIFOOver	= 0x40,
       
   395 	RxUnderrun	= 0x20,
       
   396 	RxOverflow	= 0x10,
       
   397 	TxErr		= 0x08,
       
   398 	TxOK		= 0x04,
       
   399 	RxErr		= 0x02,
       
   400 	RxOK		= 0x01,
       
   401 
       
   402 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,
       
   403 };
       
   404 
       
   405 enum TxStatusBits {
       
   406 	TxHostOwns	= 0x2000,
       
   407 	TxUnderrun	= 0x4000,
       
   408 	TxStatOK	= 0x8000,
       
   409 	TxOutOfWindow	= 0x20000000,
       
   410 	TxAborted	= 0x40000000,
       
   411 	TxCarrierLost	= 0x80000000,
       
   412 };
       
   413 enum RxStatusBits {
       
   414 	RxMulticast	= 0x8000,
       
   415 	RxPhysical	= 0x4000,
       
   416 	RxBroadcast	= 0x2000,
       
   417 	RxBadSymbol	= 0x0020,
       
   418 	RxRunt		= 0x0010,
       
   419 	RxTooLong	= 0x0008,
       
   420 	RxCRCErr	= 0x0004,
       
   421 	RxBadAlign	= 0x0002,
       
   422 	RxStatusOK	= 0x0001,
       
   423 };
       
   424 
       
   425 /* Bits in RxConfig. */
       
   426 enum rx_mode_bits {
       
   427 	AcceptErr	= 0x20,
       
   428 	AcceptRunt	= 0x10,
       
   429 	AcceptBroadcast	= 0x08,
       
   430 	AcceptMulticast	= 0x04,
       
   431 	AcceptMyPhys	= 0x02,
       
   432 	AcceptAllPhys	= 0x01,
       
   433 };
       
   434 
       
   435 /* Bits in TxConfig. */
       
   436 enum tx_config_bits {
       
   437         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
       
   438         TxIFGShift	= 24,
       
   439         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
       
   440         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
       
   441         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
       
   442         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
       
   443 
       
   444 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */
       
   445 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */
       
   446 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */
       
   447 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */
       
   448 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */
       
   449 
       
   450 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */
       
   451 };
       
   452 
       
   453 /* Bits in Config1 */
       
   454 enum Config1Bits {
       
   455 	Cfg1_PM_Enable	= 0x01,
       
   456 	Cfg1_VPD_Enable	= 0x02,
       
   457 	Cfg1_PIO	= 0x04,
       
   458 	Cfg1_MMIO	= 0x08,
       
   459 	LWAKE		= 0x10,		/* not on 8139, 8139A */
       
   460 	Cfg1_Driver_Load = 0x20,
       
   461 	Cfg1_LED0	= 0x40,
       
   462 	Cfg1_LED1	= 0x80,
       
   463 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */
       
   464 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */
       
   465 };
       
   466 
       
   467 /* Bits in Config3 */
       
   468 enum Config3Bits {
       
   469 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */
       
   470 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */
       
   471 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */
       
   472 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */
       
   473 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */
       
   474 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */
       
   475 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */
       
   476 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */
       
   477 };
       
   478 
       
   479 /* Bits in Config4 */
       
   480 enum Config4Bits {
       
   481 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */
       
   482 };
       
   483 
       
   484 /* Bits in Config5 */
       
   485 enum Config5Bits {
       
   486 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */
       
   487 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */
       
   488 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */
       
   489 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
       
   490 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */
       
   491 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */
       
   492 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */
       
   493 };
       
   494 
       
   495 enum RxConfigBits {
       
   496 	/* rx fifo threshold */
       
   497 	RxCfgFIFOShift	= 13,
       
   498 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),
       
   499 
       
   500 	/* Max DMA burst */
       
   501 	RxCfgDMAShift	= 8,
       
   502 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
       
   503 
       
   504 	/* rx ring buffer length */
       
   505 	RxCfgRcv8K	= 0,
       
   506 	RxCfgRcv16K	= (1 << 11),
       
   507 	RxCfgRcv32K	= (1 << 12),
       
   508 	RxCfgRcv64K	= (1 << 11) | (1 << 12),
       
   509 
       
   510 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
       
   511 	RxNoWrap	= (1 << 7),
       
   512 };
       
   513 
       
   514 /* Twister tuning parameters from RealTek.
       
   515    Completely undocumented, but required to tune bad links on some boards. */
       
   516 enum CSCRBits {
       
   517 	CSCR_LinkOKBit		= 0x0400,
       
   518 	CSCR_LinkChangeBit	= 0x0800,
       
   519 	CSCR_LinkStatusBits	= 0x0f000,
       
   520 	CSCR_LinkDownOffCmd	= 0x003c0,
       
   521 	CSCR_LinkDownCmd	= 0x0f3c0,
       
   522 };
       
   523 
       
   524 enum Cfg9346Bits {
       
   525 	Cfg9346_Lock	= 0x00,
       
   526 	Cfg9346_Unlock	= 0xC0,
       
   527 };
       
   528 
       
   529 typedef enum {
       
   530 	CH_8139	= 0,
       
   531 	CH_8139_K,
       
   532 	CH_8139A,
       
   533 	CH_8139A_G,
       
   534 	CH_8139B,
       
   535 	CH_8130,
       
   536 	CH_8139C,
       
   537 	CH_8100,
       
   538 	CH_8100B_8139D,
       
   539 	CH_8101,
       
   540 } chip_t;
       
   541 
       
   542 enum chip_flags {
       
   543 	HasHltClk	= (1 << 0),
       
   544 	HasLWake	= (1 << 1),
       
   545 };
       
   546 
       
   547 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
       
   548 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
       
   549 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)
       
   550 
       
   551 /* directly indexed by chip_t, above */
       
   552 static const struct {
       
   553 	const char *name;
       
   554 	u32 version; /* from RTL8139C/RTL8139D docs */
       
   555 	u32 flags;
       
   556 } rtl_chip_info[] = {
       
   557 	{ "RTL-8139",
       
   558 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),
       
   559 	  HasHltClk,
       
   560 	},
       
   561 
       
   562 	{ "RTL-8139 rev K",
       
   563 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),
       
   564 	  HasHltClk,
       
   565 	},
       
   566 
       
   567 	{ "RTL-8139A",
       
   568 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),
       
   569 	  HasHltClk, /* XXX undocumented? */
       
   570 	},
       
   571 
       
   572 	{ "RTL-8139A rev G",
       
   573 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),
       
   574 	  HasHltClk, /* XXX undocumented? */
       
   575 	},
       
   576 
       
   577 	{ "RTL-8139B",
       
   578 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),
       
   579 	  HasLWake,
       
   580 	},
       
   581 
       
   582 	{ "RTL-8130",
       
   583 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),
       
   584 	  HasLWake,
       
   585 	},
       
   586 
       
   587 	{ "RTL-8139C",
       
   588 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),
       
   589 	  HasLWake,
       
   590 	},
       
   591 
       
   592 	{ "RTL-8100",
       
   593 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),
       
   594  	  HasLWake,
       
   595  	},
       
   596 
       
   597 	{ "RTL-8100B/8139D",
       
   598 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),
       
   599 	  HasHltClk /* XXX undocumented? */
       
   600 	| HasLWake,
       
   601 	},
       
   602 
       
   603 	{ "RTL-8101",
       
   604 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),
       
   605 	  HasLWake,
       
   606 	},
       
   607 };
       
   608 
       
   609 struct rtl_extra_stats {
       
   610 	unsigned long early_rx;
       
   611 	unsigned long tx_buf_mapped;
       
   612 	unsigned long tx_timeouts;
       
   613 	unsigned long rx_lost_in_ring;
       
   614 };
       
   615 
       
   616 struct rtl8139_stats {
       
   617 	u64	packets;
       
   618 	u64	bytes;
       
   619 	struct u64_stats_sync	syncp;
       
   620 };
       
   621 
       
   622 struct rtl8139_private {
       
   623 	void __iomem		*mmio_addr;
       
   624 	int			drv_flags;
       
   625 	struct pci_dev		*pci_dev;
       
   626 	u32			msg_enable;
       
   627 	struct napi_struct	napi;
       
   628 	struct net_device	*dev;
       
   629 
       
   630 	unsigned char		*rx_ring;
       
   631 	unsigned int		cur_rx;	/* RX buf index of next pkt */
       
   632 	struct rtl8139_stats	rx_stats;
       
   633 	dma_addr_t		rx_ring_dma;
       
   634 
       
   635 	unsigned int		tx_flag;
       
   636 	unsigned long		cur_tx;
       
   637 	unsigned long		dirty_tx;
       
   638 	struct rtl8139_stats	tx_stats;
       
   639 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */
       
   640 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */
       
   641 	dma_addr_t		tx_bufs_dma;
       
   642 
       
   643 	signed char		phys[4];	/* MII device addresses. */
       
   644 
       
   645 				/* Twister tune state. */
       
   646 	char			twistie, twist_row, twist_col;
       
   647 
       
   648 	unsigned int		watchdog_fired : 1;
       
   649 	unsigned int		default_port : 4; /* Last dev->if_port value. */
       
   650 	unsigned int		have_thread : 1;
       
   651 
       
   652 	spinlock_t		lock;
       
   653 	spinlock_t		rx_lock;
       
   654 
       
   655 	chip_t			chipset;
       
   656 	u32			rx_config;
       
   657 	struct rtl_extra_stats	xstats;
       
   658 
       
   659 	struct delayed_work	thread;
       
   660 
       
   661 	struct mii_if_info	mii;
       
   662 	unsigned int		regs_len;
       
   663 	unsigned long		fifo_copy_timeout;
       
   664 
       
   665 	ec_device_t *ecdev;
       
   666 };
       
   667 
       
   668 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");
       
   669 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");
       
   670 MODULE_LICENSE("GPL");
       
   671 MODULE_VERSION(EC_MASTER_VERSION);
       
   672 
       
   673 module_param(use_io, bool, 0);
       
   674 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
       
   675 module_param(multicast_filter_limit, int, 0);
       
   676 module_param_array(media, int, NULL, 0);
       
   677 module_param_array(full_duplex, int, NULL, 0);
       
   678 module_param(debug, int, 0);
       
   679 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
       
   680 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
       
   681 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
       
   682 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
       
   683 
       
   684 void ec_poll(struct net_device *);
       
   685 
       
   686 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
       
   687 static int rtl8139_open (struct net_device *dev);
       
   688 static int mdio_read (struct net_device *dev, int phy_id, int location);
       
   689 static void mdio_write (struct net_device *dev, int phy_id, int location,
       
   690 			int val);
       
   691 static void rtl8139_start_thread(struct rtl8139_private *tp);
       
   692 static void rtl8139_tx_timeout (struct net_device *dev);
       
   693 static void rtl8139_init_ring (struct net_device *dev);
       
   694 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
       
   695 				       struct net_device *dev);
       
   696 #ifdef CONFIG_NET_POLL_CONTROLLER
       
   697 static void rtl8139_poll_controller(struct net_device *dev);
       
   698 #endif
       
   699 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
       
   700 static int rtl8139_poll(struct napi_struct *napi, int budget);
       
   701 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
       
   702 static int rtl8139_close (struct net_device *dev);
       
   703 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
       
   704 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
       
   705 						    struct rtnl_link_stats64
       
   706 						    *stats);
       
   707 static void rtl8139_set_rx_mode (struct net_device *dev);
       
   708 static void __set_rx_mode (struct net_device *dev);
       
   709 static void rtl8139_hw_start (struct net_device *dev);
       
   710 static void rtl8139_thread (struct work_struct *work);
       
   711 static void rtl8139_tx_timeout_task(struct work_struct *work);
       
   712 static const struct ethtool_ops rtl8139_ethtool_ops;
       
   713 
       
   714 /* write MMIO register, with flush */
       
   715 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
       
   716 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
       
   717 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
       
   718 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
       
   719 
       
   720 /* write MMIO register */
       
   721 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))
       
   722 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))
       
   723 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))
       
   724 
       
   725 /* read MMIO register */
       
   726 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))
       
   727 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))
       
   728 #define RTL_R32(reg)		ioread32 (ioaddr + (reg))
       
   729 
       
   730 
       
   731 static const u16 rtl8139_intr_mask =
       
   732 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
       
   733 	TxErr | TxOK | RxErr | RxOK;
       
   734 
       
   735 static const u16 rtl8139_norx_intr_mask =
       
   736 	PCIErr | PCSTimeout | RxUnderrun |
       
   737 	TxErr | TxOK | RxErr ;
       
   738 
       
   739 #if RX_BUF_IDX == 0
       
   740 static const unsigned int rtl8139_rx_config =
       
   741 	RxCfgRcv8K | RxNoWrap |
       
   742 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   743 	(RX_DMA_BURST << RxCfgDMAShift);
       
   744 #elif RX_BUF_IDX == 1
       
   745 static const unsigned int rtl8139_rx_config =
       
   746 	RxCfgRcv16K | RxNoWrap |
       
   747 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   748 	(RX_DMA_BURST << RxCfgDMAShift);
       
   749 #elif RX_BUF_IDX == 2
       
   750 static const unsigned int rtl8139_rx_config =
       
   751 	RxCfgRcv32K | RxNoWrap |
       
   752 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   753 	(RX_DMA_BURST << RxCfgDMAShift);
       
   754 #elif RX_BUF_IDX == 3
       
   755 static const unsigned int rtl8139_rx_config =
       
   756 	RxCfgRcv64K |
       
   757 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   758 	(RX_DMA_BURST << RxCfgDMAShift);
       
   759 #else
       
   760 #error "Invalid configuration for 8139_RXBUF_IDX"
       
   761 #endif
       
   762 
       
   763 static const unsigned int rtl8139_tx_config =
       
   764 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
       
   765 
       
   766 static void __rtl8139_cleanup_dev (struct net_device *dev)
       
   767 {
       
   768 	struct rtl8139_private *tp = netdev_priv(dev);
       
   769 	struct pci_dev *pdev;
       
   770 
       
   771 	assert (dev != NULL);
       
   772 	assert (tp->pci_dev != NULL);
       
   773 	pdev = tp->pci_dev;
       
   774 
       
   775 	if (tp->mmio_addr)
       
   776 		pci_iounmap (pdev, tp->mmio_addr);
       
   777 
       
   778 	/* it's ok to call this even if we have no regions to free */
       
   779 	pci_release_regions (pdev);
       
   780 
       
   781 	free_netdev(dev);
       
   782 	pci_set_drvdata (pdev, NULL);
       
   783 }
       
   784 
       
   785 
       
   786 static void rtl8139_chip_reset (void __iomem *ioaddr)
       
   787 {
       
   788 	int i;
       
   789 
       
   790 	/* Soft reset the chip. */
       
   791 	RTL_W8 (ChipCmd, CmdReset);
       
   792 
       
   793 	/* Check that the chip has finished the reset. */
       
   794 	for (i = 1000; i > 0; i--) {
       
   795 		barrier();
       
   796 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
       
   797 			break;
       
   798 		udelay (10);
       
   799 	}
       
   800 }
       
   801 
       
   802 
       
   803 static struct net_device *rtl8139_init_board(struct pci_dev *pdev)
       
   804 {
       
   805 	struct device *d = &pdev->dev;
       
   806 	void __iomem *ioaddr;
       
   807 	struct net_device *dev;
       
   808 	struct rtl8139_private *tp;
       
   809 	u8 tmp8;
       
   810 	int rc, disable_dev_on_err = 0;
       
   811 	unsigned int i, bar;
       
   812 	unsigned long io_len;
       
   813 	u32 version;
       
   814 	static const struct {
       
   815 		unsigned long mask;
       
   816 		char *type;
       
   817 	} res[] = {
       
   818 		{ IORESOURCE_IO,  "PIO" },
       
   819 		{ IORESOURCE_MEM, "MMIO" }
       
   820 	};
       
   821 
       
   822 	assert (pdev != NULL);
       
   823 
       
   824 	/* dev and priv zeroed in alloc_etherdev */
       
   825 	dev = alloc_etherdev (sizeof (*tp));
       
   826 	if (dev == NULL)
       
   827 		return ERR_PTR(-ENOMEM);
       
   828 
       
   829 	SET_NETDEV_DEV(dev, &pdev->dev);
       
   830 
       
   831 	tp = netdev_priv(dev);
       
   832 	tp->pci_dev = pdev;
       
   833 
       
   834 	/* enable device (incl. PCI PM wakeup and hotplug setup) */
       
   835 	rc = pci_enable_device (pdev);
       
   836 	if (rc)
       
   837 		goto err_out;
       
   838 
       
   839 	rc = pci_request_regions (pdev, DRV_NAME);
       
   840 	if (rc)
       
   841 		goto err_out;
       
   842 	disable_dev_on_err = 1;
       
   843 
       
   844 	pci_set_master (pdev);
       
   845 
       
   846 retry:
       
   847 	/* PIO bar register comes first. */
       
   848 	bar = !use_io;
       
   849 
       
   850 	io_len = pci_resource_len(pdev, bar);
       
   851 
       
   852 	dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
       
   853 
       
   854 	if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
       
   855 		dev_err(d, "region #%d not a %s resource, aborting\n", bar,
       
   856 			res[bar].type);
       
   857 		rc = -ENODEV;
       
   858 		goto err_out;
       
   859 	}
       
   860 	if (io_len < RTL_MIN_IO_SIZE) {
       
   861 		dev_err(d, "Invalid PCI %s region size(s), aborting\n",
       
   862 			res[bar].type);
       
   863 		rc = -ENODEV;
       
   864 		goto err_out;
       
   865 	}
       
   866 
       
   867 	ioaddr = pci_iomap(pdev, bar, 0);
       
   868 	if (!ioaddr) {
       
   869 		dev_err(d, "cannot map %s\n", res[bar].type);
       
   870 		if (!use_io) {
       
   871 			use_io = true;
       
   872 			goto retry;
       
   873 		}
       
   874 		rc = -ENODEV;
       
   875 		goto err_out;
       
   876 	}
       
   877 	tp->regs_len = io_len;
       
   878 	tp->mmio_addr = ioaddr;
       
   879 
       
   880 	/* Bring old chips out of low-power mode. */
       
   881 	RTL_W8 (HltClk, 'R');
       
   882 
       
   883 	/* check for missing/broken hardware */
       
   884 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
       
   885 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
       
   886 		rc = -EIO;
       
   887 		goto err_out;
       
   888 	}
       
   889 
       
   890 	/* identify chip attached to board */
       
   891 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;
       
   892 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
       
   893 		if (version == rtl_chip_info[i].version) {
       
   894 			tp->chipset = i;
       
   895 			goto match;
       
   896 		}
       
   897 
       
   898 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */
       
   899 	i = 0;
       
   900 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
       
   901 	dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
       
   902 	tp->chipset = 0;
       
   903 
       
   904 match:
       
   905 	pr_debug("chipset id (%d) == index %d, '%s'\n",
       
   906 		 version, i, rtl_chip_info[i].name);
       
   907 
       
   908 	if (tp->chipset >= CH_8139B) {
       
   909 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
       
   910 		pr_debug("PCI PM wakeup\n");
       
   911 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
       
   912 		    (tmp8 & LWAKE))
       
   913 			new_tmp8 &= ~LWAKE;
       
   914 		new_tmp8 |= Cfg1_PM_Enable;
       
   915 		if (new_tmp8 != tmp8) {
       
   916 			RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
   917 			RTL_W8 (Config1, tmp8);
       
   918 			RTL_W8 (Cfg9346, Cfg9346_Lock);
       
   919 		}
       
   920 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {
       
   921 			tmp8 = RTL_R8 (Config4);
       
   922 			if (tmp8 & LWPTN) {
       
   923 				RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
   924 				RTL_W8 (Config4, tmp8 & ~LWPTN);
       
   925 				RTL_W8 (Cfg9346, Cfg9346_Lock);
       
   926 			}
       
   927 		}
       
   928 	} else {
       
   929 		pr_debug("Old chip wakeup\n");
       
   930 		tmp8 = RTL_R8 (Config1);
       
   931 		tmp8 &= ~(SLEEP | PWRDN);
       
   932 		RTL_W8 (Config1, tmp8);
       
   933 	}
       
   934 
       
   935 	rtl8139_chip_reset (ioaddr);
       
   936 
       
   937 	return dev;
       
   938 
       
   939 err_out:
       
   940 	__rtl8139_cleanup_dev (dev);
       
   941 	if (disable_dev_on_err)
       
   942 		pci_disable_device (pdev);
       
   943 	return ERR_PTR(rc);
       
   944 }
       
   945 
       
   946 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
       
   947 {
       
   948 	struct rtl8139_private *tp = netdev_priv(dev);
       
   949 	unsigned long flags;
       
   950 	netdev_features_t changed = features ^ dev->features;
       
   951 	void __iomem *ioaddr = tp->mmio_addr;
       
   952 
       
   953 	if (!(changed & (NETIF_F_RXALL)))
       
   954 		return 0;
       
   955 
       
   956 	spin_lock_irqsave(&tp->lock, flags);
       
   957 
       
   958 	if (changed & NETIF_F_RXALL) {
       
   959 		int rx_mode = tp->rx_config;
       
   960 		if (features & NETIF_F_RXALL)
       
   961 			rx_mode |= (AcceptErr | AcceptRunt);
       
   962 		else
       
   963 			rx_mode &= ~(AcceptErr | AcceptRunt);
       
   964 		tp->rx_config = rtl8139_rx_config | rx_mode;
       
   965 		RTL_W32_F(RxConfig, tp->rx_config);
       
   966 	}
       
   967 
       
   968 	spin_unlock_irqrestore(&tp->lock, flags);
       
   969 
       
   970 	return 0;
       
   971 }
       
   972 
       
   973 static const struct net_device_ops rtl8139_netdev_ops = {
       
   974 	.ndo_open		= rtl8139_open,
       
   975 	.ndo_stop		= rtl8139_close,
       
   976 	.ndo_get_stats64	= rtl8139_get_stats64,
       
   977 	.ndo_change_mtu		= eth_change_mtu,
       
   978 	.ndo_validate_addr	= eth_validate_addr,
       
   979 	.ndo_set_mac_address 	= rtl8139_set_mac_address,
       
   980 	.ndo_start_xmit		= rtl8139_start_xmit,
       
   981 	.ndo_set_rx_mode	= rtl8139_set_rx_mode,
       
   982 	.ndo_do_ioctl		= netdev_ioctl,
       
   983 	.ndo_tx_timeout		= rtl8139_tx_timeout,
       
   984 #ifdef CONFIG_NET_POLL_CONTROLLER
       
   985 	.ndo_poll_controller	= rtl8139_poll_controller,
       
   986 #endif
       
   987 	.ndo_set_features	= rtl8139_set_features,
       
   988 };
       
   989 
       
   990 static int rtl8139_init_one(struct pci_dev *pdev,
       
   991 			    const struct pci_device_id *ent)
       
   992 {
       
   993 	struct net_device *dev = NULL;
       
   994 	struct rtl8139_private *tp;
       
   995 	int i, addr_len, option;
       
   996 	void __iomem *ioaddr;
       
   997 	static int board_idx = -1;
       
   998 
       
   999 	assert (pdev != NULL);
       
  1000 	assert (ent != NULL);
       
  1001 
       
  1002 	board_idx++;
       
  1003 
       
  1004 	/* when we're built into the kernel, the driver version message
       
  1005 	 * is only printed if at least one 8139 board has been found
       
  1006 	 */
       
  1007 #ifndef MODULE
       
  1008 	{
       
  1009 		static int printed_version;
       
  1010 		if (!printed_version++)
       
  1011 			pr_info(RTL8139_DRIVER_NAME "\n");
       
  1012 	}
       
  1013 #endif
       
  1014 
       
  1015 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
       
  1016 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
       
  1017 		dev_info(&pdev->dev,
       
  1018 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
       
  1019 		       	   pdev->vendor, pdev->device, pdev->revision);
       
  1020 		return -ENODEV;
       
  1021 	}
       
  1022 
       
  1023 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
       
  1024 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
       
  1025 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
       
  1026 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
       
  1027 		pr_info("OQO Model 2 detected. Forcing PIO\n");
       
  1028 		use_io = 1;
       
  1029 	}
       
  1030 
       
  1031 	dev = rtl8139_init_board (pdev);
       
  1032 	if (IS_ERR(dev))
       
  1033 		return PTR_ERR(dev);
       
  1034 
       
  1035 	assert (dev != NULL);
       
  1036 	tp = netdev_priv(dev);
       
  1037 	tp->dev = dev;
       
  1038 
       
  1039 	ioaddr = tp->mmio_addr;
       
  1040 	assert (ioaddr != NULL);
       
  1041 
       
  1042 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
       
  1043 	for (i = 0; i < 3; i++)
       
  1044 		((__le16 *) (dev->dev_addr))[i] =
       
  1045 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
       
  1046 
       
  1047 	/* The Rtl8139-specific entries in the device structure. */
       
  1048 	dev->netdev_ops = &rtl8139_netdev_ops;
       
  1049 	dev->ethtool_ops = &rtl8139_ethtool_ops;
       
  1050 	dev->watchdog_timeo = TX_TIMEOUT;
       
  1051 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
       
  1052 
       
  1053 	/* note: the hardware is not capable of sg/csum/highdma, however
       
  1054 	 * through the use of skb_copy_and_csum_dev we enable these
       
  1055 	 * features
       
  1056 	 */
       
  1057 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
       
  1058 	dev->vlan_features = dev->features;
       
  1059 
       
  1060 	dev->hw_features |= NETIF_F_RXALL;
       
  1061 	dev->hw_features |= NETIF_F_RXFCS;
       
  1062 
       
  1063 	/* tp zeroed and aligned in alloc_etherdev */
       
  1064 	tp = netdev_priv(dev);
       
  1065 
       
  1066 	/* note: tp->chipset set in rtl8139_init_board */
       
  1067 	tp->drv_flags = board_info[ent->driver_data].hw_flags;
       
  1068 	tp->mmio_addr = ioaddr;
       
  1069 	tp->msg_enable =
       
  1070 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
       
  1071 	spin_lock_init (&tp->lock);
       
  1072 	spin_lock_init (&tp->rx_lock);
       
  1073 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
       
  1074 	tp->mii.dev = dev;
       
  1075 	tp->mii.mdio_read = mdio_read;
       
  1076 	tp->mii.mdio_write = mdio_write;
       
  1077 	tp->mii.phy_id_mask = 0x3f;
       
  1078 	tp->mii.reg_num_mask = 0x1f;
       
  1079 
       
  1080 	/* dev is fully set up and ready to use now */
       
  1081 
       
  1082 	// offer device to EtherCAT master module
       
  1083 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);
       
  1084 
       
  1085 	if (!tp->ecdev) {
       
  1086 		pr_debug("about to register device named %s (%p)...\n",
       
  1087 				dev->name, dev);
       
  1088 		i = register_netdev (dev);
       
  1089 		if (i) goto err_out;
       
  1090 	}
       
  1091 
       
  1092 	pci_set_drvdata (pdev, dev);
       
  1093 
       
  1094 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",
       
  1095 		dev->name,
       
  1096 		board_info[ent->driver_data].name,
       
  1097 		dev->base_addr,
       
  1098 		dev->dev_addr,
       
  1099 		dev->irq);
       
  1100 
       
  1101 	pr_debug("%s:  Identified 8139 chip type '%s'\n",
       
  1102 		dev->name, rtl_chip_info[tp->chipset].name);
       
  1103 
       
  1104 	/* Find the connected MII xcvrs.
       
  1105 	   Doing this in open() would allow detecting external xcvrs later, but
       
  1106 	   takes too much time. */
       
  1107 #ifdef CONFIG_8139TOO_8129
       
  1108 	if (tp->drv_flags & HAS_MII_XCVR) {
       
  1109 		int phy, phy_idx = 0;
       
  1110 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
       
  1111 			int mii_status = mdio_read(dev, phy, 1);
       
  1112 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {
       
  1113 				u16 advertising = mdio_read(dev, phy, 4);
       
  1114 				tp->phys[phy_idx++] = phy;
       
  1115 				pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",
       
  1116 					   dev->name, phy, mii_status, advertising);
       
  1117 			}
       
  1118 		}
       
  1119 		if (phy_idx == 0) {
       
  1120 			pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",
       
  1121 				   dev->name);
       
  1122 			tp->phys[0] = 32;
       
  1123 		}
       
  1124 	} else
       
  1125 #endif
       
  1126 		tp->phys[0] = 32;
       
  1127 	tp->mii.phy_id = tp->phys[0];
       
  1128 
       
  1129 	/* The lower four bits are the media type. */
       
  1130 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
       
  1131 	if (option > 0) {
       
  1132 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
       
  1133 		tp->default_port = option & 0xFF;
       
  1134 		if (tp->default_port)
       
  1135 			tp->mii.force_media = 1;
       
  1136 	}
       
  1137 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)
       
  1138 		tp->mii.full_duplex = full_duplex[board_idx];
       
  1139 	if (tp->mii.full_duplex) {
       
  1140 		pr_info("%s: Media type forced to Full Duplex.\n", dev->name);
       
  1141 		/* Changing the MII-advertised media because might prevent
       
  1142 		   re-connection. */
       
  1143 		tp->mii.force_media = 1;
       
  1144 	}
       
  1145 	if (tp->default_port) {
       
  1146 		pr_info("  Forcing %dMbps %s-duplex operation.\n",
       
  1147 			   (option & 0x20 ? 100 : 10),
       
  1148 			   (option & 0x10 ? "full" : "half"));
       
  1149 		mdio_write(dev, tp->phys[0], 0,
       
  1150 				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */
       
  1151 				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
       
  1152 	}
       
  1153 
       
  1154 	/* Put the chip into low-power mode. */
       
  1155 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
       
  1156 		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
       
  1157 
       
  1158 	if (tp->ecdev) {
       
  1159 		i = ecdev_open(tp->ecdev);
       
  1160 		if (i) {
       
  1161 			ecdev_withdraw(tp->ecdev);
       
  1162 			goto err_out;
       
  1163 		}
       
  1164 	}
       
  1165 
       
  1166 	return 0;
       
  1167 
       
  1168 err_out:
       
  1169 	__rtl8139_cleanup_dev (dev);
       
  1170 	pci_disable_device (pdev);
       
  1171 	return i;
       
  1172 }
       
  1173 
       
  1174 
       
  1175 static void rtl8139_remove_one(struct pci_dev *pdev)
       
  1176 {
       
  1177 	struct net_device *dev = pci_get_drvdata (pdev);
       
  1178 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1179 
       
  1180 	assert (dev != NULL);
       
  1181 
       
  1182 	if (tp->ecdev) {
       
  1183 		ecdev_close(tp->ecdev);
       
  1184 		ecdev_withdraw(tp->ecdev);
       
  1185 	}
       
  1186 	else {
       
  1187 		cancel_delayed_work_sync(&tp->thread);
       
  1188 
       
  1189 		unregister_netdev (dev);
       
  1190 	}
       
  1191 
       
  1192 	__rtl8139_cleanup_dev (dev);
       
  1193 	pci_disable_device (pdev);
       
  1194 }
       
  1195 
       
  1196 
       
  1197 /* Serial EEPROM section. */
       
  1198 
       
  1199 /*  EEPROM_Ctrl bits. */
       
  1200 #define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
       
  1201 #define EE_CS			0x08	/* EEPROM chip select. */
       
  1202 #define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
       
  1203 #define EE_WRITE_0		0x00
       
  1204 #define EE_WRITE_1		0x02
       
  1205 #define EE_DATA_READ	0x01	/* EEPROM chip data out. */
       
  1206 #define EE_ENB			(0x80 | EE_CS)
       
  1207 
       
  1208 /* Delay between EEPROM clock transitions.
       
  1209    No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
       
  1210  */
       
  1211 
       
  1212 #define eeprom_delay()	(void)RTL_R8(Cfg9346)
       
  1213 
       
  1214 /* The EEPROM commands include the alway-set leading bit. */
       
  1215 #define EE_WRITE_CMD	(5)
       
  1216 #define EE_READ_CMD		(6)
       
  1217 #define EE_ERASE_CMD	(7)
       
  1218 
       
  1219 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len)
       
  1220 {
       
  1221 	int i;
       
  1222 	unsigned retval = 0;
       
  1223 	int read_cmd = location | (EE_READ_CMD << addr_len);
       
  1224 
       
  1225 	RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
       
  1226 	RTL_W8 (Cfg9346, EE_ENB);
       
  1227 	eeprom_delay ();
       
  1228 
       
  1229 	/* Shift the read command bits out. */
       
  1230 	for (i = 4 + addr_len; i >= 0; i--) {
       
  1231 		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
       
  1232 		RTL_W8 (Cfg9346, EE_ENB | dataval);
       
  1233 		eeprom_delay ();
       
  1234 		RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
       
  1235 		eeprom_delay ();
       
  1236 	}
       
  1237 	RTL_W8 (Cfg9346, EE_ENB);
       
  1238 	eeprom_delay ();
       
  1239 
       
  1240 	for (i = 16; i > 0; i--) {
       
  1241 		RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
       
  1242 		eeprom_delay ();
       
  1243 		retval =
       
  1244 		    (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
       
  1245 				     0);
       
  1246 		RTL_W8 (Cfg9346, EE_ENB);
       
  1247 		eeprom_delay ();
       
  1248 	}
       
  1249 
       
  1250 	/* Terminate the EEPROM access. */
       
  1251 	RTL_W8(Cfg9346, 0);
       
  1252 	eeprom_delay ();
       
  1253 
       
  1254 	return retval;
       
  1255 }
       
  1256 
       
  1257 /* MII serial management: mostly bogus for now. */
       
  1258 /* Read and write the MII management registers using software-generated
       
  1259    serial MDIO protocol.
       
  1260    The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
       
  1261    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
       
  1262    "overclocking" issues. */
       
  1263 #define MDIO_DIR		0x80
       
  1264 #define MDIO_DATA_OUT	0x04
       
  1265 #define MDIO_DATA_IN	0x02
       
  1266 #define MDIO_CLK		0x01
       
  1267 #define MDIO_WRITE0 (MDIO_DIR)
       
  1268 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
       
  1269 
       
  1270 #define mdio_delay()	RTL_R8(Config4)
       
  1271 
       
  1272 
       
  1273 static const char mii_2_8139_map[8] = {
       
  1274 	BasicModeCtrl,
       
  1275 	BasicModeStatus,
       
  1276 	0,
       
  1277 	0,
       
  1278 	NWayAdvert,
       
  1279 	NWayLPAR,
       
  1280 	NWayExpansion,
       
  1281 	0
       
  1282 };
       
  1283 
       
  1284 
       
  1285 #ifdef CONFIG_8139TOO_8129
       
  1286 /* Syncronize the MII management interface by shifting 32 one bits out. */
       
  1287 static void mdio_sync (void __iomem *ioaddr)
       
  1288 {
       
  1289 	int i;
       
  1290 
       
  1291 	for (i = 32; i >= 0; i--) {
       
  1292 		RTL_W8 (Config4, MDIO_WRITE1);
       
  1293 		mdio_delay ();
       
  1294 		RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
       
  1295 		mdio_delay ();
       
  1296 	}
       
  1297 }
       
  1298 #endif
       
  1299 
       
  1300 static int mdio_read (struct net_device *dev, int phy_id, int location)
       
  1301 {
       
  1302 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1303 	int retval = 0;
       
  1304 #ifdef CONFIG_8139TOO_8129
       
  1305 	void __iomem *ioaddr = tp->mmio_addr;
       
  1306 	int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
       
  1307 	int i;
       
  1308 #endif
       
  1309 
       
  1310 	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
       
  1311 		void __iomem *ioaddr = tp->mmio_addr;
       
  1312 		return location < 8 && mii_2_8139_map[location] ?
       
  1313 		    RTL_R16 (mii_2_8139_map[location]) : 0;
       
  1314 	}
       
  1315 
       
  1316 #ifdef CONFIG_8139TOO_8129
       
  1317 	mdio_sync (ioaddr);
       
  1318 	/* Shift the read command bits out. */
       
  1319 	for (i = 15; i >= 0; i--) {
       
  1320 		int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
       
  1321 
       
  1322 		RTL_W8 (Config4, MDIO_DIR | dataval);
       
  1323 		mdio_delay ();
       
  1324 		RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
       
  1325 		mdio_delay ();
       
  1326 	}
       
  1327 
       
  1328 	/* Read the two transition, 16 data, and wire-idle bits. */
       
  1329 	for (i = 19; i > 0; i--) {
       
  1330 		RTL_W8 (Config4, 0);
       
  1331 		mdio_delay ();
       
  1332 		retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
       
  1333 		RTL_W8 (Config4, MDIO_CLK);
       
  1334 		mdio_delay ();
       
  1335 	}
       
  1336 #endif
       
  1337 
       
  1338 	return (retval >> 1) & 0xffff;
       
  1339 }
       
  1340 
       
  1341 
       
  1342 static void mdio_write (struct net_device *dev, int phy_id, int location,
       
  1343 			int value)
       
  1344 {
       
  1345 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1346 #ifdef CONFIG_8139TOO_8129
       
  1347 	void __iomem *ioaddr = tp->mmio_addr;
       
  1348 	int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
       
  1349 	int i;
       
  1350 #endif
       
  1351 
       
  1352 	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
       
  1353 		void __iomem *ioaddr = tp->mmio_addr;
       
  1354 		if (location == 0) {
       
  1355 			RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  1356 			RTL_W16 (BasicModeCtrl, value);
       
  1357 			RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  1358 		} else if (location < 8 && mii_2_8139_map[location])
       
  1359 			RTL_W16 (mii_2_8139_map[location], value);
       
  1360 		return;
       
  1361 	}
       
  1362 
       
  1363 #ifdef CONFIG_8139TOO_8129
       
  1364 	mdio_sync (ioaddr);
       
  1365 
       
  1366 	/* Shift the command bits out. */
       
  1367 	for (i = 31; i >= 0; i--) {
       
  1368 		int dataval =
       
  1369 		    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
       
  1370 		RTL_W8 (Config4, dataval);
       
  1371 		mdio_delay ();
       
  1372 		RTL_W8 (Config4, dataval | MDIO_CLK);
       
  1373 		mdio_delay ();
       
  1374 	}
       
  1375 	/* Clear out extra bits. */
       
  1376 	for (i = 2; i > 0; i--) {
       
  1377 		RTL_W8 (Config4, 0);
       
  1378 		mdio_delay ();
       
  1379 		RTL_W8 (Config4, MDIO_CLK);
       
  1380 		mdio_delay ();
       
  1381 	}
       
  1382 #endif
       
  1383 }
       
  1384 
       
  1385 
       
  1386 static int rtl8139_open (struct net_device *dev)
       
  1387 {
       
  1388 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1389 	void __iomem *ioaddr = tp->mmio_addr;
       
  1390 	const int irq = tp->pci_dev->irq;
       
  1391 	int retval;
       
  1392 
       
  1393 	if (!tp->ecdev) {
       
  1394 		retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
       
  1395 		if (retval)
       
  1396 			return retval;
       
  1397 	}
       
  1398 
       
  1399 	tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
       
  1400 					   &tp->tx_bufs_dma, GFP_KERNEL);
       
  1401 	tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
       
  1402 					   &tp->rx_ring_dma, GFP_KERNEL);
       
  1403 	if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
       
  1404 		if (!tp->ecdev) {
       
  1405 			free_irq(irq, dev);
       
  1406 		}
       
  1407 
       
  1408 		if (tp->tx_bufs)
       
  1409 			dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
       
  1410 					    tp->tx_bufs, tp->tx_bufs_dma);
       
  1411 		if (tp->rx_ring)
       
  1412 			dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
       
  1413 					    tp->rx_ring, tp->rx_ring_dma);
       
  1414 
       
  1415 		return -ENOMEM;
       
  1416 
       
  1417 	}
       
  1418 
       
  1419 	napi_enable(&tp->napi);
       
  1420 
       
  1421 	tp->mii.full_duplex = tp->mii.force_media;
       
  1422 	tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
       
  1423 
       
  1424 	rtl8139_init_ring (dev);
       
  1425 	rtl8139_hw_start (dev);
       
  1426 	if (!tp->ecdev) {
       
  1427 		netif_start_queue (dev);
       
  1428 	}
       
  1429 
       
  1430 	netif_dbg(tp, ifup, dev,
       
  1431 		  "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
       
  1432 		  __func__,
       
  1433 		  (unsigned long long)pci_resource_start (tp->pci_dev, 1),
       
  1434 		  irq, RTL_R8 (MediaStatus),
       
  1435 		  tp->mii.full_duplex ? "full" : "half");
       
  1436 
       
  1437 	if (!tp->ecdev) {
       
  1438 		rtl8139_start_thread(tp);
       
  1439 	}
       
  1440 
       
  1441 	return 0;
       
  1442 }
       
  1443 
       
  1444 
       
  1445 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
       
  1446 {
       
  1447 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1448 
       
  1449 	if (tp->ecdev) {
       
  1450 		void __iomem *ioaddr = tp->mmio_addr;
       
  1451 		u16 state = RTL_R16(BasicModeStatus) & BMSR_LSTATUS;
       
  1452 		ecdev_set_link(tp->ecdev, state ? 1 : 0);
       
  1453 	}
       
  1454 	else {
       
  1455 		if (tp->phys[0] >= 0) {
       
  1456 			mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
       
  1457 		}
       
  1458 	}
       
  1459 }
       
  1460 
       
  1461 /* Start the hardware at open or resume. */
       
  1462 static void rtl8139_hw_start (struct net_device *dev)
       
  1463 {
       
  1464 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1465 	void __iomem *ioaddr = tp->mmio_addr;
       
  1466 	u32 i;
       
  1467 	u8 tmp;
       
  1468 
       
  1469 	/* Bring old chips out of low-power mode. */
       
  1470 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
       
  1471 		RTL_W8 (HltClk, 'R');
       
  1472 
       
  1473 	rtl8139_chip_reset (ioaddr);
       
  1474 
       
  1475 	/* unlock Config[01234] and BMCR register writes */
       
  1476 	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
       
  1477 	/* Restore our idea of the MAC address. */
       
  1478 	RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
       
  1479 	RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
       
  1480 
       
  1481 	tp->cur_rx = 0;
       
  1482 
       
  1483 	/* init Rx ring buffer DMA address */
       
  1484 	RTL_W32_F (RxBuf, tp->rx_ring_dma);
       
  1485 
       
  1486 	/* Must enable Tx/Rx before setting transfer thresholds! */
       
  1487 	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1488 
       
  1489 	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
       
  1490 	RTL_W32 (RxConfig, tp->rx_config);
       
  1491 	RTL_W32 (TxConfig, rtl8139_tx_config);
       
  1492 
       
  1493 	rtl_check_media (dev, 1);
       
  1494 
       
  1495 	if (tp->chipset >= CH_8139B) {
       
  1496 		/* Disable magic packet scanning, which is enabled
       
  1497 		 * when PM is enabled in Config1.  It can be reenabled
       
  1498 		 * via ETHTOOL_SWOL if desired.  */
       
  1499 		RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
       
  1500 	}
       
  1501 
       
  1502 	netdev_dbg(dev, "init buffer addresses\n");
       
  1503 
       
  1504 	/* Lock Config[01234] and BMCR register writes */
       
  1505 	RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  1506 
       
  1507 	/* init Tx buffer DMA addresses */
       
  1508 	for (i = 0; i < NUM_TX_DESC; i++)
       
  1509 		RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
       
  1510 
       
  1511 	RTL_W32 (RxMissed, 0);
       
  1512 
       
  1513 	rtl8139_set_rx_mode (dev);
       
  1514 
       
  1515 	/* no early-rx interrupts */
       
  1516 	RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
       
  1517 
       
  1518 	/* make sure RxTx has started */
       
  1519 	tmp = RTL_R8 (ChipCmd);
       
  1520 	if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
       
  1521 		RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1522 
       
  1523 	if (!tp->ecdev) {
       
  1524 		/* Enable all known interrupts by setting the interrupt mask. */
       
  1525 		RTL_W16 (IntrMask, rtl8139_intr_mask);
       
  1526 	}
       
  1527 }
       
  1528 
       
  1529 
       
  1530 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
       
  1531 static void rtl8139_init_ring (struct net_device *dev)
       
  1532 {
       
  1533 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1534 	int i;
       
  1535 
       
  1536 	tp->cur_rx = 0;
       
  1537 	tp->cur_tx = 0;
       
  1538 	tp->dirty_tx = 0;
       
  1539 
       
  1540 	for (i = 0; i < NUM_TX_DESC; i++)
       
  1541 		tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
       
  1542 }
       
  1543 
       
  1544 
       
  1545 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
       
  1546 static int next_tick = 3 * HZ;
       
  1547 
       
  1548 #ifndef CONFIG_8139TOO_TUNE_TWISTER
       
  1549 static inline void rtl8139_tune_twister (struct net_device *dev,
       
  1550 				  struct rtl8139_private *tp) {}
       
  1551 #else
       
  1552 enum TwisterParamVals {
       
  1553 	PARA78_default	= 0x78fa8388,
       
  1554 	PARA7c_default	= 0xcb38de43,	/* param[0][3] */
       
  1555 	PARA7c_xxx	= 0xcb38de43,
       
  1556 };
       
  1557 
       
  1558 static const unsigned long param[4][4] = {
       
  1559 	{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
       
  1560 	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
       
  1561 	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
       
  1562 	{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
       
  1563 };
       
  1564 
       
  1565 static void rtl8139_tune_twister (struct net_device *dev,
       
  1566 				  struct rtl8139_private *tp)
       
  1567 {
       
  1568 	int linkcase;
       
  1569 	void __iomem *ioaddr = tp->mmio_addr;
       
  1570 
       
  1571 	/* This is a complicated state machine to configure the "twister" for
       
  1572 	   impedance/echos based on the cable length.
       
  1573 	   All of this is magic and undocumented.
       
  1574 	 */
       
  1575 	switch (tp->twistie) {
       
  1576 	case 1:
       
  1577 		if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
       
  1578 			/* We have link beat, let us tune the twister. */
       
  1579 			RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
       
  1580 			tp->twistie = 2;	/* Change to state 2. */
       
  1581 			next_tick = HZ / 10;
       
  1582 		} else {
       
  1583 			/* Just put in some reasonable defaults for when beat returns. */
       
  1584 			RTL_W16 (CSCR, CSCR_LinkDownCmd);
       
  1585 			RTL_W32 (FIFOTMS, 0x20);	/* Turn on cable test mode. */
       
  1586 			RTL_W32 (PARA78, PARA78_default);
       
  1587 			RTL_W32 (PARA7c, PARA7c_default);
       
  1588 			tp->twistie = 0;	/* Bail from future actions. */
       
  1589 		}
       
  1590 		break;
       
  1591 	case 2:
       
  1592 		/* Read how long it took to hear the echo. */
       
  1593 		linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
       
  1594 		if (linkcase == 0x7000)
       
  1595 			tp->twist_row = 3;
       
  1596 		else if (linkcase == 0x3000)
       
  1597 			tp->twist_row = 2;
       
  1598 		else if (linkcase == 0x1000)
       
  1599 			tp->twist_row = 1;
       
  1600 		else
       
  1601 			tp->twist_row = 0;
       
  1602 		tp->twist_col = 0;
       
  1603 		tp->twistie = 3;	/* Change to state 2. */
       
  1604 		next_tick = HZ / 10;
       
  1605 		break;
       
  1606 	case 3:
       
  1607 		/* Put out four tuning parameters, one per 100msec. */
       
  1608 		if (tp->twist_col == 0)
       
  1609 			RTL_W16 (FIFOTMS, 0);
       
  1610 		RTL_W32 (PARA7c, param[(int) tp->twist_row]
       
  1611 			 [(int) tp->twist_col]);
       
  1612 		next_tick = HZ / 10;
       
  1613 		if (++tp->twist_col >= 4) {
       
  1614 			/* For short cables we are done.
       
  1615 			   For long cables (row == 3) check for mistune. */
       
  1616 			tp->twistie =
       
  1617 			    (tp->twist_row == 3) ? 4 : 0;
       
  1618 		}
       
  1619 		break;
       
  1620 	case 4:
       
  1621 		/* Special case for long cables: check for mistune. */
       
  1622 		if ((RTL_R16 (CSCR) &
       
  1623 		     CSCR_LinkStatusBits) == 0x7000) {
       
  1624 			tp->twistie = 0;
       
  1625 			break;
       
  1626 		} else {
       
  1627 			RTL_W32 (PARA7c, 0xfb38de03);
       
  1628 			tp->twistie = 5;
       
  1629 			next_tick = HZ / 10;
       
  1630 		}
       
  1631 		break;
       
  1632 	case 5:
       
  1633 		/* Retune for shorter cable (column 2). */
       
  1634 		RTL_W32 (FIFOTMS, 0x20);
       
  1635 		RTL_W32 (PARA78, PARA78_default);
       
  1636 		RTL_W32 (PARA7c, PARA7c_default);
       
  1637 		RTL_W32 (FIFOTMS, 0x00);
       
  1638 		tp->twist_row = 2;
       
  1639 		tp->twist_col = 0;
       
  1640 		tp->twistie = 3;
       
  1641 		next_tick = HZ / 10;
       
  1642 		break;
       
  1643 
       
  1644 	default:
       
  1645 		/* do nothing */
       
  1646 		break;
       
  1647 	}
       
  1648 }
       
  1649 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
       
  1650 
       
  1651 static inline void rtl8139_thread_iter (struct net_device *dev,
       
  1652 				 struct rtl8139_private *tp,
       
  1653 				 void __iomem *ioaddr)
       
  1654 {
       
  1655 	int mii_lpa;
       
  1656 
       
  1657 	mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
       
  1658 
       
  1659 	if (!tp->mii.force_media && mii_lpa != 0xffff) {
       
  1660 		int duplex = ((mii_lpa & LPA_100FULL) ||
       
  1661 			      (mii_lpa & 0x01C0) == 0x0040);
       
  1662 		if (tp->mii.full_duplex != duplex) {
       
  1663 			tp->mii.full_duplex = duplex;
       
  1664 
       
  1665 			if (mii_lpa) {
       
  1666 				netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
       
  1667 					    tp->mii.full_duplex ? "full" : "half",
       
  1668 					    tp->phys[0], mii_lpa);
       
  1669 			} else {
       
  1670 				netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
       
  1671 			}
       
  1672 #if 0
       
  1673 			RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  1674 			RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
       
  1675 			RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  1676 #endif
       
  1677 		}
       
  1678 	}
       
  1679 
       
  1680 	next_tick = HZ * 60;
       
  1681 
       
  1682 	rtl8139_tune_twister (dev, tp);
       
  1683 
       
  1684 	netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
       
  1685 		   RTL_R16(NWayLPAR));
       
  1686 	netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
       
  1687 		   RTL_R16(IntrMask), RTL_R16(IntrStatus));
       
  1688 	netdev_dbg(dev, "Chip config %02x %02x\n",
       
  1689 		   RTL_R8(Config0), RTL_R8(Config1));
       
  1690 }
       
  1691 
       
  1692 static void rtl8139_thread (struct work_struct *work)
       
  1693 {
       
  1694 	struct rtl8139_private *tp =
       
  1695 		container_of(work, struct rtl8139_private, thread.work);
       
  1696 	struct net_device *dev = tp->mii.dev;
       
  1697 	unsigned long thr_delay = next_tick;
       
  1698 
       
  1699 	rtnl_lock();
       
  1700 
       
  1701 	if (!netif_running(dev))
       
  1702 		goto out_unlock;
       
  1703 
       
  1704 	if (tp->watchdog_fired) {
       
  1705 		tp->watchdog_fired = 0;
       
  1706 		rtl8139_tx_timeout_task(work);
       
  1707 	} else
       
  1708 		rtl8139_thread_iter(dev, tp, tp->mmio_addr);
       
  1709 
       
  1710 	if (tp->have_thread)
       
  1711 		schedule_delayed_work(&tp->thread, thr_delay);
       
  1712 out_unlock:
       
  1713 	rtnl_unlock ();
       
  1714 }
       
  1715 
       
  1716 static void rtl8139_start_thread(struct rtl8139_private *tp)
       
  1717 {
       
  1718 	tp->twistie = 0;
       
  1719 	if (tp->chipset == CH_8139_K)
       
  1720 		tp->twistie = 1;
       
  1721 	else if (tp->drv_flags & HAS_LNK_CHNG)
       
  1722 		return;
       
  1723 
       
  1724 	tp->have_thread = 1;
       
  1725 	tp->watchdog_fired = 0;
       
  1726 
       
  1727 	schedule_delayed_work(&tp->thread, next_tick);
       
  1728 }
       
  1729 
       
  1730 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
       
  1731 {
       
  1732 	tp->cur_tx = 0;
       
  1733 	tp->dirty_tx = 0;
       
  1734 
       
  1735 	/* XXX account for unsent Tx packets in tp->stats.tx_dropped */
       
  1736 }
       
  1737 
       
  1738 static void rtl8139_tx_timeout_task (struct work_struct *work)
       
  1739 {
       
  1740 	struct rtl8139_private *tp =
       
  1741 		container_of(work, struct rtl8139_private, thread.work);
       
  1742 	struct net_device *dev = tp->mii.dev;
       
  1743 	void __iomem *ioaddr = tp->mmio_addr;
       
  1744 	int i;
       
  1745 	u8 tmp8;
       
  1746 
       
  1747 	netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
       
  1748 		   RTL_R8(ChipCmd), RTL_R16(IntrStatus),
       
  1749 		   RTL_R16(IntrMask), RTL_R8(MediaStatus));
       
  1750 	/* Emit info to figure out what went wrong. */
       
  1751 	netdev_dbg(dev, "Tx queue start entry %ld  dirty entry %ld\n",
       
  1752 		   tp->cur_tx, tp->dirty_tx);
       
  1753 	for (i = 0; i < NUM_TX_DESC; i++)
       
  1754 		netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
       
  1755 			   i, RTL_R32(TxStatus0 + (i * 4)),
       
  1756 			   i == tp->dirty_tx % NUM_TX_DESC ?
       
  1757 			   " (queue head)" : "");
       
  1758 
       
  1759 	tp->xstats.tx_timeouts++;
       
  1760 
       
  1761 	/* disable Tx ASAP, if not already */
       
  1762 	tmp8 = RTL_R8 (ChipCmd);
       
  1763 	if (tmp8 & CmdTxEnb)
       
  1764 		RTL_W8 (ChipCmd, CmdRxEnb);
       
  1765 
       
  1766 	if (tp->ecdev) {
       
  1767 		rtl8139_tx_clear (tp);
       
  1768 		rtl8139_hw_start (dev);
       
  1769 	}
       
  1770 	else {
       
  1771 		spin_lock_bh(&tp->rx_lock);
       
  1772 
       
  1773 		/* Disable interrupts by clearing the interrupt mask. */
       
  1774 		RTL_W16 (IntrMask, 0x0000);
       
  1775 
       
  1776 		/* Stop a shared interrupt from scavenging while we are. */
       
  1777 		spin_lock_irq(&tp->lock);
       
  1778 		rtl8139_tx_clear (tp);
       
  1779 		spin_unlock_irq(&tp->lock);
       
  1780 
       
  1781 		/* ...and finally, reset everything */
       
  1782 		if (netif_running(dev)) {
       
  1783 			rtl8139_hw_start (dev);
       
  1784 			netif_wake_queue (dev);
       
  1785 		}
       
  1786 
       
  1787 		spin_unlock_bh(&tp->rx_lock);
       
  1788 	}
       
  1789 }
       
  1790 
       
  1791 static void rtl8139_tx_timeout (struct net_device *dev)
       
  1792 {
       
  1793 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1794 
       
  1795 	tp->watchdog_fired = 1;
       
  1796 	if (!tp->ecdev && !tp->have_thread) {
       
  1797 		INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
       
  1798 		schedule_delayed_work(&tp->thread, next_tick);
       
  1799 	}
       
  1800 }
       
  1801 
       
  1802 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
       
  1803 					     struct net_device *dev)
       
  1804 {
       
  1805 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1806 	void __iomem *ioaddr = tp->mmio_addr;
       
  1807 	unsigned int entry;
       
  1808 	unsigned int len = skb->len;
       
  1809 	unsigned long flags = 0;
       
  1810 
       
  1811 	/* Calculate the next Tx descriptor entry. */
       
  1812 	entry = tp->cur_tx % NUM_TX_DESC;
       
  1813 
       
  1814 	/* Note: the chip doesn't have auto-pad! */
       
  1815 	if (likely(len < TX_BUF_SIZE)) {
       
  1816 		if (len < ETH_ZLEN)
       
  1817 			memset(tp->tx_buf[entry], 0, ETH_ZLEN);
       
  1818 		skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
       
  1819 		if (!tp->ecdev) {
       
  1820 			dev_kfree_skb(skb);
       
  1821 		}
       
  1822 	} else {
       
  1823 		if (!tp->ecdev) {
       
  1824 			dev_kfree_skb(skb);
       
  1825 		}
       
  1826 		dev->stats.tx_dropped++;
       
  1827 		return NETDEV_TX_OK;
       
  1828 	}
       
  1829 
       
  1830 	if (!tp->ecdev) {
       
  1831 		spin_lock_irqsave(&tp->lock, flags);
       
  1832 	}
       
  1833 	/*
       
  1834 	 * Writing to TxStatus triggers a DMA transfer of the data
       
  1835 	 * copied to tp->tx_buf[entry] above. Use a memory barrier
       
  1836 	 * to make sure that the device sees the updated data.
       
  1837 	 */
       
  1838 	wmb();
       
  1839 	RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
       
  1840 		   tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
       
  1841 
       
  1842 	tp->cur_tx++;
       
  1843 
       
  1844 	if (!tp->ecdev) {
       
  1845 		if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
       
  1846 			netif_stop_queue (dev);
       
  1847 		spin_unlock_irqrestore(&tp->lock, flags);
       
  1848 	}
       
  1849 
       
  1850 	netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
       
  1851 		  len, entry);
       
  1852 
       
  1853 	return NETDEV_TX_OK;
       
  1854 }
       
  1855 
       
  1856 
       
  1857 static void rtl8139_tx_interrupt (struct net_device *dev,
       
  1858 				  struct rtl8139_private *tp,
       
  1859 				  void __iomem *ioaddr)
       
  1860 {
       
  1861 	unsigned long dirty_tx, tx_left;
       
  1862 
       
  1863 	assert (dev != NULL);
       
  1864 	assert (ioaddr != NULL);
       
  1865 
       
  1866 	dirty_tx = tp->dirty_tx;
       
  1867 	tx_left = tp->cur_tx - dirty_tx;
       
  1868 	while (tx_left > 0) {
       
  1869 		int entry = dirty_tx % NUM_TX_DESC;
       
  1870 		int txstatus;
       
  1871 
       
  1872 		txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
       
  1873 
       
  1874 		if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
       
  1875 			break;	/* It still hasn't been Txed */
       
  1876 
       
  1877 		/* Note: TxCarrierLost is always asserted at 100mbps. */
       
  1878 		if (txstatus & (TxOutOfWindow | TxAborted)) {
       
  1879 			/* There was an major error, log it. */
       
  1880 			netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
       
  1881 				  txstatus);
       
  1882 			dev->stats.tx_errors++;
       
  1883 			if (txstatus & TxAborted) {
       
  1884 				dev->stats.tx_aborted_errors++;
       
  1885 				RTL_W32 (TxConfig, TxClearAbt);
       
  1886 				RTL_W16 (IntrStatus, TxErr);
       
  1887 				wmb();
       
  1888 			}
       
  1889 			if (txstatus & TxCarrierLost)
       
  1890 				dev->stats.tx_carrier_errors++;
       
  1891 			if (txstatus & TxOutOfWindow)
       
  1892 				dev->stats.tx_window_errors++;
       
  1893 		} else {
       
  1894 			if (txstatus & TxUnderrun) {
       
  1895 				/* Add 64 to the Tx FIFO threshold. */
       
  1896 				if (tp->tx_flag < 0x00300000)
       
  1897 					tp->tx_flag += 0x00020000;
       
  1898 				dev->stats.tx_fifo_errors++;
       
  1899 			}
       
  1900 			dev->stats.collisions += (txstatus >> 24) & 15;
       
  1901 			u64_stats_update_begin(&tp->tx_stats.syncp);
       
  1902 			tp->tx_stats.packets++;
       
  1903 			tp->tx_stats.bytes += txstatus & 0x7ff;
       
  1904 			u64_stats_update_end(&tp->tx_stats.syncp);
       
  1905 		}
       
  1906 
       
  1907 		dirty_tx++;
       
  1908 		tx_left--;
       
  1909 	}
       
  1910 
       
  1911 #ifndef RTL8139_NDEBUG
       
  1912 	if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
       
  1913 		pr_err("%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
       
  1914 		        dev->name, dirty_tx, tp->cur_tx);
       
  1915 		dirty_tx += NUM_TX_DESC;
       
  1916 	}
       
  1917 #endif /* RTL8139_NDEBUG */
       
  1918 
       
  1919 	/* only wake the queue if we did work, and the queue is stopped */
       
  1920 	if (tp->dirty_tx != dirty_tx) {
       
  1921 		tp->dirty_tx = dirty_tx;
       
  1922 		mb();
       
  1923 		if (!tp->ecdev) {
       
  1924 			netif_wake_queue (dev);
       
  1925 		}
       
  1926 	}
       
  1927 }
       
  1928 
       
  1929 
       
  1930 /* TODO: clean this up!  Rx reset need not be this intensive */
       
  1931 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
       
  1932 			    struct rtl8139_private *tp, void __iomem *ioaddr)
       
  1933 {
       
  1934 	u8 tmp8;
       
  1935 #ifdef CONFIG_8139_OLD_RX_RESET
       
  1936 	int tmp_work;
       
  1937 #endif
       
  1938 
       
  1939 	if (netif_msg_rx_err (tp))
       
  1940 		pr_debug("%s: Ethernet frame had errors, status %8.8x.\n",
       
  1941 			dev->name, rx_status);
       
  1942 	dev->stats.rx_errors++;
       
  1943 	if (!(rx_status & RxStatusOK)) {
       
  1944 		if (rx_status & RxTooLong) {
       
  1945 			pr_debug("%s: Oversized Ethernet frame, status %4.4x!\n",
       
  1946 			 	dev->name, rx_status);
       
  1947 			/* A.C.: The chip hangs here. */
       
  1948 		}
       
  1949 		if (rx_status & (RxBadSymbol | RxBadAlign))
       
  1950 			dev->stats.rx_frame_errors++;
       
  1951 		if (rx_status & (RxRunt | RxTooLong))
       
  1952 			dev->stats.rx_length_errors++;
       
  1953 		if (rx_status & RxCRCErr)
       
  1954 			dev->stats.rx_crc_errors++;
       
  1955 	} else {
       
  1956 		tp->xstats.rx_lost_in_ring++;
       
  1957 	}
       
  1958 
       
  1959 #ifndef CONFIG_8139_OLD_RX_RESET
       
  1960 	tmp8 = RTL_R8 (ChipCmd);
       
  1961 	RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
       
  1962 	RTL_W8 (ChipCmd, tmp8);
       
  1963 	RTL_W32 (RxConfig, tp->rx_config);
       
  1964 	tp->cur_rx = 0;
       
  1965 #else
       
  1966 	/* Reset the receiver, based on RealTek recommendation. (Bug?) */
       
  1967 
       
  1968 	/* disable receive */
       
  1969 	RTL_W8_F (ChipCmd, CmdTxEnb);
       
  1970 	tmp_work = 200;
       
  1971 	while (--tmp_work > 0) {
       
  1972 		udelay(1);
       
  1973 		tmp8 = RTL_R8 (ChipCmd);
       
  1974 		if (!(tmp8 & CmdRxEnb))
       
  1975 			break;
       
  1976 	}
       
  1977 	if (tmp_work <= 0)
       
  1978 		pr_warning(PFX "rx stop wait too long\n");
       
  1979 	/* restart receive */
       
  1980 	tmp_work = 200;
       
  1981 	while (--tmp_work > 0) {
       
  1982 		RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1983 		udelay(1);
       
  1984 		tmp8 = RTL_R8 (ChipCmd);
       
  1985 		if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
       
  1986 			break;
       
  1987 	}
       
  1988 	if (tmp_work <= 0)
       
  1989 		pr_warning(PFX "tx/rx enable wait too long\n");
       
  1990 
       
  1991 	/* and reinitialize all rx related registers */
       
  1992 	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
       
  1993 	/* Must enable Tx/Rx before setting transfer thresholds! */
       
  1994 	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1995 
       
  1996 	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
       
  1997 	RTL_W32 (RxConfig, tp->rx_config);
       
  1998 	tp->cur_rx = 0;
       
  1999 
       
  2000 	pr_debug("init buffer addresses\n");
       
  2001 
       
  2002 	/* Lock Config[01234] and BMCR register writes */
       
  2003 	RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  2004 
       
  2005 	/* init Rx ring buffer DMA address */
       
  2006 	RTL_W32_F (RxBuf, tp->rx_ring_dma);
       
  2007 
       
  2008 	/* A.C.: Reset the multicast list. */
       
  2009 	__set_rx_mode (dev);
       
  2010 #endif
       
  2011 }
       
  2012 
       
  2013 #if RX_BUF_IDX == 3
       
  2014 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
       
  2015 				 u32 offset, unsigned int size)
       
  2016 {
       
  2017 	u32 left = RX_BUF_LEN - offset;
       
  2018 
       
  2019 	if (size > left) {
       
  2020 		skb_copy_to_linear_data(skb, ring + offset, left);
       
  2021 		skb_copy_to_linear_data_offset(skb, left, ring, size - left);
       
  2022 	} else
       
  2023 		skb_copy_to_linear_data(skb, ring + offset, size);
       
  2024 }
       
  2025 #endif
       
  2026 
       
  2027 static void rtl8139_isr_ack(struct rtl8139_private *tp)
       
  2028 {
       
  2029 	void __iomem *ioaddr = tp->mmio_addr;
       
  2030 	u16 status;
       
  2031 
       
  2032 	status = RTL_R16 (IntrStatus) & RxAckBits;
       
  2033 
       
  2034 	/* Clear out errors and receive interrupts */
       
  2035 	if (likely(status != 0)) {
       
  2036 		if (unlikely(status & (RxFIFOOver | RxOverflow))) {
       
  2037 			tp->dev->stats.rx_errors++;
       
  2038 			if (status & RxFIFOOver)
       
  2039 				tp->dev->stats.rx_fifo_errors++;
       
  2040 		}
       
  2041 		RTL_W16_F (IntrStatus, RxAckBits);
       
  2042 	}
       
  2043 }
       
  2044 
       
  2045 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
       
  2046 		      int budget)
       
  2047 {
       
  2048 	void __iomem *ioaddr = tp->mmio_addr;
       
  2049 	int received = 0;
       
  2050 	unsigned char *rx_ring = tp->rx_ring;
       
  2051 	unsigned int cur_rx = tp->cur_rx;
       
  2052 	unsigned int rx_size = 0;
       
  2053 
       
  2054 	pr_debug("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
       
  2055 		 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
       
  2056 		 RTL_R16 (RxBufAddr),
       
  2057 		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
       
  2058 
       
  2059 	while ((tp->ecdev || netif_running(dev))
       
  2060 			&& received < budget
       
  2061 			&& (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
       
  2062 		u32 ring_offset = cur_rx % RX_BUF_LEN;
       
  2063 		u32 rx_status;
       
  2064 		unsigned int pkt_size;
       
  2065 		struct sk_buff *skb;
       
  2066 
       
  2067 		rmb();
       
  2068 
       
  2069 		/* read size+status of next frame from DMA ring buffer */
       
  2070 		rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
       
  2071 		rx_size = rx_status >> 16;
       
  2072 		if (likely(!(dev->features & NETIF_F_RXFCS)))
       
  2073 			pkt_size = rx_size - 4;
       
  2074 		else
       
  2075 			pkt_size = rx_size;
       
  2076 
       
  2077 		if (!tp->ecdev) {
       
  2078 			if (netif_msg_rx_status(tp))
       
  2079 				pr_debug("%s:  rtl8139_rx() status %4.4x, size %4.4x,"
       
  2080 					" cur %4.4x.\n", dev->name, rx_status,
       
  2081 				 rx_size, cur_rx);
       
  2082 		}
       
  2083 #if RTL8139_DEBUG > 2
       
  2084 		{
       
  2085 			int i;
       
  2086 			pr_debug("%s: Frame contents ", dev->name);
       
  2087 			for (i = 0; i < 70; i++)
       
  2088 				pr_cont(" %2.2x",
       
  2089 					rx_ring[ring_offset + i]);
       
  2090 			pr_cont(".\n");
       
  2091 		}
       
  2092 #endif
       
  2093 
       
  2094 		/* Packet copy from FIFO still in progress.
       
  2095 		 * Theoretically, this should never happen
       
  2096 		 * since EarlyRx is disabled.
       
  2097 		 */
       
  2098 		if (unlikely(rx_size == 0xfff0)) {
       
  2099 			if (!tp->fifo_copy_timeout)
       
  2100 				tp->fifo_copy_timeout = jiffies + 2;
       
  2101 			else if (time_after(jiffies, tp->fifo_copy_timeout)) {
       
  2102 				pr_debug("%s: hung FIFO. Reset.", dev->name);
       
  2103 				rx_size = 0;
       
  2104 				goto no_early_rx;
       
  2105 			}
       
  2106 			if (netif_msg_intr(tp)) {
       
  2107 				pr_debug("%s: fifo copy in progress.",
       
  2108 				       dev->name);
       
  2109 			}
       
  2110 			tp->xstats.early_rx++;
       
  2111 			break;
       
  2112 		}
       
  2113 
       
  2114 no_early_rx:
       
  2115 		tp->fifo_copy_timeout = 0;
       
  2116 
       
  2117 		/* If Rx err or invalid rx_size/rx_status received
       
  2118 		 * (which happens if we get lost in the ring),
       
  2119 		 * Rx process gets reset, so we abort any further
       
  2120 		 * Rx processing.
       
  2121 		 */
       
  2122 		if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
       
  2123 			     (rx_size < 8) ||
       
  2124 			     (!(rx_status & RxStatusOK)))) {
       
  2125 			if ((dev->features & NETIF_F_RXALL) &&
       
  2126 			    (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
       
  2127 			    (rx_size >= 8) &&
       
  2128 			    (!(rx_status & RxStatusOK))) {
       
  2129 				/* Length is at least mostly OK, but pkt has
       
  2130 				 * error.  I'm hoping we can handle some of these
       
  2131 				 * errors without resetting the chip. --Ben
       
  2132 				 */
       
  2133 				dev->stats.rx_errors++;
       
  2134 				if (rx_status & RxCRCErr) {
       
  2135 					dev->stats.rx_crc_errors++;
       
  2136 					goto keep_pkt;
       
  2137 				}
       
  2138 				if (rx_status & RxRunt) {
       
  2139 					dev->stats.rx_length_errors++;
       
  2140 					goto keep_pkt;
       
  2141 				}
       
  2142 			}
       
  2143 			rtl8139_rx_err (rx_status, dev, tp, ioaddr);
       
  2144 			received = -1;
       
  2145 			goto out;
       
  2146 		}
       
  2147 
       
  2148 keep_pkt:
       
  2149 		/* Malloc up new buffer, compatible with net-2e. */
       
  2150 		/* Omit the four octet CRC from the length. */
       
  2151 
       
  2152 		if (tp->ecdev) {
       
  2153 			ecdev_receive(tp->ecdev,
       
  2154 					&rx_ring[ring_offset + 4], pkt_size);
       
  2155 					dev->last_rx = jiffies;
       
  2156 					dev->stats.rx_bytes += pkt_size;
       
  2157 					dev->stats.rx_packets++;
       
  2158 		}
       
  2159 		else {
       
  2160 			skb = netdev_alloc_skb_ip_align(dev, pkt_size);
       
  2161 			if (likely(skb)) {
       
  2162 #if RX_BUF_IDX == 3
       
  2163 				wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
       
  2164 #else
       
  2165 				skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4],
       
  2166 						pkt_size);
       
  2167 #endif
       
  2168 				skb_put (skb, pkt_size);
       
  2169 
       
  2170 				skb->protocol = eth_type_trans (skb, dev);
       
  2171 
       
  2172 				u64_stats_update_begin(&tp->rx_stats.syncp);
       
  2173 				tp->rx_stats.packets++;
       
  2174 				tp->rx_stats.bytes += pkt_size;
       
  2175 				u64_stats_update_end(&tp->rx_stats.syncp);
       
  2176 
       
  2177 				netif_receive_skb (skb);
       
  2178 			} else {
       
  2179 				dev->stats.rx_dropped++;
       
  2180 			}
       
  2181 		}
       
  2182 		received++;
       
  2183 
       
  2184 		cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
       
  2185 		RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
       
  2186 
       
  2187 		rtl8139_isr_ack(tp);
       
  2188 	}
       
  2189 
       
  2190 	if (unlikely(!received || rx_size == 0xfff0))
       
  2191 		rtl8139_isr_ack(tp);
       
  2192 
       
  2193 	pr_debug("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
       
  2194 		 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
       
  2195 		 RTL_R16 (RxBufAddr),
       
  2196 		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
       
  2197 
       
  2198 	tp->cur_rx = cur_rx;
       
  2199 
       
  2200 	/*
       
  2201 	 * The receive buffer should be mostly empty.
       
  2202 	 * Tell NAPI to reenable the Rx irq.
       
  2203 	 */
       
  2204 	if (tp->fifo_copy_timeout)
       
  2205 		received = budget;
       
  2206 
       
  2207 out:
       
  2208 	return received;
       
  2209 }
       
  2210 
       
  2211 
       
  2212 static void rtl8139_weird_interrupt (struct net_device *dev,
       
  2213 				     struct rtl8139_private *tp,
       
  2214 				     void __iomem *ioaddr,
       
  2215 				     int status, int link_changed)
       
  2216 {
       
  2217 	pr_debug("%s: Abnormal interrupt, status %8.8x.\n",
       
  2218 		 dev->name, status);
       
  2219 
       
  2220 	assert (dev != NULL);
       
  2221 	assert (tp != NULL);
       
  2222 	assert (ioaddr != NULL);
       
  2223 
       
  2224 	/* Update the error count. */
       
  2225 	dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2226 	RTL_W32 (RxMissed, 0);
       
  2227 
       
  2228 	if ((status & RxUnderrun) && link_changed &&
       
  2229 	    (tp->drv_flags & HAS_LNK_CHNG)) {
       
  2230 		rtl_check_media(dev, 0);
       
  2231 		status &= ~RxUnderrun;
       
  2232 	}
       
  2233 
       
  2234 	if (status & (RxUnderrun | RxErr))
       
  2235 		dev->stats.rx_errors++;
       
  2236 
       
  2237 	if (status & PCSTimeout)
       
  2238 		dev->stats.rx_length_errors++;
       
  2239 	if (status & RxUnderrun)
       
  2240 		dev->stats.rx_fifo_errors++;
       
  2241 	if (status & PCIErr) {
       
  2242 		u16 pci_cmd_status;
       
  2243 		pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
       
  2244 		pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
       
  2245 
       
  2246 		pr_err("%s: PCI Bus error %4.4x.\n",
       
  2247 			dev->name, pci_cmd_status);
       
  2248 	}
       
  2249 }
       
  2250 
       
  2251 static int rtl8139_poll(struct napi_struct *napi, int budget)
       
  2252 {
       
  2253 	struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
       
  2254 	struct net_device *dev = tp->dev;
       
  2255 	void __iomem *ioaddr = tp->mmio_addr;
       
  2256 	int work_done;
       
  2257 
       
  2258 	spin_lock(&tp->rx_lock);
       
  2259 	work_done = 0;
       
  2260 	if (likely(RTL_R16(IntrStatus) & RxAckBits))
       
  2261 		work_done += rtl8139_rx(dev, tp, budget);
       
  2262 
       
  2263 	if (work_done < budget) {
       
  2264 		unsigned long flags;
       
  2265 		/*
       
  2266 		 * Order is important since data can get interrupted
       
  2267 		 * again when we think we are done.
       
  2268 		 */
       
  2269 		spin_lock_irqsave(&tp->lock, flags);
       
  2270 		__napi_complete(napi);
       
  2271 		RTL_W16_F(IntrMask, rtl8139_intr_mask);
       
  2272 		spin_unlock_irqrestore(&tp->lock, flags);
       
  2273 	}
       
  2274 	spin_unlock(&tp->rx_lock);
       
  2275 
       
  2276 	return work_done;
       
  2277 }
       
  2278 
       
  2279 void ec_poll(struct net_device *dev)
       
  2280 {
       
  2281 	rtl8139_interrupt(0, dev);
       
  2282 }
       
  2283 
       
  2284 /* The interrupt handler does all of the Rx thread work and cleans up
       
  2285    after the Tx thread. */
       
  2286 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
       
  2287 {
       
  2288 	struct net_device *dev = (struct net_device *) dev_instance;
       
  2289 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2290 	void __iomem *ioaddr = tp->mmio_addr;
       
  2291 	u16 status, ackstat;
       
  2292 	int link_changed = 0; /* avoid bogus "uninit" warning */
       
  2293 	int handled = 0;
       
  2294 
       
  2295 	if (tp->ecdev) {
       
  2296 		status = RTL_R16 (IntrStatus);
       
  2297 	}
       
  2298 	else {
       
  2299 		spin_lock (&tp->lock);
       
  2300 		status = RTL_R16 (IntrStatus);
       
  2301 
       
  2302 		/* shared irq? */
       
  2303 		if (unlikely((status & rtl8139_intr_mask) == 0))
       
  2304 			goto out;
       
  2305 	}
       
  2306 
       
  2307 	handled = 1;
       
  2308 
       
  2309 	/* h/w no longer present (hotplug?) or major error, bail */
       
  2310 	if (unlikely(status == 0xFFFF))
       
  2311 		goto out;
       
  2312 
       
  2313 	if (!tp->ecdev) {
       
  2314 		/* close possible race's with dev_close */
       
  2315 		if (unlikely(!netif_running(dev))) {
       
  2316 			RTL_W16 (IntrMask, 0);
       
  2317 			goto out;
       
  2318 		}
       
  2319 	}
       
  2320 
       
  2321 	/* Acknowledge all of the current interrupt sources ASAP, but
       
  2322 	   an first get an additional status bit from CSCR. */
       
  2323 	if (unlikely(status & RxUnderrun))
       
  2324 		link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
       
  2325 
       
  2326 	ackstat = status & ~(RxAckBits | TxErr);
       
  2327 	if (ackstat)
       
  2328 		RTL_W16 (IntrStatus, ackstat);
       
  2329 
       
  2330 	/* Receive packets are processed by poll routine.
       
  2331 	   If not running start it now. */
       
  2332 	if (status & RxAckBits){
       
  2333 		if (tp->ecdev) {
       
  2334 			/* EtherCAT device: Just receive all frames */
       
  2335 			rtl8139_rx(dev, tp, 100); // FIXME
       
  2336 		} else {
       
  2337 			/* Mark for polling */
       
  2338 			if (napi_schedule_prep(&tp->napi)) {
       
  2339 				RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
       
  2340 				__napi_schedule(&tp->napi);
       
  2341 			}
       
  2342 		}
       
  2343 	}
       
  2344 
       
  2345 	/* Check uncommon events with one test. */
       
  2346 	if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
       
  2347 		rtl8139_weird_interrupt (dev, tp, ioaddr,
       
  2348 					 status, link_changed);
       
  2349 
       
  2350 	if (status & (TxOK | TxErr)) {
       
  2351 		rtl8139_tx_interrupt (dev, tp, ioaddr);
       
  2352 		if (status & TxErr)
       
  2353 			RTL_W16 (IntrStatus, TxErr);
       
  2354 	}
       
  2355 out:
       
  2356 	if (!tp->ecdev) {
       
  2357 		spin_unlock (&tp->lock);
       
  2358 	}
       
  2359 
       
  2360 	pr_debug("%s: exiting interrupt, intr_status=%#4.4x.\n",
       
  2361 		 dev->name, RTL_R16 (IntrStatus));
       
  2362 	return IRQ_RETVAL(handled);
       
  2363 }
       
  2364 
       
  2365 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  2366 /*
       
  2367  * Polling receive - used by netconsole and other diagnostic tools
       
  2368  * to allow network i/o with interrupts disabled.
       
  2369  */
       
  2370 static void rtl8139_poll_controller(struct net_device *dev)
       
  2371 {
       
  2372 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2373 	const int irq = tp->pci_dev->irq;
       
  2374 
       
  2375 	disable_irq(irq);
       
  2376 	rtl8139_interrupt(irq, dev);
       
  2377 	enable_irq(irq);
       
  2378 }
       
  2379 #endif
       
  2380 
       
  2381 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
       
  2382 {
       
  2383 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2384 	void __iomem *ioaddr = tp->mmio_addr;
       
  2385 	struct sockaddr *addr = p;
       
  2386 
       
  2387 	if (!is_valid_ether_addr(addr->sa_data))
       
  2388 		return -EADDRNOTAVAIL;
       
  2389 
       
  2390 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
       
  2391 
       
  2392 	spin_lock_irq(&tp->lock);
       
  2393 
       
  2394 	RTL_W8_F(Cfg9346, Cfg9346_Unlock);
       
  2395 	RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
       
  2396 	RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
       
  2397 	RTL_W8_F(Cfg9346, Cfg9346_Lock);
       
  2398 
       
  2399 	spin_unlock_irq(&tp->lock);
       
  2400 
       
  2401 	return 0;
       
  2402 }
       
  2403 
       
  2404 static int rtl8139_close (struct net_device *dev)
       
  2405 {
       
  2406 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2407 	void __iomem *ioaddr = tp->mmio_addr;
       
  2408 	unsigned long flags = 0;
       
  2409 
       
  2410 	if (!tp->ecdev) {
       
  2411 		netif_stop_queue(dev);
       
  2412 		napi_disable(&tp->napi);
       
  2413 
       
  2414 		netif_dbg(tp, ifdown, dev,
       
  2415 				"Shutting down ethercard, status was 0x%04x\n",
       
  2416 				RTL_R16(IntrStatus));
       
  2417 
       
  2418 		spin_lock_irqsave (&tp->lock, flags);
       
  2419 	}
       
  2420 
       
  2421 	/* Stop the chip's Tx and Rx DMA processes. */
       
  2422 	RTL_W8 (ChipCmd, 0);
       
  2423 
       
  2424 	/* Disable interrupts by clearing the interrupt mask. */
       
  2425 	RTL_W16 (IntrMask, 0);
       
  2426 
       
  2427 	/* Update the error counts. */
       
  2428 	dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2429 	RTL_W32 (RxMissed, 0);
       
  2430 
       
  2431 	if (!tp->ecdev) {
       
  2432 		spin_unlock_irqrestore (&tp->lock, flags);
       
  2433 
       
  2434 		free_irq(tp->pci_dev->irq, dev);
       
  2435 	}
       
  2436 
       
  2437 	rtl8139_tx_clear (tp);
       
  2438 
       
  2439 	dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
       
  2440 			  tp->rx_ring, tp->rx_ring_dma);
       
  2441 	dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
       
  2442 			  tp->tx_bufs, tp->tx_bufs_dma);
       
  2443 	tp->rx_ring = NULL;
       
  2444 	tp->tx_bufs = NULL;
       
  2445 
       
  2446 	/* Green! Put the chip in low-power mode. */
       
  2447 	RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  2448 
       
  2449 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
       
  2450 		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
       
  2451 
       
  2452 	return 0;
       
  2453 }
       
  2454 
       
  2455 
       
  2456 /* Get the ethtool Wake-on-LAN settings.  Assumes that wol points to
       
  2457    kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
       
  2458    other threads or interrupts aren't messing with the 8139.  */
       
  2459 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
  2460 {
       
  2461 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2462 	void __iomem *ioaddr = tp->mmio_addr;
       
  2463 
       
  2464 	spin_lock_irq(&tp->lock);
       
  2465 	if (rtl_chip_info[tp->chipset].flags & HasLWake) {
       
  2466 		u8 cfg3 = RTL_R8 (Config3);
       
  2467 		u8 cfg5 = RTL_R8 (Config5);
       
  2468 
       
  2469 		wol->supported = WAKE_PHY | WAKE_MAGIC
       
  2470 			| WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
       
  2471 
       
  2472 		wol->wolopts = 0;
       
  2473 		if (cfg3 & Cfg3_LinkUp)
       
  2474 			wol->wolopts |= WAKE_PHY;
       
  2475 		if (cfg3 & Cfg3_Magic)
       
  2476 			wol->wolopts |= WAKE_MAGIC;
       
  2477 		/* (KON)FIXME: See how netdev_set_wol() handles the
       
  2478 		   following constants.  */
       
  2479 		if (cfg5 & Cfg5_UWF)
       
  2480 			wol->wolopts |= WAKE_UCAST;
       
  2481 		if (cfg5 & Cfg5_MWF)
       
  2482 			wol->wolopts |= WAKE_MCAST;
       
  2483 		if (cfg5 & Cfg5_BWF)
       
  2484 			wol->wolopts |= WAKE_BCAST;
       
  2485 	}
       
  2486 	spin_unlock_irq(&tp->lock);
       
  2487 }
       
  2488 
       
  2489 
       
  2490 /* Set the ethtool Wake-on-LAN settings.  Return 0 or -errno.  Assumes
       
  2491    that wol points to kernel memory and other threads or interrupts
       
  2492    aren't messing with the 8139.  */
       
  2493 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
  2494 {
       
  2495 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2496 	void __iomem *ioaddr = tp->mmio_addr;
       
  2497 	u32 support;
       
  2498 	u8 cfg3, cfg5;
       
  2499 
       
  2500 	support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
       
  2501 		   ? (WAKE_PHY | WAKE_MAGIC
       
  2502 		      | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
       
  2503 		   : 0);
       
  2504 	if (wol->wolopts & ~support)
       
  2505 		return -EINVAL;
       
  2506 
       
  2507 	spin_lock_irq(&tp->lock);
       
  2508 	cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
       
  2509 	if (wol->wolopts & WAKE_PHY)
       
  2510 		cfg3 |= Cfg3_LinkUp;
       
  2511 	if (wol->wolopts & WAKE_MAGIC)
       
  2512 		cfg3 |= Cfg3_Magic;
       
  2513 	RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  2514 	RTL_W8 (Config3, cfg3);
       
  2515 	RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  2516 
       
  2517 	cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
       
  2518 	/* (KON)FIXME: These are untested.  We may have to set the
       
  2519 	   CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
       
  2520 	   documentation.  */
       
  2521 	if (wol->wolopts & WAKE_UCAST)
       
  2522 		cfg5 |= Cfg5_UWF;
       
  2523 	if (wol->wolopts & WAKE_MCAST)
       
  2524 		cfg5 |= Cfg5_MWF;
       
  2525 	if (wol->wolopts & WAKE_BCAST)
       
  2526 		cfg5 |= Cfg5_BWF;
       
  2527 	RTL_W8 (Config5, cfg5);	/* need not unlock via Cfg9346 */
       
  2528 	spin_unlock_irq(&tp->lock);
       
  2529 
       
  2530 	return 0;
       
  2531 }
       
  2532 
       
  2533 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
       
  2534 {
       
  2535 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2536 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
       
  2537 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
       
  2538 	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
       
  2539 	info->regdump_len = tp->regs_len;
       
  2540 }
       
  2541 
       
  2542 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  2543 {
       
  2544 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2545 	spin_lock_irq(&tp->lock);
       
  2546 	mii_ethtool_gset(&tp->mii, cmd);
       
  2547 	spin_unlock_irq(&tp->lock);
       
  2548 	return 0;
       
  2549 }
       
  2550 
       
  2551 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  2552 {
       
  2553 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2554 	int rc;
       
  2555 	spin_lock_irq(&tp->lock);
       
  2556 	rc = mii_ethtool_sset(&tp->mii, cmd);
       
  2557 	spin_unlock_irq(&tp->lock);
       
  2558 	return rc;
       
  2559 }
       
  2560 
       
  2561 static int rtl8139_nway_reset(struct net_device *dev)
       
  2562 {
       
  2563 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2564 	return mii_nway_restart(&tp->mii);
       
  2565 }
       
  2566 
       
  2567 static u32 rtl8139_get_link(struct net_device *dev)
       
  2568 {
       
  2569 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2570 	return mii_link_ok(&tp->mii);
       
  2571 }
       
  2572 
       
  2573 static u32 rtl8139_get_msglevel(struct net_device *dev)
       
  2574 {
       
  2575 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2576 	return tp->msg_enable;
       
  2577 }
       
  2578 
       
  2579 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
       
  2580 {
       
  2581 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2582 	tp->msg_enable = datum;
       
  2583 }
       
  2584 
       
  2585 static int rtl8139_get_regs_len(struct net_device *dev)
       
  2586 {
       
  2587 	struct rtl8139_private *tp;
       
  2588 	/* TODO: we are too slack to do reg dumping for pio, for now */
       
  2589 	if (use_io)
       
  2590 		return 0;
       
  2591 	tp = netdev_priv(dev);
       
  2592 	return tp->regs_len;
       
  2593 }
       
  2594 
       
  2595 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
       
  2596 {
       
  2597 	struct rtl8139_private *tp;
       
  2598 
       
  2599 	/* TODO: we are too slack to do reg dumping for pio, for now */
       
  2600 	if (use_io)
       
  2601 		return;
       
  2602 	tp = netdev_priv(dev);
       
  2603 
       
  2604 	regs->version = RTL_REGS_VER;
       
  2605 
       
  2606 	spin_lock_irq(&tp->lock);
       
  2607 	memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
       
  2608 	spin_unlock_irq(&tp->lock);
       
  2609 }
       
  2610 
       
  2611 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
       
  2612 {
       
  2613 	switch (sset) {
       
  2614 	case ETH_SS_STATS:
       
  2615 		return RTL_NUM_STATS;
       
  2616 	default:
       
  2617 		return -EOPNOTSUPP;
       
  2618 	}
       
  2619 }
       
  2620 
       
  2621 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
       
  2622 {
       
  2623 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2624 
       
  2625 	data[0] = tp->xstats.early_rx;
       
  2626 	data[1] = tp->xstats.tx_buf_mapped;
       
  2627 	data[2] = tp->xstats.tx_timeouts;
       
  2628 	data[3] = tp->xstats.rx_lost_in_ring;
       
  2629 }
       
  2630 
       
  2631 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
       
  2632 {
       
  2633 	memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
       
  2634 }
       
  2635 
       
  2636 static const struct ethtool_ops rtl8139_ethtool_ops = {
       
  2637 	.get_drvinfo		= rtl8139_get_drvinfo,
       
  2638 	.get_settings		= rtl8139_get_settings,
       
  2639 	.set_settings		= rtl8139_set_settings,
       
  2640 	.get_regs_len		= rtl8139_get_regs_len,
       
  2641 	.get_regs		= rtl8139_get_regs,
       
  2642 	.nway_reset		= rtl8139_nway_reset,
       
  2643 	.get_link		= rtl8139_get_link,
       
  2644 	.get_msglevel		= rtl8139_get_msglevel,
       
  2645 	.set_msglevel		= rtl8139_set_msglevel,
       
  2646 	.get_wol		= rtl8139_get_wol,
       
  2647 	.set_wol		= rtl8139_set_wol,
       
  2648 	.get_strings		= rtl8139_get_strings,
       
  2649 	.get_sset_count		= rtl8139_get_sset_count,
       
  2650 	.get_ethtool_stats	= rtl8139_get_ethtool_stats,
       
  2651 };
       
  2652 
       
  2653 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
       
  2654 {
       
  2655 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2656 	int rc;
       
  2657 
       
  2658 	if (tp->ecdev || !netif_running(dev))
       
  2659 		return -EINVAL;
       
  2660 
       
  2661 	spin_lock_irq(&tp->lock);
       
  2662 	rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
       
  2663 	spin_unlock_irq(&tp->lock);
       
  2664 
       
  2665 	return rc;
       
  2666 }
       
  2667 
       
  2668 
       
  2669 static struct rtnl_link_stats64 *
       
  2670 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
       
  2671 {
       
  2672 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2673 	void __iomem *ioaddr = tp->mmio_addr;
       
  2674 	unsigned long flags;
       
  2675 	unsigned int start;
       
  2676 
       
  2677 	if (tp->ecdev || netif_running(dev)) {
       
  2678 		spin_lock_irqsave (&tp->lock, flags);
       
  2679 		dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2680 		RTL_W32 (RxMissed, 0);
       
  2681 		spin_unlock_irqrestore (&tp->lock, flags);
       
  2682 	}
       
  2683 
       
  2684 	netdev_stats_to_stats64(stats, &dev->stats);
       
  2685 
       
  2686 	do {
       
  2687 		start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
       
  2688 		stats->rx_packets = tp->rx_stats.packets;
       
  2689 		stats->rx_bytes = tp->rx_stats.bytes;
       
  2690 	} while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
       
  2691 
       
  2692 	do {
       
  2693 		start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
       
  2694 		stats->tx_packets = tp->tx_stats.packets;
       
  2695 		stats->tx_bytes = tp->tx_stats.bytes;
       
  2696 	} while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
       
  2697 
       
  2698 	return stats;
       
  2699 }
       
  2700 
       
  2701 /* Set or clear the multicast filter for this adaptor.
       
  2702    This routine is not state sensitive and need not be SMP locked. */
       
  2703 
       
  2704 static void __set_rx_mode (struct net_device *dev)
       
  2705 {
       
  2706 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2707 	void __iomem *ioaddr = tp->mmio_addr;
       
  2708 	u32 mc_filter[2];	/* Multicast hash filter */
       
  2709 	int rx_mode;
       
  2710 	u32 tmp;
       
  2711 
       
  2712 	netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
       
  2713 		   dev->flags, RTL_R32(RxConfig));
       
  2714 
       
  2715 	/* Note: do not reorder, GCC is clever about common statements. */
       
  2716 	if (dev->flags & IFF_PROMISC) {
       
  2717 		rx_mode =
       
  2718 		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
       
  2719 		    AcceptAllPhys;
       
  2720 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  2721 	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
       
  2722 		   (dev->flags & IFF_ALLMULTI)) {
       
  2723 		/* Too many to filter perfectly -- accept all multicasts. */
       
  2724 		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
       
  2725 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  2726 	} else {
       
  2727 		struct netdev_hw_addr *ha;
       
  2728 		rx_mode = AcceptBroadcast | AcceptMyPhys;
       
  2729 		mc_filter[1] = mc_filter[0] = 0;
       
  2730 		netdev_for_each_mc_addr(ha, dev) {
       
  2731 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
       
  2732 
       
  2733 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
       
  2734 			rx_mode |= AcceptMulticast;
       
  2735 		}
       
  2736 	}
       
  2737 
       
  2738 	if (dev->features & NETIF_F_RXALL)
       
  2739 		rx_mode |= (AcceptErr | AcceptRunt);
       
  2740 
       
  2741 	/* We can safely update without stopping the chip. */
       
  2742 	tmp = rtl8139_rx_config | rx_mode;
       
  2743 	if (tp->rx_config != tmp) {
       
  2744 		RTL_W32_F (RxConfig, tmp);
       
  2745 		tp->rx_config = tmp;
       
  2746 	}
       
  2747 	RTL_W32_F (MAR0 + 0, mc_filter[0]);
       
  2748 	RTL_W32_F (MAR0 + 4, mc_filter[1]);
       
  2749 }
       
  2750 
       
  2751 static void rtl8139_set_rx_mode (struct net_device *dev)
       
  2752 {
       
  2753 	unsigned long flags;
       
  2754 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2755 
       
  2756 	spin_lock_irqsave (&tp->lock, flags);
       
  2757 	__set_rx_mode(dev);
       
  2758 	spin_unlock_irqrestore (&tp->lock, flags);
       
  2759 }
       
  2760 
       
  2761 #ifdef CONFIG_PM
       
  2762 
       
  2763 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
       
  2764 {
       
  2765 	struct net_device *dev = pci_get_drvdata (pdev);
       
  2766 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2767 	void __iomem *ioaddr = tp->mmio_addr;
       
  2768 	unsigned long flags;
       
  2769 
       
  2770 	pci_save_state (pdev);
       
  2771 
       
  2772 	if (tp->ecdev || !netif_running (dev))
       
  2773 		return 0;
       
  2774 
       
  2775 	netif_device_detach (dev);
       
  2776 
       
  2777 	spin_lock_irqsave (&tp->lock, flags);
       
  2778 
       
  2779 	/* Disable interrupts, stop Tx and Rx. */
       
  2780 	RTL_W16 (IntrMask, 0);
       
  2781 	RTL_W8 (ChipCmd, 0);
       
  2782 
       
  2783 	/* Update the error counts. */
       
  2784 	dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2785 	RTL_W32 (RxMissed, 0);
       
  2786 
       
  2787 	spin_unlock_irqrestore (&tp->lock, flags);
       
  2788 
       
  2789 	pci_set_power_state (pdev, PCI_D3hot);
       
  2790 
       
  2791 	return 0;
       
  2792 }
       
  2793 
       
  2794 
       
  2795 static int rtl8139_resume (struct pci_dev *pdev)
       
  2796 {
       
  2797 	struct net_device *dev = pci_get_drvdata (pdev);
       
  2798 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2799 
       
  2800 	pci_restore_state (pdev);
       
  2801 	if (tp->ecdev || !netif_running (dev))
       
  2802 		return 0;
       
  2803 	pci_set_power_state (pdev, PCI_D0);
       
  2804 	rtl8139_init_ring (dev);
       
  2805 	rtl8139_hw_start (dev);
       
  2806 	netif_device_attach (dev);
       
  2807 	return 0;
       
  2808 }
       
  2809 
       
  2810 #endif /* CONFIG_PM */
       
  2811 
       
  2812 
       
  2813 static struct pci_driver rtl8139_pci_driver = {
       
  2814 	.name		= DRV_NAME,
       
  2815 	.id_table	= rtl8139_pci_tbl,
       
  2816 	.probe		= rtl8139_init_one,
       
  2817 	.remove		= rtl8139_remove_one,
       
  2818 #ifdef CONFIG_PM
       
  2819 	.suspend	= rtl8139_suspend,
       
  2820 	.resume		= rtl8139_resume,
       
  2821 #endif /* CONFIG_PM */
       
  2822 };
       
  2823 
       
  2824 
       
  2825 static int __init rtl8139_init_module (void)
       
  2826 {
       
  2827 	/* when we're a module, we always print a version message,
       
  2828 	 * even if no 8139 board is found.
       
  2829 	 */
       
  2830 #ifdef MODULE
       
  2831 	pr_info(RTL8139_DRIVER_NAME "\n");
       
  2832 #endif
       
  2833 
       
  2834 	return pci_register_driver(&rtl8139_pci_driver);
       
  2835 }
       
  2836 
       
  2837 
       
  2838 static void __exit rtl8139_cleanup_module (void)
       
  2839 {
       
  2840 	pci_unregister_driver (&rtl8139_pci_driver);
       
  2841 }
       
  2842 
       
  2843 
       
  2844 module_init(rtl8139_init_module);
       
  2845 module_exit(rtl8139_cleanup_module);