1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *****************************************************************************/

    29 

    30 /**

    31    \file

    32    EtherCAT driver for RTL8139-compatible NICs.

    33 */

    34 

    35 /*****************************************************************************/

    36 

    37 /*

    38   Former documentation:

    39 

    40 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41 

    42 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43 	Copyright 2000-2002 Jeff Garzik

    44 

    45 	Much code comes from Donald Becker's rtl8139.c driver,

    46 	versions 1.13 and older.  This driver was originally based

    47 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48 

    49 	-----<snip>-----

    50 

    51         	Written 1997-2001 by Donald Becker.

    52 		This software may be used and distributed according to the

    53 		terms of the GNU General Public License (GPL), incorporated

    54 		herein by reference.  Drivers based on or derived from this

    55 		code fall under the GPL and must retain the authorship,

    56 		copyright and license notice.  This file is not a complete

    57 		program and may only be used when the entire operating

    58 		system is licensed under the GPL.

    59 

    60 		This driver is for boards based on the RTL8129 and RTL8139

    61 		PCI ethernet chips.

    62 

    63 		The author may be reached as becker@scyld.com, or C/O Scyld

    64 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65 		MD 21403

    66 

    67 		Support and updates available at

    68 		http://www.scyld.com/network/rtl8139.html

    69 

    70 		Twister-tuning table provided by Kinston

    71 		<shangh@realtek.com.tw>.

    72 

    73 	-----<snip>-----

    74 

    75 	This software may be used and distributed according to the terms

    76 	of the GNU General Public License, incorporated herein by reference.

    77 

    78 	Contributors:

    79 

    80 		Donald Becker - he wrote the original driver, kudos to him!

    81 		(but please don't e-mail him for support, this isn't his driver)

    82 

    83 		Tigran Aivazian - bug fixes, skbuff free cleanup

    84 

    85 		Martin Mares - suggestions for PCI cleanup

    86 

    87 		David S. Miller - PCI DMA and softnet updates

    88 

    89 		Ernst Gill - fixes ported from BSD driver

    90 

    91 		Daniel Kobras - identified specific locations of

    92 			posted MMIO write bugginess

    93 

    94 		Gerard Sharp - bug fix, testing and feedback

    95 

    96 		David Ford - Rx ring wrap fix

    97 

    98 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    99 		to find and fix a crucial bug on older chipsets.

   100 

   101 		Donald Becker/Chris Butterworth/Marcus Westergren -

   102 		Noticed various Rx packet size-related buglets.

   103 

   104 		Santiago Garcia Mantinan - testing and feedback

   105 

   106 		Jens David - 2.2.x kernel backports

   107 

   108 		Martin Dennett - incredibly helpful insight on undocumented

   109 		features of the 8139 chips

   110 

   111 		Jean-Jacques Michel - bug fix

   112 

   113 		Tobias Ringström - Rx interrupt status checking suggestion

   114 

   115 		Andrew Morton - Clear blocked signals, avoid

   116 		buffer overrun setting current->comm.

   117 

   118 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   119 

   120 		Robert Kuebel - Save kernel thread from dying on any signal.

   121 

   122 	Submitting bug reports:

   123 

   124 		"rtl8139-diag -mmmaaavvveefN" output

   125 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   126 

   127 */

   128 

   129 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

   130 

   131 #define DRV_NAME	"ec_8139too"

   132 #define DRV_VERSION	"0.9.28"

   133 

   134 

   135 #include <linux/module.h>

   136 #include <linux/kernel.h>

   137 #include <linux/compiler.h>

   138 #include <linux/pci.h>

   139 #include <linux/init.h>

   140 #include <linux/netdevice.h>

   141 #include <linux/etherdevice.h>

   142 #include <linux/rtnetlink.h>

   143 #include <linux/delay.h>

   144 #include <linux/ethtool.h>

   145 #include <linux/mii.h>

   146 #include <linux/completion.h>

   147 #include <linux/crc32.h>

   148 #include <linux/io.h>

   149 #include <linux/uaccess.h>

   150 #include <linux/gfp.h>

   151 #include <asm/irq.h>

   152 

   153 #include "../globals.h"

   154 #include "ecdev.h"

   155 

   156 #define RTL8139_DRIVER_NAME DRV_NAME \

   157                             " EtherCAT-capable Fast Ethernet driver " \

   158                             DRV_VERSION ", master " EC_MASTER_VERSION

   159 

   160 #define PFX DRV_NAME ": "

   161 

   162 /* Default Message level */

   163 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   164                                  NETIF_MSG_PROBE  | \

   165                                  NETIF_MSG_LINK)

   166 

   167 

   168 /* define to 1, 2 or 3 to enable copious debugging info */

   169 #define RTL8139_DEBUG 0

   170 

   171 /* define to 1 to disable lightweight runtime debugging checks */

   172 #undef RTL8139_NDEBUG

   173 

   174 

   175 #ifdef RTL8139_NDEBUG

   176 #  define assert(expr) do {} while (0)

   177 #else

   178 #  define assert(expr) \

   179         if (unlikely(!(expr))) {				\

   180 		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   181 		       #expr, __FILE__, __func__, __LINE__);	\

   182         }

   183 #endif

   184 

   185 

   186 /* A few user-configurable values. */

   187 /* media options */

   188 #define MAX_UNITS 8

   189 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   190 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   191 

   192 /* Whether to use MMIO or PIO. Default to MMIO. */

   193 #ifdef CONFIG_8139TOO_PIO

   194 static int use_io = 1;

   195 #else

   196 static int use_io = 0;

   197 #endif

   198 

   199 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   200    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   201 static int multicast_filter_limit = 32;

   202 

   203 /* bitmapped message enable number */

   204 static int debug = -1;

   205 

   206 /*

   207  * Receive ring size

   208  * Warning: 64K ring has hardware issues and may lock up.

   209  */

   210 #if defined(CONFIG_SH_DREAMCAST)

   211 #define RX_BUF_IDX 0	/* 8K ring */

   212 #else

   213 #define RX_BUF_IDX	2	/* 32K ring */

   214 #endif

   215 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   216 #define RX_BUF_PAD	16

   217 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   218 

   219 #if RX_BUF_LEN == 65536

   220 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   221 #else

   222 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   223 #endif

   224 

   225 /* Number of Tx descriptor registers. */

   226 #define NUM_TX_DESC	4

   227 

   228 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   229 #define MAX_ETH_FRAME_SIZE	1536

   230 

   231 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   232 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   233 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   234 

   235 /* PCI Tuning Parameters

   236    Threshold is bytes transferred to chip before transmission starts. */

   237 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   238 

   239 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   240 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   241 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   242 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   243 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   244 

   245 /* Operational parameters that usually are not changed. */

   246 /* Time in jiffies before concluding the transmitter is hung. */

   247 #define TX_TIMEOUT  (6*HZ)

   248 

   249 

   250 enum {

   251 	HAS_MII_XCVR = 0x010000,

   252 	HAS_CHIP_XCVR = 0x020000,

   253 	HAS_LNK_CHNG = 0x040000,

   254 };

   255 

   256 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   257 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   258 #define RTL_MIN_IO_SIZE 0x80

   259 #define RTL8139B_IO_SIZE 256

   260 

   261 #define RTL8129_CAPS	HAS_MII_XCVR

   262 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   263 

   264 typedef enum {

   265 	RTL8139 = 0,

   266 	RTL8129,

   267 } board_t;

   268 

   269 

   270 /* indexed by board_t, above */

   271 static const struct {

   272 	const char *name;

   273 	u32 hw_flags;

   274 } board_info[] __devinitdata = {

   275 	{ "RealTek RTL8139", RTL8139_CAPS },

   276 	{ "RealTek RTL8129", RTL8129_CAPS },

   277 };

   278 

   279 

   280 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   281 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   282 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 

   301 #ifdef CONFIG_SH_SECUREEDGE5410

   302 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   303 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 #endif

   305 #ifdef CONFIG_8139TOO_8129

   306 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   307 #endif

   308 

   309 	/* some crazy cards report invalid vendor ids like

   310 	 * 0x0001 here.  The other ids are valid and constant,

   311 	 * so we simply don't match on the main vendor id.

   312 	 */

   313 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   314 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   315 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   316 

   317 	{0,}

   318 };

   319 

   320 /* prevent driver from being loaded automatically */

   321 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   322 

   323 static struct {

   324 	const char str[ETH_GSTRING_LEN];

   325 } ethtool_stats_keys[] = {

   326 	{ "early_rx" },

   327 	{ "tx_buf_mapped" },

   328 	{ "tx_timeouts" },

   329 	{ "rx_lost_in_ring" },

   330 };

   331 

   332 /* The rest of these values should never change. */

   333 

   334 /* Symbolic offsets to registers. */

   335 enum RTL8139_registers {

   336 	MAC0		= 0,	 /* Ethernet hardware address. */

   337 	MAR0		= 8,	 /* Multicast filter. */

   338 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   339 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   340 	RxBuf		= 0x30,

   341 	ChipCmd		= 0x37,

   342 	RxBufPtr	= 0x38,

   343 	RxBufAddr	= 0x3A,

   344 	IntrMask	= 0x3C,

   345 	IntrStatus	= 0x3E,

   346 	TxConfig	= 0x40,

   347 	RxConfig	= 0x44,

   348 	Timer		= 0x48,	 /* A general-purpose counter. */

   349 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   350 	Cfg9346		= 0x50,

   351 	Config0		= 0x51,

   352 	Config1		= 0x52,

   353 	TimerInt	= 0x54,

   354 	MediaStatus	= 0x58,

   355 	Config3		= 0x59,

   356 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   357 	HltClk		= 0x5B,

   358 	MultiIntr	= 0x5C,

   359 	TxSummary	= 0x60,

   360 	BasicModeCtrl	= 0x62,

   361 	BasicModeStatus	= 0x64,

   362 	NWayAdvert	= 0x66,

   363 	NWayLPAR	= 0x68,

   364 	NWayExpansion	= 0x6A,

   365 	/* Undocumented registers, but required for proper operation. */

   366 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   367 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   368 	PARA78		= 0x78,

   369 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   370 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   371 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   372 };

   373 

   374 enum ClearBitMasks {

   375 	MultiIntrClear	= 0xF000,

   376 	ChipCmdClear	= 0xE2,

   377 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   378 };

   379 

   380 enum ChipCmdBits {

   381 	CmdReset	= 0x10,

   382 	CmdRxEnb	= 0x08,

   383 	CmdTxEnb	= 0x04,

   384 	RxBufEmpty	= 0x01,

   385 };

   386 

   387 /* Interrupt register bits, using my own meaningful names. */

   388 enum IntrStatusBits {

   389 	PCIErr		= 0x8000,

   390 	PCSTimeout	= 0x4000,

   391 	RxFIFOOver	= 0x40,

   392 	RxUnderrun	= 0x20,

   393 	RxOverflow	= 0x10,

   394 	TxErr		= 0x08,

   395 	TxOK		= 0x04,

   396 	RxErr		= 0x02,

   397 	RxOK		= 0x01,

   398 

   399 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   400 };

   401 

   402 enum TxStatusBits {

   403 	TxHostOwns	= 0x2000,

   404 	TxUnderrun	= 0x4000,

   405 	TxStatOK	= 0x8000,

   406 	TxOutOfWindow	= 0x20000000,

   407 	TxAborted	= 0x40000000,

   408 	TxCarrierLost	= 0x80000000,

   409 };

   410 enum RxStatusBits {

   411 	RxMulticast	= 0x8000,

   412 	RxPhysical	= 0x4000,

   413 	RxBroadcast	= 0x2000,

   414 	RxBadSymbol	= 0x0020,

   415 	RxRunt		= 0x0010,

   416 	RxTooLong	= 0x0008,

   417 	RxCRCErr	= 0x0004,

   418 	RxBadAlign	= 0x0002,

   419 	RxStatusOK	= 0x0001,

   420 };

   421 

   422 /* Bits in RxConfig. */

   423 enum rx_mode_bits {

   424 	AcceptErr	= 0x20,

   425 	AcceptRunt	= 0x10,

   426 	AcceptBroadcast	= 0x08,

   427 	AcceptMulticast	= 0x04,

   428 	AcceptMyPhys	= 0x02,

   429 	AcceptAllPhys	= 0x01,

   430 };

   431 

   432 /* Bits in TxConfig. */

   433 enum tx_config_bits {

   434         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   435         TxIFGShift	= 24,

   436         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   437         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   438         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   439         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   440 

   441 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   442 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   443 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   444 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   445 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   446 

   447 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   448 };

   449 

   450 /* Bits in Config1 */

   451 enum Config1Bits {

   452 	Cfg1_PM_Enable	= 0x01,

   453 	Cfg1_VPD_Enable	= 0x02,

   454 	Cfg1_PIO	= 0x04,

   455 	Cfg1_MMIO	= 0x08,

   456 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   457 	Cfg1_Driver_Load = 0x20,

   458 	Cfg1_LED0	= 0x40,

   459 	Cfg1_LED1	= 0x80,

   460 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   461 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   462 };

   463 

   464 /* Bits in Config3 */

   465 enum Config3Bits {

   466 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   467 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   468 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   469 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   470 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   471 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   472 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   473 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   474 };

   475 

   476 /* Bits in Config4 */

   477 enum Config4Bits {

   478 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   479 };

   480 

   481 /* Bits in Config5 */

   482 enum Config5Bits {

   483 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   484 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   485 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   486 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   487 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   488 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   489 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   490 };

   491 

   492 enum RxConfigBits {

   493 	/* rx fifo threshold */

   494 	RxCfgFIFOShift	= 13,

   495 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   496 

   497 	/* Max DMA burst */

   498 	RxCfgDMAShift	= 8,

   499 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   500 

   501 	/* rx ring buffer length */

   502 	RxCfgRcv8K	= 0,

   503 	RxCfgRcv16K	= (1 << 11),

   504 	RxCfgRcv32K	= (1 << 12),

   505 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   506 

   507 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   508 	RxNoWrap	= (1 << 7),

   509 };

   510 

   511 /* Twister tuning parameters from RealTek.

   512    Completely undocumented, but required to tune bad links on some boards. */

   513 enum CSCRBits {

   514 	CSCR_LinkOKBit		= 0x0400,

   515 	CSCR_LinkChangeBit	= 0x0800,

   516 	CSCR_LinkStatusBits	= 0x0f000,

   517 	CSCR_LinkDownOffCmd	= 0x003c0,

   518 	CSCR_LinkDownCmd	= 0x0f3c0,

   519 };

   520 

   521 enum Cfg9346Bits {

   522 	Cfg9346_Lock	= 0x00,

   523 	Cfg9346_Unlock	= 0xC0,

   524 };

   525 

   526 typedef enum {

   527 	CH_8139	= 0,

   528 	CH_8139_K,

   529 	CH_8139A,

   530 	CH_8139A_G,

   531 	CH_8139B,

   532 	CH_8130,

   533 	CH_8139C,

   534 	CH_8100,

   535 	CH_8100B_8139D,

   536 	CH_8101,

   537 } chip_t;

   538 

   539 enum chip_flags {

   540 	HasHltClk	= (1 << 0),

   541 	HasLWake	= (1 << 1),

   542 };

   543 

   544 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   545 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   546 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   547 

   548 /* directly indexed by chip_t, above */

   549 static const struct {

   550 	const char *name;

   551 	u32 version; /* from RTL8139C/RTL8139D docs */

   552 	u32 flags;

   553 } rtl_chip_info[] = {

   554 	{ "RTL-8139",

   555 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   556 	  HasHltClk,

   557 	},

   558 

   559 	{ "RTL-8139 rev K",

   560 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   561 	  HasHltClk,

   562 	},

   563 

   564 	{ "RTL-8139A",

   565 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   566 	  HasHltClk, /* XXX undocumented? */

   567 	},

   568 

   569 	{ "RTL-8139A rev G",

   570 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   571 	  HasHltClk, /* XXX undocumented? */

   572 	},

   573 

   574 	{ "RTL-8139B",

   575 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   576 	  HasLWake,

   577 	},

   578 

   579 	{ "RTL-8130",

   580 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   581 	  HasLWake,

   582 	},

   583 

   584 	{ "RTL-8139C",

   585 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   586 	  HasLWake,

   587 	},

   588 

   589 	{ "RTL-8100",

   590 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   591  	  HasLWake,

   592  	},

   593 

   594 	{ "RTL-8100B/8139D",

   595 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   596 	  HasHltClk /* XXX undocumented? */

   597 	| HasLWake,

   598 	},

   599 

   600 	{ "RTL-8101",

   601 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   602 	  HasLWake,

   603 	},

   604 };

   605 

   606 struct rtl_extra_stats {

   607 	unsigned long early_rx;

   608 	unsigned long tx_buf_mapped;

   609 	unsigned long tx_timeouts;

   610 	unsigned long rx_lost_in_ring;

   611 };

   612 

   613 struct rtl8139_private {

   614 	void __iomem		*mmio_addr;

   615 	int			drv_flags;

   616 	struct pci_dev		*pci_dev;

   617 	u32			msg_enable;

   618 	struct napi_struct	napi;

   619 	struct net_device	*dev;

   620 

   621 	unsigned char		*rx_ring;

   622 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   623 	dma_addr_t		rx_ring_dma;

   624 

   625 	unsigned int		tx_flag;

   626 	unsigned long		cur_tx;

   627 	unsigned long		dirty_tx;

   628 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   629 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   630 	dma_addr_t		tx_bufs_dma;

   631 

   632 	signed char		phys[4];	/* MII device addresses. */

   633 

   634 				/* Twister tune state. */

   635 	char			twistie, twist_row, twist_col;

   636 

   637 	unsigned int		watchdog_fired : 1;

   638 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   639 	unsigned int		have_thread : 1;

   640 

   641 	spinlock_t		lock;

   642 	spinlock_t		rx_lock;

   643 

   644 	chip_t			chipset;

   645 	u32			rx_config;

   646 	struct rtl_extra_stats	xstats;

   647 

   648 	struct delayed_work	thread;

   649 

   650 	struct mii_if_info	mii;

   651 	unsigned int		regs_len;

   652 	unsigned long		fifo_copy_timeout;

   653 

   654 	ec_device_t *ecdev;

   655 };

   656 

   657 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   658 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   659 MODULE_LICENSE("GPL");

   660 MODULE_VERSION(EC_MASTER_VERSION);

   661 

   662 module_param(use_io, int, 0);

   663 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   664 module_param(multicast_filter_limit, int, 0);

   665 module_param_array(media, int, NULL, 0);

   666 module_param_array(full_duplex, int, NULL, 0);

   667 module_param(debug, int, 0);

   668 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   669 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   670 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   671 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   672 

   673 void ec_poll(struct net_device *);

   674 

   675 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   676 static int rtl8139_open (struct net_device *dev);

   677 static int mdio_read (struct net_device *dev, int phy_id, int location);

   678 static void mdio_write (struct net_device *dev, int phy_id, int location,

   679 			int val);

   680 static void rtl8139_start_thread(struct rtl8139_private *tp);

   681 static void rtl8139_tx_timeout (struct net_device *dev);

   682 static void rtl8139_init_ring (struct net_device *dev);

   683 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,

   684 				       struct net_device *dev);

   685 #ifdef CONFIG_NET_POLL_CONTROLLER

   686 static void rtl8139_poll_controller(struct net_device *dev);

   687 #endif

   688 static int rtl8139_set_mac_address(struct net_device *dev, void *p);

   689 static int rtl8139_poll(struct napi_struct *napi, int budget);

   690 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   691 static int rtl8139_close (struct net_device *dev);

   692 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   693 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   694 static void rtl8139_set_rx_mode (struct net_device *dev);

   695 static void __set_rx_mode (struct net_device *dev);

   696 static void rtl8139_hw_start (struct net_device *dev);

   697 static void rtl8139_thread (struct work_struct *work);

   698 static void rtl8139_tx_timeout_task(struct work_struct *work);

   699 static const struct ethtool_ops rtl8139_ethtool_ops;

   700 

   701 /* write MMIO register, with flush */

   702 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   703 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   704 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   705 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   706 

   707 /* write MMIO register */

   708 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   709 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   710 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   711 

   712 /* read MMIO register */

   713 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   714 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   715 #define RTL_R32(reg)		ioread32 (ioaddr + (reg))

   716 

   717 

   718 static const u16 rtl8139_intr_mask =

   719 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   720 	TxErr | TxOK | RxErr | RxOK;

   721 

   722 static const u16 rtl8139_norx_intr_mask =

   723 	PCIErr | PCSTimeout | RxUnderrun |

   724 	TxErr | TxOK | RxErr ;

   725 

   726 #if RX_BUF_IDX == 0

   727 static const unsigned int rtl8139_rx_config =

   728 	RxCfgRcv8K | RxNoWrap |

   729 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   730 	(RX_DMA_BURST << RxCfgDMAShift);

   731 #elif RX_BUF_IDX == 1

   732 static const unsigned int rtl8139_rx_config =

   733 	RxCfgRcv16K | RxNoWrap |

   734 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   735 	(RX_DMA_BURST << RxCfgDMAShift);

   736 #elif RX_BUF_IDX == 2

   737 static const unsigned int rtl8139_rx_config =

   738 	RxCfgRcv32K | RxNoWrap |

   739 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   740 	(RX_DMA_BURST << RxCfgDMAShift);

   741 #elif RX_BUF_IDX == 3

   742 static const unsigned int rtl8139_rx_config =

   743 	RxCfgRcv64K |

   744 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   745 	(RX_DMA_BURST << RxCfgDMAShift);

   746 #else

   747 #error "Invalid configuration for 8139_RXBUF_IDX"

   748 #endif

   749 

   750 static const unsigned int rtl8139_tx_config =

   751 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   752 

   753 static void __rtl8139_cleanup_dev (struct net_device *dev)

   754 {

   755 	struct rtl8139_private *tp = netdev_priv(dev);

   756 	struct pci_dev *pdev;

   757 

   758 	assert (dev != NULL);

   759 	assert (tp->pci_dev != NULL);

   760 	pdev = tp->pci_dev;

   761 

   762 	if (tp->mmio_addr)

   763 		pci_iounmap (pdev, tp->mmio_addr);

   764 

   765 	/* it's ok to call this even if we have no regions to free */

   766 	pci_release_regions (pdev);

   767 

   768 	free_netdev(dev);

   769 	pci_set_drvdata (pdev, NULL);

   770 }

   771 

   772 

   773 static void rtl8139_chip_reset (void __iomem *ioaddr)

   774 {

   775 	int i;

   776 

   777 	/* Soft reset the chip. */

   778 	RTL_W8 (ChipCmd, CmdReset);

   779 

   780 	/* Check that the chip has finished the reset. */

   781 	for (i = 1000; i > 0; i--) {

   782 		barrier();

   783 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   784 			break;

   785 		udelay (10);

   786 	}

   787 }

   788 

   789 

   790 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)

   791 {

   792 	void __iomem *ioaddr;

   793 	struct net_device *dev;

   794 	struct rtl8139_private *tp;

   795 	u8 tmp8;

   796 	int rc, disable_dev_on_err = 0;

   797 	unsigned int i;

   798 	unsigned long pio_start, pio_end __attribute__ ((unused)), pio_flags,

   799                   pio_len;

   800 	unsigned long mmio_start __attribute__ ((unused)),

   801                   mmio_end __attribute__ ((unused)), mmio_flags, mmio_len;

   802 	u32 version;

   803 

   804 	assert (pdev != NULL);

   805 

   806 	/* dev and priv zeroed in alloc_etherdev */

   807 	dev = alloc_etherdev (sizeof (*tp));

   808 	if (dev == NULL) {

   809 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   810 		return ERR_PTR(-ENOMEM);

   811 	}

   812 	SET_NETDEV_DEV(dev, &pdev->dev);

   813 

   814 	tp = netdev_priv(dev);

   815 	tp->pci_dev = pdev;

   816 

   817 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   818 	rc = pci_enable_device (pdev);

   819 	if (rc)

   820 		goto err_out;

   821 

   822 	pio_start = pci_resource_start (pdev, 0);

   823 	pio_end = pci_resource_end (pdev, 0);

   824 	pio_flags = pci_resource_flags (pdev, 0);

   825 	pio_len = pci_resource_len (pdev, 0);

   826 

   827 	mmio_start = pci_resource_start (pdev, 1);

   828 	mmio_end = pci_resource_end (pdev, 1);

   829 	mmio_flags = pci_resource_flags (pdev, 1);

   830 	mmio_len = pci_resource_len (pdev, 1);

   831 

   832 	/* set this immediately, we need to know before

   833 	 * we talk to the chip directly */

   834 	pr_debug("PIO region size == 0x%02lX\n", pio_len);

   835 	pr_debug("MMIO region size == 0x%02lX\n", mmio_len);

   836 

   837 retry:

   838 	if (use_io) {

   839 		/* make sure PCI base addr 0 is PIO */

   840 		if (!(pio_flags & IORESOURCE_IO)) {

   841 			dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   842 			rc = -ENODEV;

   843 			goto err_out;

   844 		}

   845 		/* check for weird/broken PCI region reporting */

   846 		if (pio_len < RTL_MIN_IO_SIZE) {

   847 			dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   848 			rc = -ENODEV;

   849 			goto err_out;

   850 		}

   851 	} else {

   852 		/* make sure PCI base addr 1 is MMIO */

   853 		if (!(mmio_flags & IORESOURCE_MEM)) {

   854 			dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   855 			rc = -ENODEV;

   856 			goto err_out;

   857 		}

   858 		if (mmio_len < RTL_MIN_IO_SIZE) {

   859 			dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   860 			rc = -ENODEV;

   861 			goto err_out;

   862 		}

   863 	}

   864 

   865 	rc = pci_request_regions (pdev, DRV_NAME);

   866 	if (rc)

   867 		goto err_out;

   868 	disable_dev_on_err = 1;

   869 

   870 	/* enable PCI bus-mastering */

   871 	pci_set_master (pdev);

   872 

   873 	if (use_io) {

   874 		ioaddr = pci_iomap(pdev, 0, 0);

   875 		if (!ioaddr) {

   876 			dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   877 			rc = -EIO;

   878 			goto err_out;

   879 		}

   880 		dev->base_addr = pio_start;

   881 		tp->regs_len = pio_len;

   882 	} else {

   883 		/* ioremap MMIO region */

   884 		ioaddr = pci_iomap(pdev, 1, 0);

   885 		if (ioaddr == NULL) {

   886 			dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");

   887 			pci_release_regions(pdev);

   888 			use_io = 1;

   889 			goto retry;

   890 		}

   891 		dev->base_addr = (long) ioaddr;

   892 		tp->regs_len = mmio_len;

   893 	}

   894 	tp->mmio_addr = ioaddr;

   895 

   896 	/* Bring old chips out of low-power mode. */

   897 	RTL_W8 (HltClk, 'R');

   898 

   899 	/* check for missing/broken hardware */

   900 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   901 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   902 		rc = -EIO;

   903 		goto err_out;

   904 	}

   905 

   906 	/* identify chip attached to board */

   907 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   908 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   909 		if (version == rtl_chip_info[i].version) {

   910 			tp->chipset = i;

   911 			goto match;

   912 		}

   913 

   914 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   915 	i = 0;

   916 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");

   917 	dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));

   918 	tp->chipset = 0;

   919 

   920 match:

   921 	pr_debug("chipset id (%d) == index %d, '%s'\n",

   922 		 version, i, rtl_chip_info[i].name);

   923 

   924 	if (tp->chipset >= CH_8139B) {

   925 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   926 		pr_debug("PCI PM wakeup\n");

   927 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   928 		    (tmp8 & LWAKE))

   929 			new_tmp8 &= ~LWAKE;

   930 		new_tmp8 |= Cfg1_PM_Enable;

   931 		if (new_tmp8 != tmp8) {

   932 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   933 			RTL_W8 (Config1, tmp8);

   934 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   935 		}

   936 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   937 			tmp8 = RTL_R8 (Config4);

   938 			if (tmp8 & LWPTN) {

   939 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   940 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   941 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   942 			}

   943 		}

   944 	} else {

   945 		pr_debug("Old chip wakeup\n");

   946 		tmp8 = RTL_R8 (Config1);

   947 		tmp8 &= ~(SLEEP | PWRDN);

   948 		RTL_W8 (Config1, tmp8);

   949 	}

   950 

   951 	rtl8139_chip_reset (ioaddr);

   952 

   953 	return dev;

   954 

   955 err_out:

   956 	__rtl8139_cleanup_dev (dev);

   957 	if (disable_dev_on_err)

   958 		pci_disable_device (pdev);

   959 	return ERR_PTR(rc);

   960 }

   961 

   962 static const struct net_device_ops rtl8139_netdev_ops = {

   963 	.ndo_open		= rtl8139_open,

   964 	.ndo_stop		= rtl8139_close,

   965 	.ndo_get_stats		= rtl8139_get_stats,

   966 	.ndo_change_mtu		= eth_change_mtu,

   967 	.ndo_validate_addr	= eth_validate_addr,

   968 	.ndo_set_mac_address 	= rtl8139_set_mac_address,

   969 	.ndo_start_xmit		= rtl8139_start_xmit,

   970 	.ndo_set_multicast_list	= rtl8139_set_rx_mode,

   971 	.ndo_do_ioctl		= netdev_ioctl,

   972 	.ndo_tx_timeout		= rtl8139_tx_timeout,

   973 #ifdef CONFIG_NET_POLL_CONTROLLER

   974 	.ndo_poll_controller	= rtl8139_poll_controller,

   975 #endif

   976 };

   977 

   978 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   979 				       const struct pci_device_id *ent)

   980 {

   981 	struct net_device *dev = NULL;

   982 	struct rtl8139_private *tp;

   983 	int i, addr_len, option;

   984 	void __iomem *ioaddr;

   985 	static int board_idx = -1;

   986 

   987 	assert (pdev != NULL);

   988 	assert (ent != NULL);

   989 

   990 	board_idx++;

   991 

   992 	/* when we're built into the kernel, the driver version message

   993 	 * is only printed if at least one 8139 board has been found

   994 	 */

   995 #ifndef MODULE

   996 	{

   997 		static int printed_version;

   998 		if (!printed_version++)

   999 			pr_info(RTL8139_DRIVER_NAME "\n");

  1000 	}

  1001 #endif

  1002 

  1003 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1004 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

  1005 		dev_info(&pdev->dev,

  1006 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",

  1007 		       	   pdev->vendor, pdev->device, pdev->revision);

  1008 		return -ENODEV;

  1009 	}

  1010 

  1011 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1012 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1013 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1014 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1015 		pr_info("OQO Model 2 detected. Forcing PIO\n");

  1016 		use_io = 1;

  1017 	}

  1018 

  1019 	dev = rtl8139_init_board (pdev);

  1020 	if (IS_ERR(dev))

  1021 		return PTR_ERR(dev);

  1022 

  1023 	assert (dev != NULL);

  1024 	tp = netdev_priv(dev);

  1025 	tp->dev = dev;

  1026 

  1027 	ioaddr = tp->mmio_addr;

  1028 	assert (ioaddr != NULL);

  1029 

  1030 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1031 	for (i = 0; i < 3; i++)

  1032 		((__le16 *) (dev->dev_addr))[i] =

  1033 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1034 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1035 

  1036 	/* The Rtl8139-specific entries in the device structure. */

  1037 	dev->netdev_ops = &rtl8139_netdev_ops;

  1038 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1039 	dev->watchdog_timeo = TX_TIMEOUT;

  1040 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1041 

  1042 	/* note: the hardware is not capable of sg/csum/highdma, however

  1043 	 * through the use of skb_copy_and_csum_dev we enable these

  1044 	 * features

  1045 	 */

  1046 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1047 	dev->vlan_features = dev->features;

  1048 

  1049 	dev->irq = pdev->irq;

  1050 

  1051 	/* tp zeroed and aligned in alloc_etherdev */

  1052 	tp = netdev_priv(dev);

  1053 

  1054 	/* note: tp->chipset set in rtl8139_init_board */

  1055 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1056 	tp->mmio_addr = ioaddr;

  1057 	tp->msg_enable =

  1058 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1059 	spin_lock_init (&tp->lock);

  1060 	spin_lock_init (&tp->rx_lock);

  1061 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1062 	tp->mii.dev = dev;

  1063 	tp->mii.mdio_read = mdio_read;

  1064 	tp->mii.mdio_write = mdio_write;

  1065 	tp->mii.phy_id_mask = 0x3f;

  1066 	tp->mii.reg_num_mask = 0x1f;

  1067 

  1068 	/* dev is fully set up and ready to use now */

  1069 	// offer device to EtherCAT master module

  1070 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1071 

  1072 	if (!tp->ecdev) {

  1073 		pr_debug("about to register device named %s (%p)...\n", dev->name, dev);

  1074 		i = register_netdev (dev);

  1075 		if (i) goto err_out;

  1076 	}

  1077 

  1078 	pci_set_drvdata (pdev, dev);

  1079 

  1080 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",

  1081 		dev->name,

  1082 		board_info[ent->driver_data].name,

  1083 		dev->base_addr,

  1084 		dev->dev_addr,

  1085 		dev->irq);

  1086 

  1087 	pr_debug("%s:  Identified 8139 chip type '%s'\n",

  1088 		dev->name, rtl_chip_info[tp->chipset].name);

  1089 

  1090 	/* Find the connected MII xcvrs.

  1091 	   Doing this in open() would allow detecting external xcvrs later, but

  1092 	   takes too much time. */

  1093 #ifdef CONFIG_8139TOO_8129

  1094 	if (tp->drv_flags & HAS_MII_XCVR) {

  1095 		int phy, phy_idx = 0;

  1096 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1097 			int mii_status = mdio_read(dev, phy, 1);

  1098 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1099 				u16 advertising = mdio_read(dev, phy, 4);

  1100 				tp->phys[phy_idx++] = phy;

  1101 				pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",

  1102 					   dev->name, phy, mii_status, advertising);

  1103 			}

  1104 		}

  1105 		if (phy_idx == 0) {

  1106 			pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",

  1107 				   dev->name);

  1108 			tp->phys[0] = 32;

  1109 		}

  1110 	} else

  1111 #endif

  1112 		tp->phys[0] = 32;

  1113 	tp->mii.phy_id = tp->phys[0];

  1114 

  1115 	/* The lower four bits are the media type. */

  1116 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1117 	if (option > 0) {

  1118 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1119 		tp->default_port = option & 0xFF;

  1120 		if (tp->default_port)

  1121 			tp->mii.force_media = 1;

  1122 	}

  1123 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1124 		tp->mii.full_duplex = full_duplex[board_idx];

  1125 	if (tp->mii.full_duplex) {

  1126 		pr_info("%s: Media type forced to Full Duplex.\n", dev->name);

  1127 		/* Changing the MII-advertised media because might prevent

  1128 		   re-connection. */

  1129 		tp->mii.force_media = 1;

  1130 	}

  1131 	if (tp->default_port) {

  1132 		pr_info("  Forcing %dMbps %s-duplex operation.\n",

  1133 			   (option & 0x20 ? 100 : 10),

  1134 			   (option & 0x10 ? "full" : "half"));

  1135 		mdio_write(dev, tp->phys[0], 0,

  1136 				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */