master/fsm_sii.c
changeset 1039 2881a83d084f
parent 986 a486591ba86b
child 1123 17bef224061d
equal deleted inserted replaced
1038:7ca4103ba170 1039:2881a83d084f
   223                 fsm->slave->ring_position);
   223                 fsm->slave->ring_position);
   224         ec_datagram_print_wc_error(datagram);
   224         ec_datagram_print_wc_error(datagram);
   225         return;
   225         return;
   226     }
   226     }
   227 
   227 
   228     fsm->cycles_start = datagram->cycles_sent;
   228     fsm->jiffies_start = datagram->jiffies_sent;
   229     fsm->check_once_more = 1;
   229     fsm->check_once_more = 1;
   230 
   230 
   231     // issue check/fetch datagram
   231     // issue check/fetch datagram
   232     switch (fsm->mode) {
   232     switch (fsm->mode) {
   233         case EC_FSM_SII_USE_INCREMENT_ADDRESS:
   233         case EC_FSM_SII_USE_INCREMENT_ADDRESS:
   287 
   287 
   288     // check "busy bit"
   288     // check "busy bit"
   289     if (EC_READ_U8(datagram->data + 1) & 0x81) { // busy bit or
   289     if (EC_READ_U8(datagram->data + 1) & 0x81) { // busy bit or
   290 												 // read operation busy
   290 												 // read operation busy
   291         // still busy... timeout?
   291         // still busy... timeout?
   292         if (datagram->cycles_received
   292         unsigned long diff_ms =
   293             - fsm->cycles_start >= (cycles_t) SII_TIMEOUT * cpu_khz) {
   293             (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ;
       
   294         if (diff_ms >= SII_TIMEOUT) {
   294             if (fsm->check_once_more) {
   295             if (fsm->check_once_more) {
   295 				fsm->check_once_more = 0;
   296 				fsm->check_once_more = 0;
   296 			} else {
   297 			} else {
   297                 EC_ERR("SII: Read timeout.\n");
   298                 EC_ERR("SII: Read timeout.\n");
   298                 fsm->state = ec_fsm_sii_state_error;
   299                 fsm->state = ec_fsm_sii_state_error;
   370                 fsm->slave->ring_position);
   371                 fsm->slave->ring_position);
   371         ec_datagram_print_wc_error(datagram);
   372         ec_datagram_print_wc_error(datagram);
   372         return;
   373         return;
   373     }
   374     }
   374 
   375 
   375     fsm->cycles_start = datagram->cycles_sent;
   376     fsm->jiffies_start = datagram->jiffies_sent;
   376     fsm->check_once_more = 1;
   377     fsm->check_once_more = 1;
   377 
   378 
   378     // issue check datagram
   379     // issue check datagram
   379     ec_datagram_fprd(datagram, fsm->slave->station_address, 0x502, 2);
   380     ec_datagram_fprd(datagram, fsm->slave->station_address, 0x502, 2);
   380     fsm->retries = EC_FSM_RETRIES;
   381     fsm->retries = EC_FSM_RETRIES;
   390 void ec_fsm_sii_state_write_check2(
   391 void ec_fsm_sii_state_write_check2(
   391 		ec_fsm_sii_t *fsm /**< finite state machine */
   392 		ec_fsm_sii_t *fsm /**< finite state machine */
   392 		)
   393 		)
   393 {
   394 {
   394     ec_datagram_t *datagram = fsm->datagram;
   395     ec_datagram_t *datagram = fsm->datagram;
       
   396     unsigned long diff_ms;
   395 
   397 
   396     if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--)
   398     if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--)
   397         return;
   399         return;
   398 
   400 
   399     if (datagram->state != EC_DATAGRAM_RECEIVED) {
   401     if (datagram->state != EC_DATAGRAM_RECEIVED) {
   423         return;
   425         return;
   424     }
   426     }
   425 
   427 
   426 	/* FIXME: some slaves never answer with the busy flag set...
   428 	/* FIXME: some slaves never answer with the busy flag set...
   427 	 * wait a few ms for the write operation to complete. */
   429 	 * wait a few ms for the write operation to complete. */
   428 	if (datagram->cycles_received - fsm->cycles_start
   430     diff_ms = (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ;
   429 			< (cycles_t) SII_INHIBIT * cpu_khz) {
   431     if (diff_ms < SII_INHIBIT) {
   430 #ifdef SII_DEBUG
   432 #ifdef SII_DEBUG
   431 		EC_DBG("too early.\n");
   433 		EC_DBG("too early.\n");
   432 #endif
   434 #endif
   433         // issue check datagram again
   435         // issue check datagram again
   434         fsm->retries = EC_FSM_RETRIES;
   436         fsm->retries = EC_FSM_RETRIES;
   436 	}
   438 	}
   437 
   439 
   438     if (EC_READ_U8(datagram->data + 1) & 0x82) { // busy bit or
   440     if (EC_READ_U8(datagram->data + 1) & 0x82) { // busy bit or
   439 												 // write operation busy bit
   441 												 // write operation busy bit
   440         // still busy... timeout?
   442         // still busy... timeout?
   441         if (datagram->cycles_received
   443         if (diff_ms >= SII_TIMEOUT) {
   442             - fsm->cycles_start >= (cycles_t) SII_TIMEOUT * cpu_khz) {
       
   443             if (fsm->check_once_more) {
   444             if (fsm->check_once_more) {
   444 				fsm->check_once_more = 0;
   445 				fsm->check_once_more = 0;
   445 			} else {
   446 			} else {
   446                 EC_ERR("SII: Write timeout.\n");
   447                 EC_ERR("SII: Write timeout.\n");
   447                 fsm->state = ec_fsm_sii_state_error;
   448                 fsm->state = ec_fsm_sii_state_error;