1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2013 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* 82562G 10/100 Network Connection

    30  * 82562G-2 10/100 Network Connection

    31  * 82562GT 10/100 Network Connection

    32  * 82562GT-2 10/100 Network Connection

    33  * 82562V 10/100 Network Connection

    34  * 82562V-2 10/100 Network Connection

    35  * 82566DC-2 Gigabit Network Connection

    36  * 82566DC Gigabit Network Connection

    37  * 82566DM-2 Gigabit Network Connection

    38  * 82566DM Gigabit Network Connection

    39  * 82566MC Gigabit Network Connection

    40  * 82566MM Gigabit Network Connection

    41  * 82567LM Gigabit Network Connection

    42  * 82567LF Gigabit Network Connection

    43  * 82567V Gigabit Network Connection

    44  * 82567LM-2 Gigabit Network Connection

    45  * 82567LF-2 Gigabit Network Connection

    46  * 82567V-2 Gigabit Network Connection

    47  * 82567LF-3 Gigabit Network Connection

    48  * 82567LM-3 Gigabit Network Connection

    49  * 82567LM-4 Gigabit Network Connection

    50  * 82577LM Gigabit Network Connection

    51  * 82577LC Gigabit Network Connection

    52  * 82578DM Gigabit Network Connection

    53  * 82578DC Gigabit Network Connection

    54  * 82579LM Gigabit Network Connection

    55  * 82579V Gigabit Network Connection

    56  */

    57 

    58 #include "e1000-3.10-ethercat.h"

    59 

    60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

    61 /* Offset 04h HSFSTS */

    62 union ich8_hws_flash_status {

    63 	struct ich8_hsfsts {

    64 		u16 flcdone:1;	/* bit 0 Flash Cycle Done */

    65 		u16 flcerr:1;	/* bit 1 Flash Cycle Error */

    66 		u16 dael:1;	/* bit 2 Direct Access error Log */

    67 		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */

    68 		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */

    69 		u16 reserved1:2;	/* bit 13:6 Reserved */

    70 		u16 reserved2:6;	/* bit 13:6 Reserved */

    71 		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */

    72 		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */

    73 	} hsf_status;

    74 	u16 regval;

    75 };

    76 

    77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

    78 /* Offset 06h FLCTL */

    79 union ich8_hws_flash_ctrl {

    80 	struct ich8_hsflctl {

    81 		u16 flcgo:1;	/* 0 Flash Cycle Go */

    82 		u16 flcycle:2;	/* 2:1 Flash Cycle */

    83 		u16 reserved:5;	/* 7:3 Reserved  */

    84 		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */

    85 		u16 flockdn:6;	/* 15:10 Reserved */

    86 	} hsf_ctrl;

    87 	u16 regval;

    88 };

    89 

    90 /* ICH Flash Region Access Permissions */

    91 union ich8_hws_flash_regacc {

    92 	struct ich8_flracc {

    93 		u32 grra:8;	/* 0:7 GbE region Read Access */

    94 		u32 grwa:8;	/* 8:15 GbE region Write Access */

    95 		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */

    96 		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */

    97 	} hsf_flregacc;

    98 	u16 regval;

    99 };

   100 

   101 /* ICH Flash Protected Region */

   102 union ich8_flash_protected_range {

   103 	struct ich8_pr {

   104 		u32 base:13;     /* 0:12 Protected Range Base */

   105 		u32 reserved1:2; /* 13:14 Reserved */

   106 		u32 rpe:1;       /* 15 Read Protection Enable */

   107 		u32 limit:13;    /* 16:28 Protected Range Limit */

   108 		u32 reserved2:2; /* 29:30 Reserved */

   109 		u32 wpe:1;       /* 31 Write Protection Enable */

   110 	} range;

   111 	u32 regval;

   112 };

   113 

   114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   118 						u32 offset, u8 byte);

   119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   120 					 u8 *data);

   121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   122 					 u16 *data);

   123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   124 					 u8 size, u16 *data);

   125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

   142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

   143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   145 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);

   146 

   147 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   148 {

   149 	return readw(hw->flash_address + reg);

   150 }

   151 

   152 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   153 {

   154 	return readl(hw->flash_address + reg);

   155 }

   156 

   157 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   158 {

   159 	writew(val, hw->flash_address + reg);

   160 }

   161 

   162 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   163 {

   164 	writel(val, hw->flash_address + reg);

   165 }

   166 

   167 #define er16flash(reg)		__er16flash(hw, (reg))

   168 #define er32flash(reg)		__er32flash(hw, (reg))

   169 #define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

   170 #define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   171 

   172 /**

   173  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers

   174  *  @hw: pointer to the HW structure

   175  *

   176  *  Test access to the PHY registers by reading the PHY ID registers.  If

   177  *  the PHY ID is already known (e.g. resume path) compare it with known ID,

   178  *  otherwise assume the read PHY ID is correct if it is valid.

   179  *

   180  *  Assumes the sw/fw/hw semaphore is already acquired.

   181  **/

   182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)

   183 {

   184 	u16 phy_reg = 0;

   185 	u32 phy_id = 0;

   186 	s32 ret_val;

   187 	u16 retry_count;

   188 

   189 	for (retry_count = 0; retry_count < 2; retry_count++) {

   190 		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);

   191 		if (ret_val || (phy_reg == 0xFFFF))

   192 			continue;

   193 		phy_id = (u32)(phy_reg << 16);

   194 

   195 		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);

   196 		if (ret_val || (phy_reg == 0xFFFF)) {

   197 			phy_id = 0;

   198 			continue;

   199 		}

   200 		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

   201 		break;

   202 	}

   203 

   204 	if (hw->phy.id) {

   205 		if (hw->phy.id == phy_id)

   206 			return true;

   207 	} else if (phy_id) {

   208 		hw->phy.id = phy_id;

   209 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

   210 		return true;

   211 	}

   212 

   213 	/* In case the PHY needs to be in mdio slow mode,

   214 	 * set slow mode and try to get the PHY id again.

   215 	 */

   216 	hw->phy.ops.release(hw);

   217 	ret_val = e1000_set_mdio_slow_mode_hv(hw);

   218 	if (!ret_val)

   219 		ret_val = e1000e_get_phy_id(hw);

   220 	hw->phy.ops.acquire(hw);

   221 

   222 	return !ret_val;

   223 }

   224 

   225 /**

   226  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds

   227  *  @hw: pointer to the HW structure

   228  *

   229  *  Workarounds/flow necessary for PHY initialization during driver load

   230  *  and resume paths.

   231  **/

   232 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

   233 {

   234 	u32 mac_reg, fwsm = er32(FWSM);

   235 	s32 ret_val;

   236 	u16 phy_reg;

   237 

   238 	/* Gate automatic PHY configuration by hardware on managed and

   239 	 * non-managed 82579 and newer adapters.

   240 	 */

   241 	e1000_gate_hw_phy_config_ich8lan(hw, true);

   242 

   243 	ret_val = hw->phy.ops.acquire(hw);

   244 	if (ret_val) {

   245 		e_dbg("Failed to initialize PHY flow\n");

   246 		goto out;

   247 	}

   248 

   249 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is

   250 	 * inaccessible and resetting the PHY is not blocked, toggle the

   251 	 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   252 	 */

   253 	switch (hw->mac.type) {

   254 	case e1000_pch_lpt:

   255 		if (e1000_phy_is_accessible_pchlan(hw))

   256 			break;

   257 

   258 		/* Before toggling LANPHYPC, see if PHY is accessible by

   259 		 * forcing MAC to SMBus mode first.

   260 		 */

   261 		mac_reg = er32(CTRL_EXT);

   262 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

   263 		ew32(CTRL_EXT, mac_reg);

   264 

   265 		/* fall-through */

   266 	case e1000_pch2lan:

   267 		if (e1000_phy_is_accessible_pchlan(hw)) {

   268 			if (hw->mac.type == e1000_pch_lpt) {

   269 				/* Unforce SMBus mode in PHY */

   270 				e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);

   271 				phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;

   272 				e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

   273 

   274 				/* Unforce SMBus mode in MAC */

   275 				mac_reg = er32(CTRL_EXT);

   276 				mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   277 				ew32(CTRL_EXT, mac_reg);

   278 			}

   279 			break;

   280 		}

   281 

   282 		/* fall-through */

   283 	case e1000_pchlan:

   284 		if ((hw->mac.type == e1000_pchlan) &&

   285 		    (fwsm & E1000_ICH_FWSM_FW_VALID))

   286 			break;

   287 

   288 		if (hw->phy.ops.check_reset_block(hw)) {

   289 			e_dbg("Required LANPHYPC toggle blocked by ME\n");

   290 			break;

   291 		}

   292 

   293 		e_dbg("Toggling LANPHYPC\n");

   294 

   295 		/* Set Phy Config Counter to 50msec */

   296 		mac_reg = er32(FEXTNVM3);

   297 		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

   298 		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

   299 		ew32(FEXTNVM3, mac_reg);

   300 

   301 		if (hw->mac.type == e1000_pch_lpt) {

   302 			/* Toggling LANPHYPC brings the PHY out of SMBus mode

   303 			 * So ensure that the MAC is also out of SMBus mode

   304 			 */

   305 			mac_reg = er32(CTRL_EXT);

   306 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   307 			ew32(CTRL_EXT, mac_reg);

   308 		}

   309 

   310 		/* Toggle LANPHYPC Value bit */

   311 		mac_reg = er32(CTRL);

   312 		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;

   313 		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

   314 		ew32(CTRL, mac_reg);

   315 		e1e_flush();

   316 		usleep_range(10, 20);

   317 		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   318 		ew32(CTRL, mac_reg);

   319 		e1e_flush();

   320 		if (hw->mac.type < e1000_pch_lpt) {

   321 			msleep(50);

   322 		} else {

   323 			u16 count = 20;

   324 			do {

   325 				usleep_range(5000, 10000);

   326 			} while (!(er32(CTRL_EXT) &

   327 				   E1000_CTRL_EXT_LPCD) && count--);

   328 		}

   329 		break;

   330 	default:

   331 		break;

   332 	}

   333 

   334 	hw->phy.ops.release(hw);

   335 

   336 	/* Reset the PHY before any access to it.  Doing so, ensures

   337 	 * that the PHY is in a known good state before we read/write

   338 	 * PHY registers.  The generic reset is sufficient here,

   339 	 * because we haven't determined the PHY type yet.

   340 	 */

   341 	ret_val = e1000e_phy_hw_reset_generic(hw);

   342 

   343 out:

   344 	/* Ungate automatic PHY configuration on non-managed 82579 */

   345 	if ((hw->mac.type == e1000_pch2lan) &&

   346 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   347 		usleep_range(10000, 20000);

   348 		e1000_gate_hw_phy_config_ich8lan(hw, false);

   349 	}

   350 

   351 	return ret_val;

   352 }

   353 

   354 /**

   355  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   356  *  @hw: pointer to the HW structure

   357  *

   358  *  Initialize family-specific PHY parameters and function pointers.

   359  **/

   360 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   361 {

   362 	struct e1000_phy_info *phy = &hw->phy;

   363 	s32 ret_val;

   364 

   365 	phy->addr                     = 1;

   366 	phy->reset_delay_us           = 100;

   367 

   368 	phy->ops.set_page             = e1000_set_page_igp;

   369 	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   370 	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   371 	phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;

   372 	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   373 	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   374 	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   375 	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   376 	phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;

   377 	phy->ops.power_up             = e1000_power_up_phy_copper;

   378 	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   379 	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   380 

   381 	phy->id = e1000_phy_unknown;

   382 

   383 	ret_val = e1000_init_phy_workarounds_pchlan(hw);

   384 	if (ret_val)

   385 		return ret_val;

   386 

   387 	if (phy->id == e1000_phy_unknown)

   388 		switch (hw->mac.type) {

   389 		default:

   390 			ret_val = e1000e_get_phy_id(hw);

   391 			if (ret_val)

   392 				return ret_val;

   393 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   394 				break;

   395 			/* fall-through */

   396 		case e1000_pch2lan:

   397 		case e1000_pch_lpt:

   398 			/* In case the PHY needs to be in mdio slow mode,

   399 			 * set slow mode and try to get the PHY id again.

   400 			 */

   401 			ret_val = e1000_set_mdio_slow_mode_hv(hw);

   402 			if (ret_val)

   403 				return ret_val;

   404 			ret_val = e1000e_get_phy_id(hw);

   405 			if (ret_val)

   406 				return ret_val;

   407 			break;

   408 		}

   409 	phy->type = e1000e_get_phy_type_from_id(phy->id);

   410 

   411 	switch (phy->type) {

   412 	case e1000_phy_82577:

   413 	case e1000_phy_82579:

   414 	case e1000_phy_i217:

   415 		phy->ops.check_polarity = e1000_check_polarity_82577;

   416 		phy->ops.force_speed_duplex =

   417 		    e1000_phy_force_speed_duplex_82577;

   418 		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   419 		phy->ops.get_info = e1000_get_phy_info_82577;

   420 		phy->ops.commit = e1000e_phy_sw_reset;

   421 		break;

   422 	case e1000_phy_82578:

   423 		phy->ops.check_polarity = e1000_check_polarity_m88;

   424 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   425 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   426 		phy->ops.get_info = e1000e_get_phy_info_m88;

   427 		break;

   428 	default:

   429 		ret_val = -E1000_ERR_PHY;

   430 		break;

   431 	}

   432 

   433 	return ret_val;

   434 }

   435 

   436 /**

   437  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   438  *  @hw: pointer to the HW structure

   439  *

   440  *  Initialize family-specific PHY parameters and function pointers.

   441  **/

   442 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   443 {

   444 	struct e1000_phy_info *phy = &hw->phy;

   445 	s32 ret_val;

   446 	u16 i = 0;

   447 

   448 	phy->addr			= 1;

   449 	phy->reset_delay_us		= 100;

   450 

   451 	phy->ops.power_up               = e1000_power_up_phy_copper;

   452 	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

   453 

   454 	/* We may need to do this twice - once for IGP and if that fails,

   455 	 * we'll set BM func pointers and try again

   456 	 */

   457 	ret_val = e1000e_determine_phy_address(hw);

   458 	if (ret_val) {

   459 		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   460 		phy->ops.read_reg  = e1000e_read_phy_reg_bm;

   461 		ret_val = e1000e_determine_phy_address(hw);

   462 		if (ret_val) {

   463 			e_dbg("Cannot determine PHY addr. Erroring out\n");

   464 			return ret_val;

   465 		}

   466 	}

   467 

   468 	phy->id = 0;

   469 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   470 	       (i++ < 100)) {

   471 		usleep_range(1000, 2000);

   472 		ret_val = e1000e_get_phy_id(hw);

   473 		if (ret_val)

   474 			return ret_val;

   475 	}

   476 

   477 	/* Verify phy id */

   478 	switch (phy->id) {

   479 	case IGP03E1000_E_PHY_ID:

   480 		phy->type = e1000_phy_igp_3;

   481 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   482 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   483 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   484 		phy->ops.get_info = e1000e_get_phy_info_igp;

   485 		phy->ops.check_polarity = e1000_check_polarity_igp;

   486 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   487 		break;

   488 	case IFE_E_PHY_ID:

   489 	case IFE_PLUS_E_PHY_ID:

   490 	case IFE_C_E_PHY_ID:

   491 		phy->type = e1000_phy_ife;

   492 		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   493 		phy->ops.get_info = e1000_get_phy_info_ife;

   494 		phy->ops.check_polarity = e1000_check_polarity_ife;

   495 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   496 		break;

   497 	case BME1000_E_PHY_ID:

   498 		phy->type = e1000_phy_bm;

   499 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   500 		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   501 		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   502 		phy->ops.commit = e1000e_phy_sw_reset;

   503 		phy->ops.get_info = e1000e_get_phy_info_m88;

   504 		phy->ops.check_polarity = e1000_check_polarity_m88;

   505 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   506 		break;

   507 	default:

   508 		return -E1000_ERR_PHY;

   509 		break;

   510 	}

   511 

   512 	return 0;

   513 }

   514 

   515 /**

   516  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   517  *  @hw: pointer to the HW structure

   518  *

   519  *  Initialize family-specific NVM parameters and function

   520  *  pointers.

   521  **/

   522 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   523 {

   524 	struct e1000_nvm_info *nvm = &hw->nvm;

   525 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   526 	u32 gfpreg, sector_base_addr, sector_end_addr;

   527 	u16 i;

   528 

   529 	/* Can't read flash registers if the register set isn't mapped. */

   530 	if (!hw->flash_address) {

   531 		e_dbg("ERROR: Flash registers not mapped\n");

   532 		return -E1000_ERR_CONFIG;

   533 	}

   534 

   535 	nvm->type = e1000_nvm_flash_sw;

   536 

   537 	gfpreg = er32flash(ICH_FLASH_GFPREG);

   538 

   539 	/* sector_X_addr is a "sector"-aligned address (4096 bytes)

   540 	 * Add 1 to sector_end_addr since this sector is included in

   541 	 * the overall size.

   542 	 */

   543 	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   544 	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   545 

   546 	/* flash_base_addr is byte-aligned */

   547 	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   548 

   549 	/* find total size of the NVM, then cut in half since the total

   550 	 * size represents two separate NVM banks.

   551 	 */

   552 	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)

   553 				<< FLASH_SECTOR_ADDR_SHIFT);

   554 	nvm->flash_bank_size /= 2;

   555 	/* Adjust to word count */

   556 	nvm->flash_bank_size /= sizeof(u16);

   557 

   558 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;

   559 

   560 	/* Clear shadow ram */

   561 	for (i = 0; i < nvm->word_size; i++) {

   562 		dev_spec->shadow_ram[i].modified = false;

   563 		dev_spec->shadow_ram[i].value    = 0xFFFF;

   564 	}

   565 

   566 	return 0;

   567 }

   568 

   569 /**

   570  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers

   571  *  @hw: pointer to the HW structure

   572  *

   573  *  Initialize family-specific MAC parameters and function

   574  *  pointers.

   575  **/

   576 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)

   577 {

   578 	struct e1000_mac_info *mac = &hw->mac;

   579 

   580 	/* Set media type function pointer */

   581 	hw->phy.media_type = e1000_media_type_copper;

   582 

   583 	/* Set mta register count */

   584 	mac->mta_reg_count = 32;

   585 	/* Set rar entry count */

   586 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;

   587 	if (mac->type == e1000_ich8lan)

   588 		mac->rar_entry_count--;

   589 	/* FWSM register */

   590 	mac->has_fwsm = true;

   591 	/* ARC subsystem not supported */

   592 	mac->arc_subsystem_valid = false;

   593 	/* Adaptive IFS supported */

   594 	mac->adaptive_ifs = true;

   595 

   596 	/* LED and other operations */

   597 	switch (mac->type) {

   598 	case e1000_ich8lan:

   599 	case e1000_ich9lan:

   600 	case e1000_ich10lan:

   601 		/* check management mode */

   602 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;

   603 		/* ID LED init */

   604 		mac->ops.id_led_init = e1000e_id_led_init_generic;

   605 		/* blink LED */

   606 		mac->ops.blink_led = e1000e_blink_led_generic;

   607 		/* setup LED */

   608 		mac->ops.setup_led = e1000e_setup_led_generic;

   609 		/* cleanup LED */

   610 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;

   611 		/* turn on/off LED */

   612 		mac->ops.led_on = e1000_led_on_ich8lan;

   613 		mac->ops.led_off = e1000_led_off_ich8lan;

   614 		break;

   615 	case e1000_pch2lan:

   616 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;

   617 		mac->ops.rar_set = e1000_rar_set_pch2lan;

   618 		/* fall-through */

   619 	case e1000_pch_lpt:

   620 	case e1000_pchlan:

   621 		/* check management mode */

   622 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;

   623 		/* ID LED init */

   624 		mac->ops.id_led_init = e1000_id_led_init_pchlan;

   625 		/* setup LED */

   626 		mac->ops.setup_led = e1000_setup_led_pchlan;

   627 		/* cleanup LED */

   628 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;

   629 		/* turn on/off LED */

   630 		mac->ops.led_on = e1000_led_on_pchlan;

   631 		mac->ops.led_off = e1000_led_off_pchlan;

   632 		break;

   633 	default:

   634 		break;

   635 	}

   636 

   637 	if (mac->type == e1000_pch_lpt) {

   638 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;

   639 		mac->ops.rar_set = e1000_rar_set_pch_lpt;

   640 		mac->ops.setup_physical_interface =

   641 		    e1000_setup_copper_link_pch_lpt;

   642 	}

   643 

   644 	/* Enable PCS Lock-loss workaround for ICH8 */

   645 	if (mac->type == e1000_ich8lan)

   646 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);

   647 

   648 	return 0;

   649 }

   650 

   651 /**

   652  *  __e1000_access_emi_reg_locked - Read/write EMI register

   653  *  @hw: pointer to the HW structure

   654  *  @addr: EMI address to program

   655  *  @data: pointer to value to read/write from/to the EMI address

   656  *  @read: boolean flag to indicate read or write

   657  *

   658  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.

   659  **/

   660 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,

   661 					 u16 *data, bool read)

   662 {

   663 	s32 ret_val;

   664 

   665 	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);

   666 	if (ret_val)

   667 		return ret_val;

   668 

   669 	if (read)

   670 		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);

   671 	else

   672 		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);

   673 

   674 	return ret_val;

   675 }

   676 

   677 /**

   678  *  e1000_read_emi_reg_locked - Read Extended Management Interface register

   679  *  @hw: pointer to the HW structure

   680  *  @addr: EMI address to program

   681  *  @data: value to be read from the EMI address

   682  *

   683  *  Assumes the SW/FW/HW Semaphore is already acquired.

   684  **/

   685 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)

   686 {

   687 	return __e1000_access_emi_reg_locked(hw, addr, data, true);

   688 }

   689 

   690 /**

   691  *  e1000_write_emi_reg_locked - Write Extended Management Interface register

   692  *  @hw: pointer to the HW structure

   693  *  @addr: EMI address to program

   694  *  @data: value to be written to the EMI address

   695  *

   696  *  Assumes the SW/FW/HW Semaphore is already acquired.

   697  **/

   698 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)

   699 {

   700 	return __e1000_access_emi_reg_locked(hw, addr, &data, false);

   701 }

   702 

   703 /**

   704  *  e1000_set_eee_pchlan - Enable/disable EEE support

   705  *  @hw: pointer to the HW structure

   706  *

   707  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of

   708  *  the link and the EEE capabilities of the link partner.  The LPI Control

   709  *  register bits will remain set only if/when link is up.

   710  **/

   711 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)

   712 {

   713 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   714 	s32 ret_val;

   715 	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;

   716 

   717 	switch (hw->phy.type) {

   718 	case e1000_phy_82579:

   719 		lpa = I82579_EEE_LP_ABILITY;

   720 		pcs_status = I82579_EEE_PCS_STATUS;

   721 		adv_addr = I82579_EEE_ADVERTISEMENT;

   722 		break;

   723 	case e1000_phy_i217:

   724 		lpa = I217_EEE_LP_ABILITY;

   725 		pcs_status = I217_EEE_PCS_STATUS;

   726 		adv_addr = I217_EEE_ADVERTISEMENT;

   727 		break;

   728 	default:

   729 		return 0;

   730 	}

   731 

   732 	ret_val = hw->phy.ops.acquire(hw);

   733 	if (ret_val)

   734 		return ret_val;

   735 

   736 	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);

   737 	if (ret_val)

   738 		goto release;

   739 

   740 	/* Clear bits that enable EEE in various speeds */

   741 	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;

   742 

   743 	/* Enable EEE if not disabled by user */

   744 	if (!dev_spec->eee_disable) {

   745 		/* Save off link partner's EEE ability */

   746 		ret_val = e1000_read_emi_reg_locked(hw, lpa,

   747 						    &dev_spec->eee_lp_ability);

   748 		if (ret_val)

   749 			goto release;

   750 

   751 		/* Read EEE advertisement */

   752 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);

   753 		if (ret_val)

   754 			goto release;

   755 

   756 		/* Enable EEE only for speeds in which the link partner is

   757 		 * EEE capable and for which we advertise EEE.

   758 		 */

   759 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)

   760 			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;

   761 

   762 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {

   763 			e1e_rphy_locked(hw, MII_LPA, &data);

   764 			if (data & LPA_100FULL)

   765 				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;

   766 			else

   767 				/* EEE is not supported in 100Half, so ignore

   768 				 * partner's EEE in 100 ability if full-duplex

   769 				 * is not advertised.

   770 				 */

   771 				dev_spec->eee_lp_ability &=

   772 				    ~I82579_EEE_100_SUPPORTED;

   773 		}

   774 	}

   775 

   776 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */

   777 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);

   778 	if (ret_val)

   779 		goto release;

   780 

   781 	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);

   782 release:

   783 	hw->phy.ops.release(hw);

   784 

   785 	return ret_val;

   786 }

   787 

   788 /**

   789  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP

   790  *  @hw:   pointer to the HW structure

   791  *  @link: link up bool flag

   792  *

   793  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications

   794  *  preventing further DMA write requests.  Workaround the issue by disabling

   795  *  the de-assertion of the clock request when in 1Gpbs mode.

   796  **/

   797 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)

   798 {

   799 	u32 fextnvm6 = er32(FEXTNVM6);

   800 	s32 ret_val = 0;

   801 

   802 	if (link && (er32(STATUS) & E1000_STATUS_SPEED_1000)) {

   803 		u16 kmrn_reg;

   804 

   805 		ret_val = hw->phy.ops.acquire(hw);

   806 		if (ret_val)

   807 			return ret_val;

   808 

   809 		ret_val =

   810 		    e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,

   811 						&kmrn_reg);

   812 		if (ret_val)

   813 			goto release;

   814 

   815 		ret_val =

   816 		    e1000e_write_kmrn_reg_locked(hw,

   817 						 E1000_KMRNCTRLSTA_K1_CONFIG,

   818 						 kmrn_reg &

   819 						 ~E1000_KMRNCTRLSTA_K1_ENABLE);

   820 		if (ret_val)

   821 			goto release;

   822 

   823 		usleep_range(10, 20);

   824 

   825 		ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);

   826 

   827 		ret_val =

   828 		    e1000e_write_kmrn_reg_locked(hw,

   829 						 E1000_KMRNCTRLSTA_K1_CONFIG,

   830 						 kmrn_reg);

   831 release:

   832 		hw->phy.ops.release(hw);

   833 	} else {

   834 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */

   835 		ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);

   836 	}

   837 

   838 	return ret_val;

   839 }

   840 

   841 /**

   842  *  e1000_platform_pm_pch_lpt - Set platform power management values

   843  *  @hw: pointer to the HW structure

   844  *  @link: bool indicating link status

   845  *

   846  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"

   847  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed

   848  *  when link is up (which must not exceed the maximum latency supported

   849  *  by the platform), otherwise specify there is no LTR requirement.

   850  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop

   851  *  latencies in the LTR Extended Capability Structure in the PCIe Extended

   852  *  Capability register set, on this device LTR is set by writing the

   853  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and

   854  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)

   855  *  message to the PMC.

   856  **/

   857 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)

   858 {

   859 	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |

   860 	    link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;

   861 	u16 lat_enc = 0;	/* latency encoded */

   862 

   863 	if (link) {

   864 		u16 speed, duplex, scale = 0;

   865 		u16 max_snoop, max_nosnoop;

   866 		u16 max_ltr_enc;	/* max LTR latency encoded */

   867 		s64 lat_ns;	/* latency (ns) */

   868 		s64 value;

   869 		u32 rxa;

   870 

   871 		if (!hw->adapter->max_frame_size) {

   872 			e_dbg("max_frame_size not set.\n");

   873 			return -E1000_ERR_CONFIG;

   874 		}

   875 

   876 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);

   877 		if (!speed) {

   878 			e_dbg("Speed not set.\n");

   879 			return -E1000_ERR_CONFIG;

   880 		}

   881 

   882 		/* Rx Packet Buffer Allocation size (KB) */

   883 		rxa = er32(PBA) & E1000_PBA_RXA_MASK;

   884 

   885 		/* Determine the maximum latency tolerated by the device.

   886 		 *

   887 		 * Per the PCIe spec, the tolerated latencies are encoded as

   888 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by

   889 		 * a 10-bit value (0-1023) to provide a range from 1 ns to

   890 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,

   891 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.

   892 		 */

   893 		lat_ns = ((s64)rxa * 1024 -

   894 			  (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;

   895 		if (lat_ns < 0)

   896 			lat_ns = 0;

   897 		else

   898 			do_div(lat_ns, speed);

   899 

   900 		value = lat_ns;

   901 		while (value > PCI_LTR_VALUE_MASK) {

   902 			scale++;

   903 			value = DIV_ROUND_UP(value, (1 << 5));

   904 		}

   905 		if (scale > E1000_LTRV_SCALE_MAX) {

   906 			e_dbg("Invalid LTR latency scale %d\n", scale);

   907 			return -E1000_ERR_CONFIG;

   908 		}

   909 		lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);

   910 

   911 		/* Determine the maximum latency tolerated by the platform */

   912 		pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,

   913 				     &max_snoop);

   914 		pci_read_config_word(hw->adapter->pdev,

   915 				     E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);

   916 		max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);

   917 

   918 		if (lat_enc > max_ltr_enc)

   919 			lat_enc = max_ltr_enc;

   920 	}

   921 

   922 	/* Set Snoop and No-Snoop latencies the same */

   923 	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);

   924 	ew32(LTRV, reg);

   925 

   926 	return 0;

   927 }

   928 

   929 /**

   930  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)

   931  *  @hw: pointer to the HW structure

   932  *

   933  *  Checks to see of the link status of the hardware has changed.  If a

   934  *  change in link status has been detected, then we read the PHY registers

   935  *  to get the current speed/duplex if link exists.

   936  **/

   937 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)

   938 {

   939 	struct e1000_mac_info *mac = &hw->mac;

   940 	s32 ret_val;

   941 	bool link;

   942 	u16 phy_reg;

   943 

   944 	/* We only want to go out to the PHY registers to see if Auto-Neg

   945 	 * has completed and/or if our link status has changed.  The

   946 	 * get_link_status flag is set upon receiving a Link Status

   947 	 * Change or Rx Sequence Error interrupt.

   948 	 */

   949 	if (!mac->get_link_status)

   950 		return 0;

   951 

   952 	/* First we want to see if the MII Status Register reports

   953 	 * link.  If so, then we want to get the current speed/duplex

   954 	 * of the PHY.

   955 	 */

   956 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   957 	if (ret_val)

   958 		return ret_val;

   959 

   960 	if (hw->mac.type == e1000_pchlan) {

   961 		ret_val = e1000_k1_gig_workaround_hv(hw, link);

   962 		if (ret_val)

   963 			return ret_val;

   964 	}

   965 

   966 	/* When connected at 10Mbps half-duplex, 82579 parts are excessively

   967 	 * aggressive resulting in many collisions. To avoid this, increase

   968 	 * the IPG and reduce Rx latency in the PHY.

   969 	 */

   970 	if ((hw->mac.type == e1000_pch2lan) && link) {

   971 		u32 reg;

   972 		reg = er32(STATUS);

   973 		if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {

   974 			reg = er32(TIPG);

   975 			reg &= ~E1000_TIPG_IPGT_MASK;

   976 			reg |= 0xFF;

   977 			ew32(TIPG, reg);

   978 

   979 			/* Reduce Rx latency in analog PHY */

   980 			ret_val = hw->phy.ops.acquire(hw);

   981 			if (ret_val)

   982 				return ret_val;

   983 

   984 			ret_val =

   985 			    e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);

   986 

   987 			hw->phy.ops.release(hw);

   988 

   989 			if (ret_val)

   990 				return ret_val;

   991 		}

   992 	}

   993 

   994 	/* Work-around I218 hang issue */

   995 	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||

   996 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V)) {

   997 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);

   998 		if (ret_val)

   999 			return ret_val;

  1000 	}

  1001 

  1002 	if (hw->mac.type == e1000_pch_lpt) {

  1003 		/* Set platform power management values for

  1004 		 * Latency Tolerance Reporting (LTR)

  1005 		 */

  1006 		ret_val = e1000_platform_pm_pch_lpt(hw, link);

  1007 		if (ret_val)

  1008 			return ret_val;

  1009 	}

  1010 

  1011 	/* Clear link partner's EEE ability */

  1012 	hw->dev_spec.ich8lan.eee_lp_ability = 0;

  1013 

  1014 	if (!link)

  1015 		return 0; /* No link detected */

  1016 

  1017 	mac->get_link_status = false;

  1018 

  1019 	switch (hw->mac.type) {

  1020 	case e1000_pch2lan:

  1021 		ret_val = e1000_k1_workaround_lv(hw);

  1022 		if (ret_val)

  1023 			return ret_val;

  1024 		/* fall-thru */

  1025 	case e1000_pchlan:

  1026 		if (hw->phy.type == e1000_phy_82578) {

  1027 			ret_val = e1000_link_stall_workaround_hv(hw);

  1028 			if (ret_val)

  1029 				return ret_val;

  1030 		}

  1031 

  1032 		/* Workaround for PCHx parts in half-duplex:

  1033 		 * Set the number of preambles removed from the packet

  1034 		 * when it is passed from the PHY to the MAC to prevent

  1035 		 * the MAC from misinterpreting the packet type.

  1036 		 */

  1037 		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);

  1038 		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;

  1039 

  1040 		if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)

  1041 			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);

  1042 

  1043 		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);

  1044 		break;

  1045 	default:

  1046 		break;

  1047 	}

  1048 

  1049 	/* Check if there was DownShift, must be checked

  1050 	 * immediately after link-up

  1051 	 */

  1052 	e1000e_check_downshift(hw);

  1053 

  1054 	/* Enable/Disable EEE after link up */

  1055 	ret_val = e1000_set_eee_pchlan(hw);

  1056 	if (ret_val)

  1057 		return ret_val;

  1058 

  1059 	/* If we are forcing speed/duplex, then we simply return since

  1060 	 * we have already determined whether we have link or not.

  1061 	 */

  1062 	if (!mac->autoneg)

  1063 		return -E1000_ERR_CONFIG;

  1064 

  1065 	/* Auto-Neg is enabled.  Auto Speed Detection takes care

  1066 	 * of MAC speed/duplex configuration.  So we only need to

  1067 	 * configure Collision Distance in the MAC.

  1068 	 */

  1069 	mac->ops.config_collision_dist(hw);

  1070 

  1071 	/* Configure Flow Control now that Auto-Neg has completed.

  1072 	 * First, we need to restore the desired flow control

  1073 	 * settings because we may have had to re-autoneg with a

  1074 	 * different link partner.

  1075 	 */

  1076 	ret_val = e1000e_config_fc_after_link_up(hw);

  1077 	if (ret_val)

  1078 		e_dbg("Error configuring flow control\n");

  1079 

  1080 	return ret_val;

  1081 }

  1082 

  1083 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)

  1084 {

  1085 	struct e1000_hw *hw = &adapter->hw;

  1086 	s32 rc;

  1087 

  1088 	rc = e1000_init_mac_params_ich8lan(hw);

  1089 	if (rc)

  1090 		return rc;

  1091 

  1092 	rc = e1000_init_nvm_params_ich8lan(hw);

  1093 	if (rc)

  1094 		return rc;

  1095 

  1096 	switch (hw->mac.type) {

  1097 	case e1000_ich8lan:

  1098 	case e1000_ich9lan:

  1099 	case e1000_ich10lan:

  1100 		rc = e1000_init_phy_params_ich8lan(hw);

  1101 		break;

  1102 	case e1000_pchlan:

  1103 	case e1000_pch2lan:

  1104 	case e1000_pch_lpt:

  1105 		rc = e1000_init_phy_params_pchlan(hw);

  1106 		break;

  1107 	default:

  1108 		break;

  1109 	}

  1110 	if (rc)

  1111 		return rc;

  1112 

  1113 	/* Disable Jumbo Frame support on parts with Intel 10/100 PHY or

  1114 	 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).

  1115 	 */

  1116 	if ((adapter->hw.phy.type == e1000_phy_ife) ||

  1117 	    ((adapter->hw.mac.type >= e1000_pch2lan) &&

  1118 	     (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {

  1119 		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;

  1120 		adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;

  1121 

  1122 		hw->mac.ops.blink_led = NULL;

  1123 	}

  1124 

  1125 	if ((adapter->hw.mac.type == e1000_ich8lan) &&

  1126 	    (adapter->hw.phy.type != e1000_phy_ife))

  1127 		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;

  1128 

  1129 	/* Enable workaround for 82579 w/ ME enabled */

  1130 	if ((adapter->hw.mac.type == e1000_pch2lan) &&

  1131 	    (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))

  1132 		adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;

  1133 

  1134 	return 0;

  1135 }

  1136