devices/forcedeth-2.6.19-ethercat.c
changeset 583 172d42146930
child 586 99df3f4d8d76
equal deleted inserted replaced
582:39f1704b0c99 583:172d42146930
       
     1 /*
       
     2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
       
     3  *
       
     4  * Note: This driver is a cleanroom reimplementation based on reverse
       
     5  *      engineered documentation written by Carl-Daniel Hailfinger
       
     6  *      and Andrew de Quincey. It's neither supported nor endorsed
       
     7  *      by NVIDIA Corp. Use at your own risk.
       
     8  *
       
     9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
       
    10  * trademarks of NVIDIA Corporation in the United States and other
       
    11  * countries.
       
    12  *
       
    13  * Copyright (C) 2003,4,5 Manfred Spraul
       
    14  * Copyright (C) 2004 Andrew de Quincey (wol support)
       
    15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
       
    16  *		IRQ rate fixes, bigendian fixes, cleanups, verification)
       
    17  * Copyright (c) 2004 NVIDIA Corporation
       
    18  *
       
    19  * This program is free software; you can redistribute it and/or modify
       
    20  * it under the terms of the GNU General Public License as published by
       
    21  * the Free Software Foundation; either version 2 of the License, or
       
    22  * (at your option) any later version.
       
    23  *
       
    24  * This program is distributed in the hope that it will be useful,
       
    25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
       
    26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
       
    27  * GNU General Public License for more details.
       
    28  *
       
    29  * You should have received a copy of the GNU General Public License
       
    30  * along with this program; if not, write to the Free Software
       
    31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
       
    32  *
       
    33  * Changelog:
       
    34  * 	0.01: 05 Oct 2003: First release that compiles without warnings.
       
    35  * 	0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
       
    36  * 			   Check all PCI BARs for the register window.
       
    37  * 			   udelay added to mii_rw.
       
    38  * 	0.03: 06 Oct 2003: Initialize dev->irq.
       
    39  * 	0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
       
    40  * 	0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
       
    41  * 	0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
       
    42  * 			   irq mask updated
       
    43  * 	0.07: 14 Oct 2003: Further irq mask updates.
       
    44  * 	0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
       
    45  * 			   added into irq handler, NULL check for drain_ring.
       
    46  * 	0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
       
    47  * 			   requested interrupt sources.
       
    48  * 	0.10: 20 Oct 2003: First cleanup for release.
       
    49  * 	0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
       
    50  * 			   MAC Address init fix, set_multicast cleanup.
       
    51  * 	0.12: 23 Oct 2003: Cleanups for release.
       
    52  * 	0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
       
    53  * 			   Set link speed correctly. start rx before starting
       
    54  * 			   tx (nv_start_rx sets the link speed).
       
    55  * 	0.14: 25 Oct 2003: Nic dependant irq mask.
       
    56  * 	0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
       
    57  * 			   open.
       
    58  * 	0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
       
    59  * 			   increased to 1628 bytes.
       
    60  * 	0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
       
    61  * 			   the tx length.
       
    62  * 	0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
       
    63  * 	0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
       
    64  * 			   addresses, really stop rx if already running
       
    65  * 			   in nv_start_rx, clean up a bit.
       
    66  * 	0.20: 07 Dec 2003: alloc fixes
       
    67  * 	0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
       
    68  *	0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
       
    69  *			   on close.
       
    70  *	0.23: 26 Jan 2004: various small cleanups
       
    71  *	0.24: 27 Feb 2004: make driver even less anonymous in backtraces
       
    72  *	0.25: 09 Mar 2004: wol support
       
    73  *	0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
       
    74  *	0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
       
    75  *			   added CK804/MCP04 device IDs, code fixes
       
    76  *			   for registers, link status and other minor fixes.
       
    77  *	0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
       
    78  *	0.29: 31 Aug 2004: Add backup timer for link change notification.
       
    79  *	0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
       
    80  *			   into nv_close, otherwise reenabling for wol can
       
    81  *			   cause DMA to kfree'd memory.
       
    82  *	0.31: 14 Nov 2004: ethtool support for getting/setting link
       
    83  *			   capabilities.
       
    84  *	0.32: 16 Apr 2005: RX_ERROR4 handling added.
       
    85  *	0.33: 16 May 2005: Support for MCP51 added.
       
    86  *	0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
       
    87  *	0.35: 26 Jun 2005: Support for MCP55 added.
       
    88  *	0.36: 28 Jun 2005: Add jumbo frame support.
       
    89  *	0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
       
    90  *	0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
       
    91  *			   per-packet flags.
       
    92  *	0.39: 18 Jul 2005: Add 64bit descriptor support.
       
    93  *	0.40: 19 Jul 2005: Add support for mac address change.
       
    94  *	0.41: 30 Jul 2005: Write back original MAC in nv_close instead
       
    95  *			   of nv_remove
       
    96  *	0.42: 06 Aug 2005: Fix lack of link speed initialization
       
    97  *			   in the second (and later) nv_open call
       
    98  *	0.43: 10 Aug 2005: Add support for tx checksum.
       
    99  *	0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
       
   100  *	0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
       
   101  *	0.46: 20 Oct 2005: Add irq optimization modes.
       
   102  *	0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
       
   103  *	0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
       
   104  *	0.49: 10 Dec 2005: Fix tso for large buffers.
       
   105  *	0.50: 20 Jan 2006: Add 8021pq tagging support.
       
   106  *	0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
       
   107  *	0.52: 20 Jan 2006: Add MSI/MSIX support.
       
   108  *	0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
       
   109  *	0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
       
   110  *	0.55: 22 Mar 2006: Add flow control (pause frame).
       
   111  *	0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
       
   112  *	0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
       
   113  *
       
   114  * Known bugs:
       
   115  * We suspect that on some hardware no TX done interrupts are generated.
       
   116  * This means recovery from netif_stop_queue only happens if the hw timer
       
   117  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
       
   118  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
       
   119  * If your hardware reliably generates tx done interrupts, then you can remove
       
   120  * DEV_NEED_TIMERIRQ from the driver_data flags.
       
   121  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
       
   122  * superfluous timer interrupts from the nic.
       
   123  */
       
   124 #ifdef CONFIG_FORCEDETH_NAPI
       
   125 #define DRIVERNAPI "-NAPI"
       
   126 #else
       
   127 #define DRIVERNAPI
       
   128 #endif
       
   129 #define FORCEDETH_VERSION		"0.57"
       
   130 #define DRV_NAME			"forcedeth"
       
   131 
       
   132 #include <linux/module.h>
       
   133 #include <linux/types.h>
       
   134 #include <linux/pci.h>
       
   135 #include <linux/interrupt.h>
       
   136 #include <linux/netdevice.h>
       
   137 #include <linux/etherdevice.h>
       
   138 #include <linux/delay.h>
       
   139 #include <linux/spinlock.h>
       
   140 #include <linux/ethtool.h>
       
   141 #include <linux/timer.h>
       
   142 #include <linux/skbuff.h>
       
   143 #include <linux/mii.h>
       
   144 #include <linux/random.h>
       
   145 #include <linux/init.h>
       
   146 #include <linux/if_vlan.h>
       
   147 #include <linux/dma-mapping.h>
       
   148 
       
   149 #include <asm/irq.h>
       
   150 #include <asm/io.h>
       
   151 #include <asm/uaccess.h>
       
   152 #include <asm/system.h>
       
   153 
       
   154 #include "../globals.h"
       
   155 #include "ecdev.h"
       
   156 
       
   157 #if 0
       
   158 #define dprintk			printk
       
   159 #else
       
   160 #define dprintk(x...)		do { } while (0)
       
   161 #endif
       
   162 
       
   163 
       
   164 /*
       
   165  * Hardware access:
       
   166  */
       
   167 
       
   168 #define DEV_NEED_TIMERIRQ	0x0001  /* set the timer irq flag in the irq mask */
       
   169 #define DEV_NEED_LINKTIMER	0x0002	/* poll link settings. Relies on the timer irq */
       
   170 #define DEV_HAS_LARGEDESC	0x0004	/* device supports jumbo frames and needs packet format 2 */
       
   171 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
       
   172 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
       
   173 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
       
   174 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
       
   175 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
       
   176 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
       
   177 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
       
   178 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
       
   179 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
       
   180 
       
   181 enum {
       
   182 	NvRegIrqStatus = 0x000,
       
   183 #define NVREG_IRQSTAT_MIIEVENT	0x040
       
   184 #define NVREG_IRQSTAT_MASK		0x1ff
       
   185 	NvRegIrqMask = 0x004,
       
   186 #define NVREG_IRQ_RX_ERROR		0x0001
       
   187 #define NVREG_IRQ_RX			0x0002
       
   188 #define NVREG_IRQ_RX_NOBUF		0x0004
       
   189 #define NVREG_IRQ_TX_ERR		0x0008
       
   190 #define NVREG_IRQ_TX_OK			0x0010
       
   191 #define NVREG_IRQ_TIMER			0x0020
       
   192 #define NVREG_IRQ_LINK			0x0040
       
   193 #define NVREG_IRQ_RX_FORCED		0x0080
       
   194 #define NVREG_IRQ_TX_FORCED		0x0100
       
   195 #define NVREG_IRQMASK_THROUGHPUT	0x00df
       
   196 #define NVREG_IRQMASK_CPU		0x0040
       
   197 #define NVREG_IRQ_TX_ALL		(NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
       
   198 #define NVREG_IRQ_RX_ALL		(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
       
   199 #define NVREG_IRQ_OTHER			(NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
       
   200 
       
   201 #define NVREG_IRQ_UNKNOWN	(~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
       
   202 					NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
       
   203 					NVREG_IRQ_TX_FORCED))
       
   204 
       
   205 	NvRegUnknownSetupReg6 = 0x008,
       
   206 #define NVREG_UNKSETUP6_VAL		3
       
   207 
       
   208 /*
       
   209  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
       
   210  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
       
   211  */
       
   212 	NvRegPollingInterval = 0x00c,
       
   213 #define NVREG_POLL_DEFAULT_THROUGHPUT	970
       
   214 #define NVREG_POLL_DEFAULT_CPU	13
       
   215 	NvRegMSIMap0 = 0x020,
       
   216 	NvRegMSIMap1 = 0x024,
       
   217 	NvRegMSIIrqMask = 0x030,
       
   218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
       
   219 	NvRegMisc1 = 0x080,
       
   220 #define NVREG_MISC1_PAUSE_TX	0x01
       
   221 #define NVREG_MISC1_HD		0x02
       
   222 #define NVREG_MISC1_FORCE	0x3b0f3c
       
   223 
       
   224 	NvRegMacReset = 0x3c,
       
   225 #define NVREG_MAC_RESET_ASSERT	0x0F3
       
   226 	NvRegTransmitterControl = 0x084,
       
   227 #define NVREG_XMITCTL_START	0x01
       
   228 	NvRegTransmitterStatus = 0x088,
       
   229 #define NVREG_XMITSTAT_BUSY	0x01
       
   230 
       
   231 	NvRegPacketFilterFlags = 0x8c,
       
   232 #define NVREG_PFF_PAUSE_RX	0x08
       
   233 #define NVREG_PFF_ALWAYS	0x7F0000
       
   234 #define NVREG_PFF_PROMISC	0x80
       
   235 #define NVREG_PFF_MYADDR	0x20
       
   236 #define NVREG_PFF_LOOPBACK	0x10
       
   237 
       
   238 	NvRegOffloadConfig = 0x90,
       
   239 #define NVREG_OFFLOAD_HOMEPHY	0x601
       
   240 #define NVREG_OFFLOAD_NORMAL	RX_NIC_BUFSIZE
       
   241 	NvRegReceiverControl = 0x094,
       
   242 #define NVREG_RCVCTL_START	0x01
       
   243 	NvRegReceiverStatus = 0x98,
       
   244 #define NVREG_RCVSTAT_BUSY	0x01
       
   245 
       
   246 	NvRegRandomSeed = 0x9c,
       
   247 #define NVREG_RNDSEED_MASK	0x00ff
       
   248 #define NVREG_RNDSEED_FORCE	0x7f00
       
   249 #define NVREG_RNDSEED_FORCE2	0x2d00
       
   250 #define NVREG_RNDSEED_FORCE3	0x7400
       
   251 
       
   252 	NvRegTxDeferral = 0xA0,
       
   253 #define NVREG_TX_DEFERRAL_DEFAULT	0x15050f
       
   254 #define NVREG_TX_DEFERRAL_RGMII_10_100	0x16070f
       
   255 #define NVREG_TX_DEFERRAL_RGMII_1000	0x14050f
       
   256 	NvRegRxDeferral = 0xA4,
       
   257 #define NVREG_RX_DEFERRAL_DEFAULT	0x16
       
   258 	NvRegMacAddrA = 0xA8,
       
   259 	NvRegMacAddrB = 0xAC,
       
   260 	NvRegMulticastAddrA = 0xB0,
       
   261 #define NVREG_MCASTADDRA_FORCE	0x01
       
   262 	NvRegMulticastAddrB = 0xB4,
       
   263 	NvRegMulticastMaskA = 0xB8,
       
   264 	NvRegMulticastMaskB = 0xBC,
       
   265 
       
   266 	NvRegPhyInterface = 0xC0,
       
   267 #define PHY_RGMII		0x10000000
       
   268 
       
   269 	NvRegTxRingPhysAddr = 0x100,
       
   270 	NvRegRxRingPhysAddr = 0x104,
       
   271 	NvRegRingSizes = 0x108,
       
   272 #define NVREG_RINGSZ_TXSHIFT 0
       
   273 #define NVREG_RINGSZ_RXSHIFT 16
       
   274 	NvRegTransmitPoll = 0x10c,
       
   275 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV	0x00008000
       
   276 	NvRegLinkSpeed = 0x110,
       
   277 #define NVREG_LINKSPEED_FORCE 0x10000
       
   278 #define NVREG_LINKSPEED_10	1000
       
   279 #define NVREG_LINKSPEED_100	100
       
   280 #define NVREG_LINKSPEED_1000	50
       
   281 #define NVREG_LINKSPEED_MASK	(0xFFF)
       
   282 	NvRegUnknownSetupReg5 = 0x130,
       
   283 #define NVREG_UNKSETUP5_BIT31	(1<<31)
       
   284 	NvRegTxWatermark = 0x13c,
       
   285 #define NVREG_TX_WM_DESC1_DEFAULT	0x0200010
       
   286 #define NVREG_TX_WM_DESC2_3_DEFAULT	0x1e08000
       
   287 #define NVREG_TX_WM_DESC2_3_1000	0xfe08000
       
   288 	NvRegTxRxControl = 0x144,
       
   289 #define NVREG_TXRXCTL_KICK	0x0001
       
   290 #define NVREG_TXRXCTL_BIT1	0x0002
       
   291 #define NVREG_TXRXCTL_BIT2	0x0004
       
   292 #define NVREG_TXRXCTL_IDLE	0x0008
       
   293 #define NVREG_TXRXCTL_RESET	0x0010
       
   294 #define NVREG_TXRXCTL_RXCHECK	0x0400
       
   295 #define NVREG_TXRXCTL_DESC_1	0
       
   296 #define NVREG_TXRXCTL_DESC_2	0x02100
       
   297 #define NVREG_TXRXCTL_DESC_3	0x02200
       
   298 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
       
   299 #define NVREG_TXRXCTL_VLANINS	0x00080
       
   300 	NvRegTxRingPhysAddrHigh = 0x148,
       
   301 	NvRegRxRingPhysAddrHigh = 0x14C,
       
   302 	NvRegTxPauseFrame = 0x170,
       
   303 #define NVREG_TX_PAUSEFRAME_DISABLE	0x1ff0080
       
   304 #define NVREG_TX_PAUSEFRAME_ENABLE	0x0c00030
       
   305 	NvRegMIIStatus = 0x180,
       
   306 #define NVREG_MIISTAT_ERROR		0x0001
       
   307 #define NVREG_MIISTAT_LINKCHANGE	0x0008
       
   308 #define NVREG_MIISTAT_MASK		0x000f
       
   309 #define NVREG_MIISTAT_MASK2		0x000f
       
   310 	NvRegUnknownSetupReg4 = 0x184,
       
   311 #define NVREG_UNKSETUP4_VAL	8
       
   312 
       
   313 	NvRegAdapterControl = 0x188,
       
   314 #define NVREG_ADAPTCTL_START	0x02
       
   315 #define NVREG_ADAPTCTL_LINKUP	0x04
       
   316 #define NVREG_ADAPTCTL_PHYVALID	0x40000
       
   317 #define NVREG_ADAPTCTL_RUNNING	0x100000
       
   318 #define NVREG_ADAPTCTL_PHYSHIFT	24
       
   319 	NvRegMIISpeed = 0x18c,
       
   320 #define NVREG_MIISPEED_BIT8	(1<<8)
       
   321 #define NVREG_MIIDELAY	5
       
   322 	NvRegMIIControl = 0x190,
       
   323 #define NVREG_MIICTL_INUSE	0x08000
       
   324 #define NVREG_MIICTL_WRITE	0x00400
       
   325 #define NVREG_MIICTL_ADDRSHIFT	5
       
   326 	NvRegMIIData = 0x194,
       
   327 	NvRegWakeUpFlags = 0x200,
       
   328 #define NVREG_WAKEUPFLAGS_VAL		0x7770
       
   329 #define NVREG_WAKEUPFLAGS_BUSYSHIFT	24
       
   330 #define NVREG_WAKEUPFLAGS_ENABLESHIFT	16
       
   331 #define NVREG_WAKEUPFLAGS_D3SHIFT	12
       
   332 #define NVREG_WAKEUPFLAGS_D2SHIFT	8
       
   333 #define NVREG_WAKEUPFLAGS_D1SHIFT	4
       
   334 #define NVREG_WAKEUPFLAGS_D0SHIFT	0
       
   335 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT		0x01
       
   336 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT	0x02
       
   337 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE	0x04
       
   338 #define NVREG_WAKEUPFLAGS_ENABLE	0x1111
       
   339 
       
   340 	NvRegPatternCRC = 0x204,
       
   341 	NvRegPatternMask = 0x208,
       
   342 	NvRegPowerCap = 0x268,
       
   343 #define NVREG_POWERCAP_D3SUPP	(1<<30)
       
   344 #define NVREG_POWERCAP_D2SUPP	(1<<26)
       
   345 #define NVREG_POWERCAP_D1SUPP	(1<<25)
       
   346 	NvRegPowerState = 0x26c,
       
   347 #define NVREG_POWERSTATE_POWEREDUP	0x8000
       
   348 #define NVREG_POWERSTATE_VALID		0x0100
       
   349 #define NVREG_POWERSTATE_MASK		0x0003
       
   350 #define NVREG_POWERSTATE_D0		0x0000
       
   351 #define NVREG_POWERSTATE_D1		0x0001
       
   352 #define NVREG_POWERSTATE_D2		0x0002
       
   353 #define NVREG_POWERSTATE_D3		0x0003
       
   354 	NvRegTxCnt = 0x280,
       
   355 	NvRegTxZeroReXmt = 0x284,
       
   356 	NvRegTxOneReXmt = 0x288,
       
   357 	NvRegTxManyReXmt = 0x28c,
       
   358 	NvRegTxLateCol = 0x290,
       
   359 	NvRegTxUnderflow = 0x294,
       
   360 	NvRegTxLossCarrier = 0x298,
       
   361 	NvRegTxExcessDef = 0x29c,
       
   362 	NvRegTxRetryErr = 0x2a0,
       
   363 	NvRegRxFrameErr = 0x2a4,
       
   364 	NvRegRxExtraByte = 0x2a8,
       
   365 	NvRegRxLateCol = 0x2ac,
       
   366 	NvRegRxRunt = 0x2b0,
       
   367 	NvRegRxFrameTooLong = 0x2b4,
       
   368 	NvRegRxOverflow = 0x2b8,
       
   369 	NvRegRxFCSErr = 0x2bc,
       
   370 	NvRegRxFrameAlignErr = 0x2c0,
       
   371 	NvRegRxLenErr = 0x2c4,
       
   372 	NvRegRxUnicast = 0x2c8,
       
   373 	NvRegRxMulticast = 0x2cc,
       
   374 	NvRegRxBroadcast = 0x2d0,
       
   375 	NvRegTxDef = 0x2d4,
       
   376 	NvRegTxFrame = 0x2d8,
       
   377 	NvRegRxCnt = 0x2dc,
       
   378 	NvRegTxPause = 0x2e0,
       
   379 	NvRegRxPause = 0x2e4,
       
   380 	NvRegRxDropFrame = 0x2e8,
       
   381 	NvRegVlanControl = 0x300,
       
   382 #define NVREG_VLANCONTROL_ENABLE	0x2000
       
   383 	NvRegMSIXMap0 = 0x3e0,
       
   384 	NvRegMSIXMap1 = 0x3e4,
       
   385 	NvRegMSIXIrqStatus = 0x3f0,
       
   386 
       
   387 	NvRegPowerState2 = 0x600,
       
   388 #define NVREG_POWERSTATE2_POWERUP_MASK		0x0F11
       
   389 #define NVREG_POWERSTATE2_POWERUP_REV_A3	0x0001
       
   390 };
       
   391 
       
   392 /* Big endian: should work, but is untested */
       
   393 struct ring_desc {
       
   394 	__le32 buf;
       
   395 	__le32 flaglen;
       
   396 };
       
   397 
       
   398 struct ring_desc_ex {
       
   399 	__le32 bufhigh;
       
   400 	__le32 buflow;
       
   401 	__le32 txvlan;
       
   402 	__le32 flaglen;
       
   403 };
       
   404 
       
   405 union ring_type {
       
   406 	struct ring_desc* orig;
       
   407 	struct ring_desc_ex* ex;
       
   408 };
       
   409 
       
   410 #define FLAG_MASK_V1 0xffff0000
       
   411 #define FLAG_MASK_V2 0xffffc000
       
   412 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
       
   413 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
       
   414 
       
   415 #define NV_TX_LASTPACKET	(1<<16)
       
   416 #define NV_TX_RETRYERROR	(1<<19)
       
   417 #define NV_TX_FORCED_INTERRUPT	(1<<24)
       
   418 #define NV_TX_DEFERRED		(1<<26)
       
   419 #define NV_TX_CARRIERLOST	(1<<27)
       
   420 #define NV_TX_LATECOLLISION	(1<<28)
       
   421 #define NV_TX_UNDERFLOW		(1<<29)
       
   422 #define NV_TX_ERROR		(1<<30)
       
   423 #define NV_TX_VALID		(1<<31)
       
   424 
       
   425 #define NV_TX2_LASTPACKET	(1<<29)
       
   426 #define NV_TX2_RETRYERROR	(1<<18)
       
   427 #define NV_TX2_FORCED_INTERRUPT	(1<<30)
       
   428 #define NV_TX2_DEFERRED		(1<<25)
       
   429 #define NV_TX2_CARRIERLOST	(1<<26)
       
   430 #define NV_TX2_LATECOLLISION	(1<<27)
       
   431 #define NV_TX2_UNDERFLOW	(1<<28)
       
   432 /* error and valid are the same for both */
       
   433 #define NV_TX2_ERROR		(1<<30)
       
   434 #define NV_TX2_VALID		(1<<31)
       
   435 #define NV_TX2_TSO		(1<<28)
       
   436 #define NV_TX2_TSO_SHIFT	14
       
   437 #define NV_TX2_TSO_MAX_SHIFT	14
       
   438 #define NV_TX2_TSO_MAX_SIZE	(1<<NV_TX2_TSO_MAX_SHIFT)
       
   439 #define NV_TX2_CHECKSUM_L3	(1<<27)
       
   440 #define NV_TX2_CHECKSUM_L4	(1<<26)
       
   441 
       
   442 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
       
   443 
       
   444 #define NV_RX_DESCRIPTORVALID	(1<<16)
       
   445 #define NV_RX_MISSEDFRAME	(1<<17)
       
   446 #define NV_RX_SUBSTRACT1	(1<<18)
       
   447 #define NV_RX_ERROR1		(1<<23)
       
   448 #define NV_RX_ERROR2		(1<<24)
       
   449 #define NV_RX_ERROR3		(1<<25)
       
   450 #define NV_RX_ERROR4		(1<<26)
       
   451 #define NV_RX_CRCERR		(1<<27)
       
   452 #define NV_RX_OVERFLOW		(1<<28)
       
   453 #define NV_RX_FRAMINGERR	(1<<29)
       
   454 #define NV_RX_ERROR		(1<<30)
       
   455 #define NV_RX_AVAIL		(1<<31)
       
   456 
       
   457 #define NV_RX2_CHECKSUMMASK	(0x1C000000)
       
   458 #define NV_RX2_CHECKSUMOK1	(0x10000000)
       
   459 #define NV_RX2_CHECKSUMOK2	(0x14000000)
       
   460 #define NV_RX2_CHECKSUMOK3	(0x18000000)
       
   461 #define NV_RX2_DESCRIPTORVALID	(1<<29)
       
   462 #define NV_RX2_SUBSTRACT1	(1<<25)
       
   463 #define NV_RX2_ERROR1		(1<<18)
       
   464 #define NV_RX2_ERROR2		(1<<19)
       
   465 #define NV_RX2_ERROR3		(1<<20)
       
   466 #define NV_RX2_ERROR4		(1<<21)
       
   467 #define NV_RX2_CRCERR		(1<<22)
       
   468 #define NV_RX2_OVERFLOW		(1<<23)
       
   469 #define NV_RX2_FRAMINGERR	(1<<24)
       
   470 /* error and avail are the same for both */
       
   471 #define NV_RX2_ERROR		(1<<30)
       
   472 #define NV_RX2_AVAIL		(1<<31)
       
   473 
       
   474 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
       
   475 #define NV_RX3_VLAN_TAG_MASK	(0x0000FFFF)
       
   476 
       
   477 /* Miscelaneous hardware related defines: */
       
   478 #define NV_PCI_REGSZ_VER1      	0x270
       
   479 #define NV_PCI_REGSZ_VER2      	0x604
       
   480 
       
   481 /* various timeout delays: all in usec */
       
   482 #define NV_TXRX_RESET_DELAY	4
       
   483 #define NV_TXSTOP_DELAY1	10
       
   484 #define NV_TXSTOP_DELAY1MAX	500000
       
   485 #define NV_TXSTOP_DELAY2	100
       
   486 #define NV_RXSTOP_DELAY1	10
       
   487 #define NV_RXSTOP_DELAY1MAX	500000
       
   488 #define NV_RXSTOP_DELAY2	100
       
   489 #define NV_SETUP5_DELAY		5
       
   490 #define NV_SETUP5_DELAYMAX	50000
       
   491 #define NV_POWERUP_DELAY	5
       
   492 #define NV_POWERUP_DELAYMAX	5000
       
   493 #define NV_MIIBUSY_DELAY	50
       
   494 #define NV_MIIPHY_DELAY	10
       
   495 #define NV_MIIPHY_DELAYMAX	10000
       
   496 #define NV_MAC_RESET_DELAY	64
       
   497 
       
   498 #define NV_WAKEUPPATTERNS	5
       
   499 #define NV_WAKEUPMASKENTRIES	4
       
   500 
       
   501 /* General driver defaults */
       
   502 #define NV_WATCHDOG_TIMEO	(5*HZ)
       
   503 
       
   504 #define RX_RING_DEFAULT		128
       
   505 #define TX_RING_DEFAULT		256
       
   506 #define RX_RING_MIN		128
       
   507 #define TX_RING_MIN		64
       
   508 #define RING_MAX_DESC_VER_1	1024
       
   509 #define RING_MAX_DESC_VER_2_3	16384
       
   510 /*
       
   511  * Difference between the get and put pointers for the tx ring.
       
   512  * This is used to throttle the amount of data outstanding in the
       
   513  * tx ring.
       
   514  */
       
   515 #define TX_LIMIT_DIFFERENCE	1
       
   516 
       
   517 /* rx/tx mac addr + type + vlan + align + slack*/
       
   518 #define NV_RX_HEADERS		(64)
       
   519 /* even more slack. */
       
   520 #define NV_RX_ALLOC_PAD		(64)
       
   521 
       
   522 /* maximum mtu size */
       
   523 #define NV_PKTLIMIT_1	ETH_DATA_LEN	/* hard limit not known */
       
   524 #define NV_PKTLIMIT_2	9100	/* Actual limit according to NVidia: 9202 */
       
   525 
       
   526 #define OOM_REFILL	(1+HZ/20)
       
   527 #define POLL_WAIT	(1+HZ/100)
       
   528 #define LINK_TIMEOUT	(3*HZ)
       
   529 #define STATS_INTERVAL	(10*HZ)
       
   530 
       
   531 /*
       
   532  * desc_ver values:
       
   533  * The nic supports three different descriptor types:
       
   534  * - DESC_VER_1: Original
       
   535  * - DESC_VER_2: support for jumbo frames.
       
   536  * - DESC_VER_3: 64-bit format.
       
   537  */
       
   538 #define DESC_VER_1	1
       
   539 #define DESC_VER_2	2
       
   540 #define DESC_VER_3	3
       
   541 
       
   542 /* PHY defines */
       
   543 #define PHY_OUI_MARVELL	0x5043
       
   544 #define PHY_OUI_CICADA	0x03f1
       
   545 #define PHYID1_OUI_MASK	0x03ff
       
   546 #define PHYID1_OUI_SHFT	6
       
   547 #define PHYID2_OUI_MASK	0xfc00
       
   548 #define PHYID2_OUI_SHFT	10
       
   549 #define PHYID2_MODEL_MASK		0x03f0
       
   550 #define PHY_MODEL_MARVELL_E3016		0x220
       
   551 #define PHY_MARVELL_E3016_INITMASK	0x0300
       
   552 #define PHY_INIT1	0x0f000
       
   553 #define PHY_INIT2	0x0e00
       
   554 #define PHY_INIT3	0x01000
       
   555 #define PHY_INIT4	0x0200
       
   556 #define PHY_INIT5	0x0004
       
   557 #define PHY_INIT6	0x02000
       
   558 #define PHY_GIGABIT	0x0100
       
   559 
       
   560 #define PHY_TIMEOUT	0x1
       
   561 #define PHY_ERROR	0x2
       
   562 
       
   563 #define PHY_100	0x1
       
   564 #define PHY_1000	0x2
       
   565 #define PHY_HALF	0x100
       
   566 
       
   567 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
       
   568 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
       
   569 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
       
   570 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
       
   571 #define NV_PAUSEFRAME_RX_REQ     0x0010
       
   572 #define NV_PAUSEFRAME_TX_REQ     0x0020
       
   573 #define NV_PAUSEFRAME_AUTONEG    0x0040
       
   574 
       
   575 /* MSI/MSI-X defines */
       
   576 #define NV_MSI_X_MAX_VECTORS  8
       
   577 #define NV_MSI_X_VECTORS_MASK 0x000f
       
   578 #define NV_MSI_CAPABLE        0x0010
       
   579 #define NV_MSI_X_CAPABLE      0x0020
       
   580 #define NV_MSI_ENABLED        0x0040
       
   581 #define NV_MSI_X_ENABLED      0x0080
       
   582 
       
   583 #define NV_MSI_X_VECTOR_ALL   0x0
       
   584 #define NV_MSI_X_VECTOR_RX    0x0
       
   585 #define NV_MSI_X_VECTOR_TX    0x1
       
   586 #define NV_MSI_X_VECTOR_OTHER 0x2
       
   587 
       
   588 /* statistics */
       
   589 struct nv_ethtool_str {
       
   590 	char name[ETH_GSTRING_LEN];
       
   591 };
       
   592 
       
   593 static const struct nv_ethtool_str nv_estats_str[] = {
       
   594 	{ "tx_bytes" },
       
   595 	{ "tx_zero_rexmt" },
       
   596 	{ "tx_one_rexmt" },
       
   597 	{ "tx_many_rexmt" },
       
   598 	{ "tx_late_collision" },
       
   599 	{ "tx_fifo_errors" },
       
   600 	{ "tx_carrier_errors" },
       
   601 	{ "tx_excess_deferral" },
       
   602 	{ "tx_retry_error" },
       
   603 	{ "tx_deferral" },
       
   604 	{ "tx_packets" },
       
   605 	{ "tx_pause" },
       
   606 	{ "rx_frame_error" },
       
   607 	{ "rx_extra_byte" },
       
   608 	{ "rx_late_collision" },
       
   609 	{ "rx_runt" },
       
   610 	{ "rx_frame_too_long" },
       
   611 	{ "rx_over_errors" },
       
   612 	{ "rx_crc_errors" },
       
   613 	{ "rx_frame_align_error" },
       
   614 	{ "rx_length_error" },
       
   615 	{ "rx_unicast" },
       
   616 	{ "rx_multicast" },
       
   617 	{ "rx_broadcast" },
       
   618 	{ "rx_bytes" },
       
   619 	{ "rx_pause" },
       
   620 	{ "rx_drop_frame" },
       
   621 	{ "rx_packets" },
       
   622 	{ "rx_errors_total" }
       
   623 };
       
   624 
       
   625 struct nv_ethtool_stats {
       
   626 	u64 tx_bytes;
       
   627 	u64 tx_zero_rexmt;
       
   628 	u64 tx_one_rexmt;
       
   629 	u64 tx_many_rexmt;
       
   630 	u64 tx_late_collision;
       
   631 	u64 tx_fifo_errors;
       
   632 	u64 tx_carrier_errors;
       
   633 	u64 tx_excess_deferral;
       
   634 	u64 tx_retry_error;
       
   635 	u64 tx_deferral;
       
   636 	u64 tx_packets;
       
   637 	u64 tx_pause;
       
   638 	u64 rx_frame_error;
       
   639 	u64 rx_extra_byte;
       
   640 	u64 rx_late_collision;
       
   641 	u64 rx_runt;
       
   642 	u64 rx_frame_too_long;
       
   643 	u64 rx_over_errors;
       
   644 	u64 rx_crc_errors;
       
   645 	u64 rx_frame_align_error;
       
   646 	u64 rx_length_error;
       
   647 	u64 rx_unicast;
       
   648 	u64 rx_multicast;
       
   649 	u64 rx_broadcast;
       
   650 	u64 rx_bytes;
       
   651 	u64 rx_pause;
       
   652 	u64 rx_drop_frame;
       
   653 	u64 rx_packets;
       
   654 	u64 rx_errors_total;
       
   655 };
       
   656 
       
   657 /* diagnostics */
       
   658 #define NV_TEST_COUNT_BASE 3
       
   659 #define NV_TEST_COUNT_EXTENDED 4
       
   660 
       
   661 static const struct nv_ethtool_str nv_etests_str[] = {
       
   662 	{ "link      (online/offline)" },
       
   663 	{ "register  (offline)       " },
       
   664 	{ "interrupt (offline)       " },
       
   665 	{ "loopback  (offline)       " }
       
   666 };
       
   667 
       
   668 struct register_test {
       
   669 	__le32 reg;
       
   670 	__le32 mask;
       
   671 };
       
   672 
       
   673 static const struct register_test nv_registers_test[] = {
       
   674 	{ NvRegUnknownSetupReg6, 0x01 },
       
   675 	{ NvRegMisc1, 0x03c },
       
   676 	{ NvRegOffloadConfig, 0x03ff },
       
   677 	{ NvRegMulticastAddrA, 0xffffffff },
       
   678 	{ NvRegTxWatermark, 0x0ff },
       
   679 	{ NvRegWakeUpFlags, 0x07777 },
       
   680 	{ 0,0 }
       
   681 };
       
   682 
       
   683 /*
       
   684  * SMP locking:
       
   685  * All hardware access under dev->priv->lock, except the performance
       
   686  * critical parts:
       
   687  * - rx is (pseudo-) lockless: it relies on the single-threading provided
       
   688  *	by the arch code for interrupts.
       
   689  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
       
   690  *	needs dev->priv->lock :-(
       
   691  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
       
   692  */
       
   693 
       
   694 /* in dev: base, irq */
       
   695 struct fe_priv {
       
   696 	spinlock_t lock;
       
   697 
       
   698 	/* General data:
       
   699 	 * Locking: spin_lock(&np->lock); */
       
   700 	struct net_device_stats stats;
       
   701 	struct nv_ethtool_stats estats;
       
   702 	int in_shutdown;
       
   703 	u32 linkspeed;
       
   704 	int duplex;
       
   705 	int autoneg;
       
   706 	int fixed_mode;
       
   707 	int phyaddr;
       
   708 	int wolenabled;
       
   709 	unsigned int phy_oui;
       
   710 	unsigned int phy_model;
       
   711 	u16 gigabit;
       
   712 	int intr_test;
       
   713 
       
   714 	/* General data: RO fields */
       
   715 	dma_addr_t ring_addr;
       
   716 	struct pci_dev *pci_dev;
       
   717 	u32 orig_mac[2];
       
   718 	u32 irqmask;
       
   719 	u32 desc_ver;
       
   720 	u32 txrxctl_bits;
       
   721 	u32 vlanctl_bits;
       
   722 	u32 driver_data;
       
   723 	u32 register_size;
       
   724 	int rx_csum;
       
   725 
       
   726 	void __iomem *base;
       
   727 
       
   728 	/* rx specific fields.
       
   729 	 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
       
   730 	 */
       
   731 	union ring_type rx_ring;
       
   732 	unsigned int cur_rx, refill_rx;
       
   733 	struct sk_buff **rx_skbuff;
       
   734 	dma_addr_t *rx_dma;
       
   735 	unsigned int rx_buf_sz;
       
   736 	unsigned int pkt_limit;
       
   737 	struct timer_list oom_kick;
       
   738 	struct timer_list nic_poll;
       
   739 	struct timer_list stats_poll;
       
   740 	u32 nic_poll_irq;
       
   741 	int rx_ring_size;
       
   742 
       
   743 	/* media detection workaround.
       
   744 	 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
       
   745 	 */
       
   746 	int need_linktimer;
       
   747 	unsigned long link_timeout;
       
   748 	/*
       
   749 	 * tx specific fields.
       
   750 	 */
       
   751 	union ring_type tx_ring;
       
   752 	unsigned int next_tx, nic_tx;
       
   753 	struct sk_buff **tx_skbuff;
       
   754 	dma_addr_t *tx_dma;
       
   755 	unsigned int *tx_dma_len;
       
   756 	u32 tx_flags;
       
   757 	int tx_ring_size;
       
   758 	int tx_limit_start;
       
   759 	int tx_limit_stop;
       
   760 
       
   761 	/* vlan fields */
       
   762 	struct vlan_group *vlangrp;
       
   763 
       
   764 	/* msi/msi-x fields */
       
   765 	u32 msi_flags;
       
   766 	struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
       
   767 
       
   768 	/* flow control */
       
   769 	u32 pause_flags;
       
   770 
       
   771     ec_device_t *ecdev;
       
   772 };
       
   773 
       
   774 /*
       
   775  * Maximum number of loops until we assume that a bit in the irq mask
       
   776  * is stuck. Overridable with module param.
       
   777  */
       
   778 static int max_interrupt_work = 5;
       
   779 
       
   780 /*
       
   781  * Optimization can be either throuput mode or cpu mode
       
   782  *
       
   783  * Throughput Mode: Every tx and rx packet will generate an interrupt.
       
   784  * CPU Mode: Interrupts are controlled by a timer.
       
   785  */
       
   786 enum {
       
   787 	NV_OPTIMIZATION_MODE_THROUGHPUT,
       
   788 	NV_OPTIMIZATION_MODE_CPU
       
   789 };
       
   790 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
       
   791 
       
   792 /*
       
   793  * Poll interval for timer irq
       
   794  *
       
   795  * This interval determines how frequent an interrupt is generated.
       
   796  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
       
   797  * Min = 0, and Max = 65535
       
   798  */
       
   799 static int poll_interval = -1;
       
   800 
       
   801 /*
       
   802  * MSI interrupts
       
   803  */
       
   804 enum {
       
   805 	NV_MSI_INT_DISABLED,
       
   806 	NV_MSI_INT_ENABLED
       
   807 };
       
   808 static int msi = NV_MSI_INT_ENABLED;
       
   809 
       
   810 /*
       
   811  * MSIX interrupts
       
   812  */
       
   813 enum {
       
   814 	NV_MSIX_INT_DISABLED,
       
   815 	NV_MSIX_INT_ENABLED
       
   816 };
       
   817 static int msix = NV_MSIX_INT_ENABLED;
       
   818 
       
   819 /*
       
   820  * DMA 64bit
       
   821  */
       
   822 enum {
       
   823 	NV_DMA_64BIT_DISABLED,
       
   824 	NV_DMA_64BIT_ENABLED
       
   825 };
       
   826 static int dma_64bit = NV_DMA_64BIT_ENABLED;
       
   827 
       
   828 static int board_idx = -1;
       
   829 
       
   830 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
       
   831 {
       
   832 	return netdev_priv(dev);
       
   833 }
       
   834 
       
   835 static inline u8 __iomem *get_hwbase(struct net_device *dev)
       
   836 {
       
   837 	return ((struct fe_priv *)netdev_priv(dev))->base;
       
   838 }
       
   839 
       
   840 static inline void pci_push(u8 __iomem *base)
       
   841 {
       
   842 	/* force out pending posted writes */
       
   843 	readl(base);
       
   844 }
       
   845 
       
   846 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
       
   847 {
       
   848 	return le32_to_cpu(prd->flaglen)
       
   849 		& ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
       
   850 }
       
   851 
       
   852 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
       
   853 {
       
   854 	return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
       
   855 }
       
   856 
       
   857 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
       
   858 				int delay, int delaymax, const char *msg)
       
   859 {
       
   860 	u8 __iomem *base = get_hwbase(dev);
       
   861 
       
   862 	pci_push(base);
       
   863 	do {
       
   864 		udelay(delay);
       
   865 		delaymax -= delay;
       
   866 		if (delaymax < 0) {
       
   867 			if (msg)
       
   868 				printk(msg);
       
   869 			return 1;
       
   870 		}
       
   871 	} while ((readl(base + offset) & mask) != target);
       
   872 	return 0;
       
   873 }
       
   874 
       
   875 #define NV_SETUP_RX_RING 0x01
       
   876 #define NV_SETUP_TX_RING 0x02
       
   877 
       
   878 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
       
   879 {
       
   880 	struct fe_priv *np = get_nvpriv(dev);
       
   881 	u8 __iomem *base = get_hwbase(dev);
       
   882 
       
   883 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
   884 		if (rxtx_flags & NV_SETUP_RX_RING) {
       
   885 			writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
       
   886 		}
       
   887 		if (rxtx_flags & NV_SETUP_TX_RING) {
       
   888 			writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
       
   889 		}
       
   890 	} else {
       
   891 		if (rxtx_flags & NV_SETUP_RX_RING) {
       
   892 			writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
       
   893 			writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
       
   894 		}
       
   895 		if (rxtx_flags & NV_SETUP_TX_RING) {
       
   896 			writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
       
   897 			writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
       
   898 		}
       
   899 	}
       
   900 }
       
   901 
       
   902 static void free_rings(struct net_device *dev)
       
   903 {
       
   904 	struct fe_priv *np = get_nvpriv(dev);
       
   905 
       
   906 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
   907 		if (np->rx_ring.orig)
       
   908 			pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
       
   909 					    np->rx_ring.orig, np->ring_addr);
       
   910 	} else {
       
   911 		if (np->rx_ring.ex)
       
   912 			pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
       
   913 					    np->rx_ring.ex, np->ring_addr);
       
   914 	}
       
   915 	if (np->rx_skbuff)
       
   916 		kfree(np->rx_skbuff);
       
   917 	if (np->rx_dma)
       
   918 		kfree(np->rx_dma);
       
   919 	if (np->tx_skbuff)
       
   920 		kfree(np->tx_skbuff);
       
   921 	if (np->tx_dma)
       
   922 		kfree(np->tx_dma);
       
   923 	if (np->tx_dma_len)
       
   924 		kfree(np->tx_dma_len);
       
   925 }
       
   926 
       
   927 static int using_multi_irqs(struct net_device *dev)
       
   928 {
       
   929 	struct fe_priv *np = get_nvpriv(dev);
       
   930 
       
   931 	if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
       
   932 	    ((np->msi_flags & NV_MSI_X_ENABLED) &&
       
   933 	     ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
       
   934 		return 0;
       
   935 	else
       
   936 		return 1;
       
   937 }
       
   938 
       
   939 static void nv_enable_irq(struct net_device *dev)
       
   940 {
       
   941 	struct fe_priv *np = get_nvpriv(dev);
       
   942 
       
   943 	if (!using_multi_irqs(dev)) {
       
   944 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
   945 			enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
       
   946 		else
       
   947 			enable_irq(dev->irq);
       
   948 	} else {
       
   949 		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
       
   950 		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
       
   951 		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
       
   952 	}
       
   953 }
       
   954 
       
   955 static void nv_disable_irq(struct net_device *dev)
       
   956 {
       
   957 	struct fe_priv *np = get_nvpriv(dev);
       
   958 
       
   959 	if (!using_multi_irqs(dev)) {
       
   960 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
   961 			disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
       
   962 		else
       
   963 			disable_irq(dev->irq);
       
   964 	} else {
       
   965 		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
       
   966 		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
       
   967 		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
       
   968 	}
       
   969 }
       
   970 
       
   971 /* In MSIX mode, a write to irqmask behaves as XOR */
       
   972 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
       
   973 {
       
   974 	u8 __iomem *base = get_hwbase(dev);
       
   975 
       
   976 	writel(mask, base + NvRegIrqMask);
       
   977 }
       
   978 
       
   979 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
       
   980 {
       
   981 	struct fe_priv *np = get_nvpriv(dev);
       
   982 	u8 __iomem *base = get_hwbase(dev);
       
   983 
       
   984 	if (np->msi_flags & NV_MSI_X_ENABLED) {
       
   985 		writel(mask, base + NvRegIrqMask);
       
   986 	} else {
       
   987 		if (np->msi_flags & NV_MSI_ENABLED)
       
   988 			writel(0, base + NvRegMSIIrqMask);
       
   989 		writel(0, base + NvRegIrqMask);
       
   990 	}
       
   991 }
       
   992 
       
   993 #define MII_READ	(-1)
       
   994 /* mii_rw: read/write a register on the PHY.
       
   995  *
       
   996  * Caller must guarantee serialization
       
   997  */
       
   998 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
       
   999 {
       
  1000 	u8 __iomem *base = get_hwbase(dev);
       
  1001 	u32 reg;
       
  1002 	int retval;
       
  1003 
       
  1004 	writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
       
  1005 
       
  1006 	reg = readl(base + NvRegMIIControl);
       
  1007 	if (reg & NVREG_MIICTL_INUSE) {
       
  1008 		writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
       
  1009 		udelay(NV_MIIBUSY_DELAY);
       
  1010 	}
       
  1011 
       
  1012 	reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
       
  1013 	if (value != MII_READ) {
       
  1014 		writel(value, base + NvRegMIIData);
       
  1015 		reg |= NVREG_MIICTL_WRITE;
       
  1016 	}
       
  1017 	writel(reg, base + NvRegMIIControl);
       
  1018 
       
  1019 	if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
       
  1020 			NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
       
  1021 		dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
       
  1022 				dev->name, miireg, addr);
       
  1023 		retval = -1;
       
  1024 	} else if (value != MII_READ) {
       
  1025 		/* it was a write operation - fewer failures are detectable */
       
  1026 		dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
       
  1027 				dev->name, value, miireg, addr);
       
  1028 		retval = 0;
       
  1029 	} else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
       
  1030 		dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
       
  1031 				dev->name, miireg, addr);
       
  1032 		retval = -1;
       
  1033 	} else {
       
  1034 		retval = readl(base + NvRegMIIData);
       
  1035 		dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
       
  1036 				dev->name, miireg, addr, retval);
       
  1037 	}
       
  1038 
       
  1039 	return retval;
       
  1040 }
       
  1041 
       
  1042 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
       
  1043 {
       
  1044 	struct fe_priv *np = netdev_priv(dev);
       
  1045 	u32 miicontrol;
       
  1046 	unsigned int tries = 0;
       
  1047 
       
  1048 	miicontrol = BMCR_RESET | bmcr_setup;
       
  1049 	if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
       
  1050 		return -1;
       
  1051 	}
       
  1052 
       
  1053 	/* wait for 500ms */
       
  1054 	msleep(500);
       
  1055 
       
  1056 	/* must wait till reset is deasserted */
       
  1057 	while (miicontrol & BMCR_RESET) {
       
  1058 		msleep(10);
       
  1059 		miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  1060 		/* FIXME: 100 tries seem excessive */
       
  1061 		if (tries++ > 100)
       
  1062 			return -1;
       
  1063 	}
       
  1064 	return 0;
       
  1065 }
       
  1066 
       
  1067 static int phy_init(struct net_device *dev)
       
  1068 {
       
  1069 	struct fe_priv *np = get_nvpriv(dev);
       
  1070 	u8 __iomem *base = get_hwbase(dev);
       
  1071 	u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
       
  1072 
       
  1073 	/* phy errata for E3016 phy */
       
  1074 	if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
       
  1075 		reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
       
  1076 		reg &= ~PHY_MARVELL_E3016_INITMASK;
       
  1077 		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
       
  1078 			printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
       
  1079 			return PHY_ERROR;
       
  1080 		}
       
  1081 	}
       
  1082 
       
  1083 	/* set advertise register */
       
  1084 	reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
       
  1085 	reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
       
  1086 	if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
       
  1087 		printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
       
  1088 		return PHY_ERROR;
       
  1089 	}
       
  1090 
       
  1091 	/* get phy interface type */
       
  1092 	phyinterface = readl(base + NvRegPhyInterface);
       
  1093 
       
  1094 	/* see if gigabit phy */
       
  1095 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
       
  1096 	if (mii_status & PHY_GIGABIT) {
       
  1097 		np->gigabit = PHY_GIGABIT;
       
  1098 		mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
       
  1099 		mii_control_1000 &= ~ADVERTISE_1000HALF;
       
  1100 		if (phyinterface & PHY_RGMII)
       
  1101 			mii_control_1000 |= ADVERTISE_1000FULL;
       
  1102 		else
       
  1103 			mii_control_1000 &= ~ADVERTISE_1000FULL;
       
  1104 
       
  1105 		if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
       
  1106 			printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
       
  1107 			return PHY_ERROR;
       
  1108 		}
       
  1109 	}
       
  1110 	else
       
  1111 		np->gigabit = 0;
       
  1112 
       
  1113 	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  1114 	mii_control |= BMCR_ANENABLE;
       
  1115 
       
  1116 	/* reset the phy
       
  1117 	 * (certain phys need bmcr to be setup with reset)
       
  1118 	 */
       
  1119 	if (phy_reset(dev, mii_control)) {
       
  1120 		printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
       
  1121 		return PHY_ERROR;
       
  1122 	}
       
  1123 
       
  1124 	/* phy vendor specific configuration */
       
  1125 	if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
       
  1126 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
       
  1127 		phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
       
  1128 		phy_reserved |= (PHY_INIT3 | PHY_INIT4);
       
  1129 		if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
       
  1130 			printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
       
  1131 			return PHY_ERROR;
       
  1132 		}
       
  1133 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
       
  1134 		phy_reserved |= PHY_INIT5;
       
  1135 		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
       
  1136 			printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
       
  1137 			return PHY_ERROR;
       
  1138 		}
       
  1139 	}
       
  1140 	if (np->phy_oui == PHY_OUI_CICADA) {
       
  1141 		phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
       
  1142 		phy_reserved |= PHY_INIT6;
       
  1143 		if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
       
  1144 			printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
       
  1145 			return PHY_ERROR;
       
  1146 		}
       
  1147 	}
       
  1148 	/* some phys clear out pause advertisment on reset, set it back */
       
  1149 	mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
       
  1150 
       
  1151 	/* restart auto negotiation */
       
  1152 	mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  1153 	mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
       
  1154 	if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
       
  1155 		return PHY_ERROR;
       
  1156 	}
       
  1157 
       
  1158 	return 0;
       
  1159 }
       
  1160 
       
  1161 static void nv_start_rx(struct net_device *dev)
       
  1162 {
       
  1163 	struct fe_priv *np = netdev_priv(dev);
       
  1164 	u8 __iomem *base = get_hwbase(dev);
       
  1165 
       
  1166 	dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
       
  1167 	/* Already running? Stop it. */
       
  1168 	if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
       
  1169 		writel(0, base + NvRegReceiverControl);
       
  1170 		pci_push(base);
       
  1171 	}
       
  1172 	writel(np->linkspeed, base + NvRegLinkSpeed);
       
  1173 	pci_push(base);
       
  1174 	writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
       
  1175 	dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
       
  1176 				dev->name, np->duplex, np->linkspeed);
       
  1177 	pci_push(base);
       
  1178 }
       
  1179 
       
  1180 static void nv_stop_rx(struct net_device *dev)
       
  1181 {
       
  1182 	u8 __iomem *base = get_hwbase(dev);
       
  1183 
       
  1184 	dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
       
  1185 	writel(0, base + NvRegReceiverControl);
       
  1186 	reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
       
  1187 			NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
       
  1188 			KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
       
  1189 
       
  1190 	udelay(NV_RXSTOP_DELAY2);
       
  1191 	writel(0, base + NvRegLinkSpeed);
       
  1192 }
       
  1193 
       
  1194 static void nv_start_tx(struct net_device *dev)
       
  1195 {
       
  1196 	u8 __iomem *base = get_hwbase(dev);
       
  1197 
       
  1198 	dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
       
  1199 	writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
       
  1200 	pci_push(base);
       
  1201 }
       
  1202 
       
  1203 static void nv_stop_tx(struct net_device *dev)
       
  1204 {
       
  1205 	u8 __iomem *base = get_hwbase(dev);
       
  1206 
       
  1207 	dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
       
  1208 	writel(0, base + NvRegTransmitterControl);
       
  1209 	reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
       
  1210 			NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
       
  1211 			KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
       
  1212 
       
  1213 	udelay(NV_TXSTOP_DELAY2);
       
  1214 	writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
       
  1215 }
       
  1216 
       
  1217 static void nv_txrx_reset(struct net_device *dev)
       
  1218 {
       
  1219 	struct fe_priv *np = netdev_priv(dev);
       
  1220 	u8 __iomem *base = get_hwbase(dev);
       
  1221 
       
  1222 	dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
       
  1223 	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
       
  1224 	pci_push(base);
       
  1225 	udelay(NV_TXRX_RESET_DELAY);
       
  1226 	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
       
  1227 	pci_push(base);
       
  1228 }
       
  1229 
       
  1230 static void nv_mac_reset(struct net_device *dev)
       
  1231 {
       
  1232 	struct fe_priv *np = netdev_priv(dev);
       
  1233 	u8 __iomem *base = get_hwbase(dev);
       
  1234 
       
  1235 	dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
       
  1236 	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
       
  1237 	pci_push(base);
       
  1238 	writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
       
  1239 	pci_push(base);
       
  1240 	udelay(NV_MAC_RESET_DELAY);
       
  1241 	writel(0, base + NvRegMacReset);
       
  1242 	pci_push(base);
       
  1243 	udelay(NV_MAC_RESET_DELAY);
       
  1244 	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
       
  1245 	pci_push(base);
       
  1246 }
       
  1247 
       
  1248 /*
       
  1249  * nv_get_stats: dev->get_stats function
       
  1250  * Get latest stats value from the nic.
       
  1251  * Called with read_lock(&dev_base_lock) held for read -
       
  1252  * only synchronized against unregister_netdevice.
       
  1253  */
       
  1254 static struct net_device_stats *nv_get_stats(struct net_device *dev)
       
  1255 {
       
  1256 	struct fe_priv *np = netdev_priv(dev);
       
  1257 
       
  1258 	/* It seems that the nic always generates interrupts and doesn't
       
  1259 	 * accumulate errors internally. Thus the current values in np->stats
       
  1260 	 * are already up to date.
       
  1261 	 */
       
  1262 	return &np->stats;
       
  1263 }
       
  1264 
       
  1265 /*
       
  1266  * nv_alloc_rx: fill rx ring entries.
       
  1267  * Return 1 if the allocations for the skbs failed and the
       
  1268  * rx engine is without Available descriptors
       
  1269  */
       
  1270 static int nv_alloc_rx(struct net_device *dev)
       
  1271 {
       
  1272 	struct fe_priv *np = netdev_priv(dev);
       
  1273 	unsigned int refill_rx = np->refill_rx;
       
  1274 	int nr;
       
  1275 
       
  1276 	while (np->cur_rx != refill_rx) {
       
  1277 		struct sk_buff *skb;
       
  1278 
       
  1279 		nr = refill_rx % np->rx_ring_size;
       
  1280 		if (np->rx_skbuff[nr] == NULL) {
       
  1281 
       
  1282 			skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
       
  1283 			if (!skb)
       
  1284 				break;
       
  1285 
       
  1286 			skb->dev = dev;
       
  1287 			np->rx_skbuff[nr] = skb;
       
  1288 		} else {
       
  1289 			skb = np->rx_skbuff[nr];
       
  1290 		}
       
  1291 		np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
       
  1292 					skb->end-skb->data, PCI_DMA_FROMDEVICE);
       
  1293 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1294 			np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
       
  1295 			wmb();
       
  1296 			np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
       
  1297 		} else {
       
  1298 			np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
       
  1299 			np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
       
  1300 			wmb();
       
  1301 			np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
       
  1302 		}
       
  1303 		dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
       
  1304 					dev->name, refill_rx);
       
  1305 		refill_rx++;
       
  1306 	}
       
  1307 	np->refill_rx = refill_rx;
       
  1308 	if (np->cur_rx - refill_rx == np->rx_ring_size)
       
  1309 		return 1;
       
  1310 	return 0;
       
  1311 }
       
  1312 
       
  1313 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
       
  1314 #ifdef CONFIG_FORCEDETH_NAPI
       
  1315 static void nv_do_rx_refill(unsigned long data)
       
  1316 {
       
  1317 	struct net_device *dev = (struct net_device *) data;
       
  1318 
       
  1319 	/* Just reschedule NAPI rx processing */
       
  1320 	netif_rx_schedule(dev);
       
  1321 }
       
  1322 #else
       
  1323 static void nv_do_rx_refill(unsigned long data)
       
  1324 {
       
  1325 	struct net_device *dev = (struct net_device *) data;
       
  1326 	struct fe_priv *np = netdev_priv(dev);
       
  1327 
       
  1328 	if (!using_multi_irqs(dev)) {
       
  1329 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
  1330 			disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
       
  1331 		else
       
  1332 			disable_irq(dev->irq);
       
  1333 	} else {
       
  1334 		disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
       
  1335 	}
       
  1336 	if (nv_alloc_rx(dev)) {
       
  1337 		spin_lock_irq(&np->lock);
       
  1338 		if (!np->in_shutdown)
       
  1339 			mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  1340 		spin_unlock_irq(&np->lock);
       
  1341 	}
       
  1342 	if (!using_multi_irqs(dev)) {
       
  1343 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
  1344 			enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
       
  1345 		else
       
  1346 			enable_irq(dev->irq);
       
  1347 	} else {
       
  1348 		enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
       
  1349 	}
       
  1350 }
       
  1351 #endif
       
  1352 
       
  1353 static void nv_init_rx(struct net_device *dev)
       
  1354 {
       
  1355 	struct fe_priv *np = netdev_priv(dev);
       
  1356 	int i;
       
  1357 
       
  1358 	np->cur_rx = np->rx_ring_size;
       
  1359 	np->refill_rx = 0;
       
  1360 	for (i = 0; i < np->rx_ring_size; i++)
       
  1361 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
       
  1362 			np->rx_ring.orig[i].flaglen = 0;
       
  1363 	        else
       
  1364 			np->rx_ring.ex[i].flaglen = 0;
       
  1365 }
       
  1366 
       
  1367 static void nv_init_tx(struct net_device *dev)
       
  1368 {
       
  1369 	struct fe_priv *np = netdev_priv(dev);
       
  1370 	int i;
       
  1371 
       
  1372 	np->next_tx = np->nic_tx = 0;
       
  1373 	for (i = 0; i < np->tx_ring_size; i++) {
       
  1374 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
       
  1375 			np->tx_ring.orig[i].flaglen = 0;
       
  1376 	        else
       
  1377 			np->tx_ring.ex[i].flaglen = 0;
       
  1378 		np->tx_skbuff[i] = NULL;
       
  1379 		np->tx_dma[i] = 0;
       
  1380 	}
       
  1381 }
       
  1382 
       
  1383 static int nv_init_ring(struct net_device *dev)
       
  1384 {
       
  1385 	nv_init_tx(dev);
       
  1386 	nv_init_rx(dev);
       
  1387 	return nv_alloc_rx(dev);
       
  1388 }
       
  1389 
       
  1390 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
       
  1391 {
       
  1392 	struct fe_priv *np = netdev_priv(dev);
       
  1393 
       
  1394 	dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
       
  1395 		dev->name, skbnr);
       
  1396 
       
  1397 	if (np->tx_dma[skbnr]) {
       
  1398 		pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
       
  1399 			       np->tx_dma_len[skbnr],
       
  1400 			       PCI_DMA_TODEVICE);
       
  1401 		np->tx_dma[skbnr] = 0;
       
  1402 	}
       
  1403 
       
  1404 	if (np->tx_skbuff[skbnr]) {
       
  1405 		if (!np->ecdev) dev_kfree_skb_any(np->tx_skbuff[skbnr]);
       
  1406 		np->tx_skbuff[skbnr] = NULL;
       
  1407 		return 1;
       
  1408 	} else {
       
  1409 		return 0;
       
  1410 	}
       
  1411 }
       
  1412 
       
  1413 static void nv_drain_tx(struct net_device *dev)
       
  1414 {
       
  1415 	struct fe_priv *np = netdev_priv(dev);
       
  1416 	unsigned int i;
       
  1417 
       
  1418 	for (i = 0; i < np->tx_ring_size; i++) {
       
  1419 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
       
  1420 			np->tx_ring.orig[i].flaglen = 0;
       
  1421 		else
       
  1422 			np->tx_ring.ex[i].flaglen = 0;
       
  1423 		if (nv_release_txskb(dev, i))
       
  1424 			np->stats.tx_dropped++;
       
  1425 	}
       
  1426 }
       
  1427 
       
  1428 static void nv_drain_rx(struct net_device *dev)
       
  1429 {
       
  1430 	struct fe_priv *np = netdev_priv(dev);
       
  1431 	int i;
       
  1432 	for (i = 0; i < np->rx_ring_size; i++) {
       
  1433 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
       
  1434 			np->rx_ring.orig[i].flaglen = 0;
       
  1435 		else
       
  1436 			np->rx_ring.ex[i].flaglen = 0;
       
  1437 		wmb();
       
  1438 		if (np->rx_skbuff[i]) {
       
  1439 			pci_unmap_single(np->pci_dev, np->rx_dma[i],
       
  1440 						np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
       
  1441 						PCI_DMA_FROMDEVICE);
       
  1442 			if (!np->ecdev) dev_kfree_skb(np->rx_skbuff[i]);
       
  1443 			np->rx_skbuff[i] = NULL;
       
  1444 		}
       
  1445 	}
       
  1446 }
       
  1447 
       
  1448 static void drain_ring(struct net_device *dev)
       
  1449 {
       
  1450 	nv_drain_tx(dev);
       
  1451 	nv_drain_rx(dev);
       
  1452 }
       
  1453 
       
  1454 /*
       
  1455  * nv_start_xmit: dev->hard_start_xmit function
       
  1456  * Called with netif_tx_lock held.
       
  1457  */
       
  1458 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
       
  1459 {
       
  1460 	struct fe_priv *np = netdev_priv(dev);
       
  1461 	u32 tx_flags = 0;
       
  1462 	u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
       
  1463 	unsigned int fragments = skb_shinfo(skb)->nr_frags;
       
  1464 	unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
       
  1465 	unsigned int start_nr = np->next_tx % np->tx_ring_size;
       
  1466 	unsigned int i;
       
  1467 	u32 offset = 0;
       
  1468 	u32 bcnt;
       
  1469 	u32 size = skb->len-skb->data_len;
       
  1470 	u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
       
  1471 	u32 tx_flags_vlan = 0;
       
  1472 
       
  1473 	/* add fragments to entries count */
       
  1474 	for (i = 0; i < fragments; i++) {
       
  1475 		entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
       
  1476 			   ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
       
  1477 	}
       
  1478 
       
  1479 	if (!np->ecdev) {
       
  1480 		spin_lock_irq(&np->lock);
       
  1481 
       
  1482         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
       
  1483             spin_unlock_irq(&np->lock);
       
  1484             netif_stop_queue(dev);
       
  1485             return NETDEV_TX_BUSY;
       
  1486 	}
       
  1487 
       
  1488 	/* setup the header buffer */
       
  1489 	do {
       
  1490 		bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
       
  1491 		nr = (nr + 1) % np->tx_ring_size;
       
  1492 
       
  1493 		np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
       
  1494 						PCI_DMA_TODEVICE);
       
  1495 		np->tx_dma_len[nr] = bcnt;
       
  1496 
       
  1497 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1498 			np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
       
  1499 			np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
       
  1500 		} else {
       
  1501 			np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
       
  1502 			np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
       
  1503 			np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
       
  1504 		}
       
  1505 		tx_flags = np->tx_flags;
       
  1506 		offset += bcnt;
       
  1507 		size -= bcnt;
       
  1508 	} while (size);
       
  1509 
       
  1510 	/* setup the fragments */
       
  1511 	for (i = 0; i < fragments; i++) {
       
  1512 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
       
  1513 		u32 size = frag->size;
       
  1514 		offset = 0;
       
  1515 
       
  1516 		do {
       
  1517 			bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
       
  1518 			nr = (nr + 1) % np->tx_ring_size;
       
  1519 
       
  1520 			np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
       
  1521 						      PCI_DMA_TODEVICE);
       
  1522 			np->tx_dma_len[nr] = bcnt;
       
  1523 
       
  1524 			if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1525 				np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
       
  1526 				np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
       
  1527 			} else {
       
  1528 				np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
       
  1529 				np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
       
  1530 				np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
       
  1531 			}
       
  1532 			offset += bcnt;
       
  1533 			size -= bcnt;
       
  1534 		} while (size);
       
  1535 	}
       
  1536 
       
  1537 	/* set last fragment flag  */
       
  1538 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1539 		np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
       
  1540 	} else {
       
  1541 		np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
       
  1542 	}
       
  1543 
       
  1544 	np->tx_skbuff[nr] = skb;
       
  1545 
       
  1546 #ifdef NETIF_F_TSO
       
  1547 	if (skb_is_gso(skb))
       
  1548 		tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
       
  1549 	else
       
  1550 #endif
       
  1551 	tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
       
  1552 			 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
       
  1553 
       
  1554 	/* vlan tag */
       
  1555 	if (np->vlangrp && vlan_tx_tag_present(skb)) {
       
  1556 		tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
       
  1557 	}
       
  1558 
       
  1559 	/* set tx flags */
       
  1560 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1561 		np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
       
  1562 	} else {
       
  1563 		np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
       
  1564 		np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
       
  1565 	}
       
  1566 
       
  1567 	dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
       
  1568 		dev->name, np->next_tx, entries, tx_flags_extra);
       
  1569 	{
       
  1570 		int j;
       
  1571 		for (j=0; j<64; j++) {
       
  1572 			if ((j%16) == 0)
       
  1573 				dprintk("\n%03x:", j);
       
  1574 			dprintk(" %02x", ((unsigned char*)skb->data)[j]);
       
  1575 		}
       
  1576 		dprintk("\n");
       
  1577 	}
       
  1578 
       
  1579 	np->next_tx += entries;
       
  1580 
       
  1581 	dev->trans_start = jiffies;
       
  1582 	if (!np->ecdev) spin_unlock_irq(&np->lock);
       
  1583 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
       
  1584 	pci_push(get_hwbase(dev));
       
  1585 	return NETDEV_TX_OK;
       
  1586 }
       
  1587 
       
  1588 /*
       
  1589  * nv_tx_done: check for completed packets, release the skbs.
       
  1590  *
       
  1591  * Caller must own np->lock.
       
  1592  */
       
  1593 static void nv_tx_done(struct net_device *dev)
       
  1594 {
       
  1595 	struct fe_priv *np = netdev_priv(dev);
       
  1596 	u32 flags;
       
  1597 	unsigned int i;
       
  1598 	struct sk_buff *skb;
       
  1599 
       
  1600 	while (np->nic_tx != np->next_tx) {
       
  1601 		i = np->nic_tx % np->tx_ring_size;
       
  1602 
       
  1603 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
       
  1604 			flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
       
  1605 		else
       
  1606 			flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
       
  1607 
       
  1608 		dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
       
  1609 					dev->name, np->nic_tx, flags);
       
  1610 		if (flags & NV_TX_VALID)
       
  1611 			break;
       
  1612 		if (np->desc_ver == DESC_VER_1) {
       
  1613 			if (flags & NV_TX_LASTPACKET) {
       
  1614 				skb = np->tx_skbuff[i];
       
  1615 				if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
       
  1616 					     NV_TX_UNDERFLOW|NV_TX_ERROR)) {
       
  1617 					if (flags & NV_TX_UNDERFLOW)
       
  1618 						np->stats.tx_fifo_errors++;
       
  1619 					if (flags & NV_TX_CARRIERLOST)
       
  1620 						np->stats.tx_carrier_errors++;
       
  1621 					np->stats.tx_errors++;
       
  1622 				} else {
       
  1623 					np->stats.tx_packets++;
       
  1624 					np->stats.tx_bytes += skb->len;
       
  1625 				}
       
  1626 			}
       
  1627 		} else {
       
  1628 			if (flags & NV_TX2_LASTPACKET) {
       
  1629 				skb = np->tx_skbuff[i];
       
  1630 				if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
       
  1631 					     NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
       
  1632 					if (flags & NV_TX2_UNDERFLOW)
       
  1633 						np->stats.tx_fifo_errors++;
       
  1634 					if (flags & NV_TX2_CARRIERLOST)
       
  1635 						np->stats.tx_carrier_errors++;
       
  1636 					np->stats.tx_errors++;
       
  1637 				} else {
       
  1638 					np->stats.tx_packets++;
       
  1639 					np->stats.tx_bytes += skb->len;
       
  1640 				}
       
  1641 			}
       
  1642 		}
       
  1643 		nv_release_txskb(dev, i);
       
  1644 		np->nic_tx++;
       
  1645 	}
       
  1646 	if (!np->ecdev && np->next_tx - np->nic_tx < np->tx_limit_start)
       
  1647 		netif_wake_queue(dev);
       
  1648 }
       
  1649 
       
  1650 /*
       
  1651  * nv_tx_timeout: dev->tx_timeout function
       
  1652  * Called with netif_tx_lock held.
       
  1653  */
       
  1654 static void nv_tx_timeout(struct net_device *dev)
       
  1655 {
       
  1656 	struct fe_priv *np = netdev_priv(dev);
       
  1657 	u8 __iomem *base = get_hwbase(dev);
       
  1658 	u32 status;
       
  1659 
       
  1660 	if (np->msi_flags & NV_MSI_X_ENABLED)
       
  1661 		status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
       
  1662 	else
       
  1663 		status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
       
  1664 
       
  1665 	printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
       
  1666 
       
  1667 	{
       
  1668 		int i;
       
  1669 
       
  1670 		printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
       
  1671 				dev->name, (unsigned long)np->ring_addr,
       
  1672 				np->next_tx, np->nic_tx);
       
  1673 		printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
       
  1674 		for (i=0;i<=np->register_size;i+= 32) {
       
  1675 			printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
       
  1676 					i,
       
  1677 					readl(base + i + 0), readl(base + i + 4),
       
  1678 					readl(base + i + 8), readl(base + i + 12),
       
  1679 					readl(base + i + 16), readl(base + i + 20),
       
  1680 					readl(base + i + 24), readl(base + i + 28));
       
  1681 		}
       
  1682 		printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
       
  1683 		for (i=0;i<np->tx_ring_size;i+= 4) {
       
  1684 			if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1685 				printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
       
  1686 				       i,
       
  1687 				       le32_to_cpu(np->tx_ring.orig[i].buf),
       
  1688 				       le32_to_cpu(np->tx_ring.orig[i].flaglen),
       
  1689 				       le32_to_cpu(np->tx_ring.orig[i+1].buf),
       
  1690 				       le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
       
  1691 				       le32_to_cpu(np->tx_ring.orig[i+2].buf),
       
  1692 				       le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
       
  1693 				       le32_to_cpu(np->tx_ring.orig[i+3].buf),
       
  1694 				       le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
       
  1695 			} else {
       
  1696 				printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
       
  1697 				       i,
       
  1698 				       le32_to_cpu(np->tx_ring.ex[i].bufhigh),
       
  1699 				       le32_to_cpu(np->tx_ring.ex[i].buflow),
       
  1700 				       le32_to_cpu(np->tx_ring.ex[i].flaglen),
       
  1701 				       le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
       
  1702 				       le32_to_cpu(np->tx_ring.ex[i+1].buflow),
       
  1703 				       le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
       
  1704 				       le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
       
  1705 				       le32_to_cpu(np->tx_ring.ex[i+2].buflow),
       
  1706 				       le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
       
  1707 				       le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
       
  1708 				       le32_to_cpu(np->tx_ring.ex[i+3].buflow),
       
  1709 				       le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
       
  1710 			}
       
  1711 		}
       
  1712 	}
       
  1713 
       
  1714 	if (!np->ecdev) spin_lock_irq(&np->lock);
       
  1715 
       
  1716 	/* 1) stop tx engine */
       
  1717 	nv_stop_tx(dev);
       
  1718 
       
  1719 	/* 2) check that the packets were not sent already: */
       
  1720 	nv_tx_done(dev);
       
  1721 
       
  1722 	/* 3) if there are dead entries: clear everything */
       
  1723 	if (np->next_tx != np->nic_tx) {
       
  1724 		printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
       
  1725 		nv_drain_tx(dev);
       
  1726 		np->next_tx = np->nic_tx = 0;
       
  1727 		setup_hw_rings(dev, NV_SETUP_TX_RING);
       
  1728 		if (!np->ecdev) netif_wake_queue(dev);
       
  1729 	}
       
  1730 
       
  1731 	/* 4) restart tx engine */
       
  1732 	nv_start_tx(dev);
       
  1733 	if (!np->ecdev) spin_unlock_irq(&np->lock);
       
  1734 }
       
  1735 
       
  1736 /*
       
  1737  * Called when the nic notices a mismatch between the actual data len on the
       
  1738  * wire and the len indicated in the 802 header
       
  1739  */
       
  1740 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
       
  1741 {
       
  1742 	int hdrlen;	/* length of the 802 header */
       
  1743 	int protolen;	/* length as stored in the proto field */
       
  1744 
       
  1745 	/* 1) calculate len according to header */
       
  1746 	if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
       
  1747 		protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
       
  1748 		hdrlen = VLAN_HLEN;
       
  1749 	} else {
       
  1750 		protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
       
  1751 		hdrlen = ETH_HLEN;
       
  1752 	}
       
  1753 	dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
       
  1754 				dev->name, datalen, protolen, hdrlen);
       
  1755 	if (protolen > ETH_DATA_LEN)
       
  1756 		return datalen; /* Value in proto field not a len, no checks possible */
       
  1757 
       
  1758 	protolen += hdrlen;
       
  1759 	/* consistency checks: */
       
  1760 	if (datalen > ETH_ZLEN) {
       
  1761 		if (datalen >= protolen) {
       
  1762 			/* more data on wire than in 802 header, trim of
       
  1763 			 * additional data.
       
  1764 			 */
       
  1765 			dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
       
  1766 					dev->name, protolen);
       
  1767 			return protolen;
       
  1768 		} else {
       
  1769 			/* less data on wire than mentioned in header.
       
  1770 			 * Discard the packet.
       
  1771 			 */
       
  1772 			dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
       
  1773 					dev->name);
       
  1774 			return -1;
       
  1775 		}
       
  1776 	} else {
       
  1777 		/* short packet. Accept only if 802 values are also short */
       
  1778 		if (protolen > ETH_ZLEN) {
       
  1779 			dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
       
  1780 					dev->name);
       
  1781 			return -1;
       
  1782 		}
       
  1783 		dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
       
  1784 				dev->name, datalen);
       
  1785 		return datalen;
       
  1786 	}
       
  1787 }
       
  1788 
       
  1789 static int nv_rx_process(struct net_device *dev, int limit)
       
  1790 {
       
  1791 	struct fe_priv *np = netdev_priv(dev);
       
  1792 	u32 flags;
       
  1793 	u32 vlanflags = 0;
       
  1794 	int count;
       
  1795 
       
  1796  	for (count = 0; count < limit; ++count) {
       
  1797 		struct sk_buff *skb;
       
  1798 		int len;
       
  1799 		int i;
       
  1800 		if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
       
  1801 			break;	/* we scanned the whole ring - do not continue */
       
  1802 
       
  1803 		i = np->cur_rx % np->rx_ring_size;
       
  1804 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  1805 			flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
       
  1806 			len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
       
  1807 		} else {
       
  1808 			flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
       
  1809 			len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
       
  1810 			vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
       
  1811 		}
       
  1812 
       
  1813 		dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
       
  1814 					dev->name, np->cur_rx, flags);
       
  1815 
       
  1816 		if (flags & NV_RX_AVAIL)
       
  1817 			break;	/* still owned by hardware, */
       
  1818 
       
  1819 		/*
       
  1820 		 * the packet is for us - immediately tear down the pci mapping.
       
  1821 		 * TODO: check if a prefetch of the first cacheline improves
       
  1822 		 * the performance.
       
  1823 		 */
       
  1824 		pci_unmap_single(np->pci_dev, np->rx_dma[i],
       
  1825 				np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
       
  1826 				PCI_DMA_FROMDEVICE);
       
  1827 		{
       
  1828 			int j;
       
  1829 			dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
       
  1830 			for (j=0; j<64; j++) {
       
  1831 				if ((j%16) == 0)
       
  1832 					dprintk("\n%03x:", j);
       
  1833 				dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
       
  1834 			}
       
  1835 			dprintk("\n");
       
  1836 		}
       
  1837 		/* look at what we actually got: */
       
  1838 		if (np->desc_ver == DESC_VER_1) {
       
  1839 			if (!(flags & NV_RX_DESCRIPTORVALID))
       
  1840 				goto next_pkt;
       
  1841 
       
  1842 			if (flags & NV_RX_ERROR) {
       
  1843 				if (flags & NV_RX_MISSEDFRAME) {
       
  1844 					np->stats.rx_missed_errors++;
       
  1845 					np->stats.rx_errors++;
       
  1846 					goto next_pkt;
       
  1847 				}
       
  1848 				if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
       
  1849 					np->stats.rx_errors++;
       
  1850 					goto next_pkt;
       
  1851 				}
       
  1852 				if (flags & NV_RX_CRCERR) {
       
  1853 					np->stats.rx_crc_errors++;
       
  1854 					np->stats.rx_errors++;
       
  1855 					goto next_pkt;
       
  1856 				}
       
  1857 				if (flags & NV_RX_OVERFLOW) {
       
  1858 					np->stats.rx_over_errors++;
       
  1859 					np->stats.rx_errors++;
       
  1860 					goto next_pkt;
       
  1861 				}
       
  1862 				if (flags & NV_RX_ERROR4) {
       
  1863 					len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
       
  1864 					if (len < 0) {
       
  1865 						np->stats.rx_errors++;
       
  1866 						goto next_pkt;
       
  1867 					}
       
  1868 				}
       
  1869 				/* framing errors are soft errors. */
       
  1870 				if (flags & NV_RX_FRAMINGERR) {
       
  1871 					if (flags & NV_RX_SUBSTRACT1) {
       
  1872 						len--;
       
  1873 					}
       
  1874 				}
       
  1875 			}
       
  1876 		} else {
       
  1877 			if (!(flags & NV_RX2_DESCRIPTORVALID))
       
  1878 				goto next_pkt;
       
  1879 
       
  1880 			if (flags & NV_RX2_ERROR) {
       
  1881 				if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
       
  1882 					np->stats.rx_errors++;
       
  1883 					goto next_pkt;
       
  1884 				}
       
  1885 				if (flags & NV_RX2_CRCERR) {
       
  1886 					np->stats.rx_crc_errors++;
       
  1887 					np->stats.rx_errors++;
       
  1888 					goto next_pkt;
       
  1889 				}
       
  1890 				if (flags & NV_RX2_OVERFLOW) {
       
  1891 					np->stats.rx_over_errors++;
       
  1892 					np->stats.rx_errors++;
       
  1893 					goto next_pkt;
       
  1894 				}
       
  1895 				if (flags & NV_RX2_ERROR4) {
       
  1896 					len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
       
  1897 					if (len < 0) {
       
  1898 						np->stats.rx_errors++;
       
  1899 						goto next_pkt;
       
  1900 					}
       
  1901 				}
       
  1902 				/* framing errors are soft errors */
       
  1903 				if (flags & NV_RX2_FRAMINGERR) {
       
  1904 					if (flags & NV_RX2_SUBSTRACT1) {
       
  1905 						len--;
       
  1906 					}
       
  1907 				}
       
  1908 			}
       
  1909 			if (np->rx_csum) {
       
  1910 				flags &= NV_RX2_CHECKSUMMASK;
       
  1911 				if (flags == NV_RX2_CHECKSUMOK1 ||
       
  1912 				    flags == NV_RX2_CHECKSUMOK2 ||
       
  1913 				    flags == NV_RX2_CHECKSUMOK3) {
       
  1914 					dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
       
  1915 					np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
       
  1916 				} else {
       
  1917 					dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
       
  1918 				}
       
  1919 			}
       
  1920 		}
       
  1921 		if (np->ecdev) {
       
  1922 			ecdev_receive(np->ecdev, np->rx_skbuff[i]->data, len);
       
  1923 		}
       
  1924 		else {
       
  1925 			/* got a valid packet - forward it to the network core */
       
  1926 			skb = np->rx_skbuff[i];
       
  1927 			np->rx_skbuff[i] = NULL;
       
  1928 
       
  1929 			skb_put(skb, len);
       
  1930 			skb->protocol = eth_type_trans(skb, dev);
       
  1931 			dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
       
  1932 					dev->name, np->cur_rx, len, skb->protocol);
       
  1933 #ifdef CONFIG_FORCEDETH_NAPI
       
  1934 			if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
       
  1935 				vlan_hwaccel_receive_skb(skb, np->vlangrp,
       
  1936 						vlanflags & NV_RX3_VLAN_TAG_MASK);
       
  1937 			else
       
  1938 				netif_receive_skb(skb);
       
  1939 #else
       
  1940 			if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
       
  1941 				vlan_hwaccel_rx(skb, np->vlangrp,
       
  1942 						vlanflags & NV_RX3_VLAN_TAG_MASK);
       
  1943 			else
       
  1944 				netif_rx(skb);
       
  1945 #endif
       
  1946 		}
       
  1947 		dev->last_rx = jiffies;
       
  1948 		np->stats.rx_packets++;
       
  1949 		np->stats.rx_bytes += len;
       
  1950 next_pkt:
       
  1951 		np->cur_rx++;
       
  1952 	}
       
  1953 
       
  1954 	return count;
       
  1955 }
       
  1956 
       
  1957 static void set_bufsize(struct net_device *dev)
       
  1958 {
       
  1959 	struct fe_priv *np = netdev_priv(dev);
       
  1960 
       
  1961 	if (dev->mtu <= ETH_DATA_LEN)
       
  1962 		np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
       
  1963 	else
       
  1964 		np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
       
  1965 }
       
  1966 
       
  1967 /*
       
  1968  * nv_change_mtu: dev->change_mtu function
       
  1969  * Called with dev_base_lock held for read.
       
  1970  */
       
  1971 static int nv_change_mtu(struct net_device *dev, int new_mtu)
       
  1972 {
       
  1973 	struct fe_priv *np = netdev_priv(dev);
       
  1974 	int old_mtu;
       
  1975 
       
  1976 	if (new_mtu < 64 || new_mtu > np->pkt_limit)
       
  1977 		return -EINVAL;
       
  1978 
       
  1979 	old_mtu = dev->mtu;
       
  1980 	dev->mtu = new_mtu;
       
  1981 
       
  1982 	/* return early if the buffer sizes will not change */
       
  1983 	if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
       
  1984 		return 0;
       
  1985 	if (old_mtu == new_mtu)
       
  1986 		return 0;
       
  1987 
       
  1988 	/* synchronized against open : rtnl_lock() held by caller */
       
  1989 	if (netif_running(dev)) {
       
  1990 		u8 __iomem *base = get_hwbase(dev);
       
  1991 		/*
       
  1992 		 * It seems that the nic preloads valid ring entries into an
       
  1993 		 * internal buffer. The procedure for flushing everything is
       
  1994 		 * guessed, there is probably a simpler approach.
       
  1995 		 * Changing the MTU is a rare event, it shouldn't matter.
       
  1996 		 */
       
  1997 		nv_disable_irq(dev);
       
  1998 		netif_tx_lock_bh(dev);
       
  1999 		spin_lock(&np->lock);
       
  2000 		/* stop engines */
       
  2001 		nv_stop_rx(dev);
       
  2002 		nv_stop_tx(dev);
       
  2003 		nv_txrx_reset(dev);
       
  2004 		/* drain rx queue */
       
  2005 		nv_drain_rx(dev);
       
  2006 		nv_drain_tx(dev);
       
  2007 		/* reinit driver view of the rx queue */
       
  2008 		set_bufsize(dev);
       
  2009 		if (nv_init_ring(dev)) {
       
  2010 			if (!np->in_shutdown)
       
  2011 				mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  2012 		}
       
  2013 		/* reinit nic view of the rx queue */
       
  2014 		writel(np->rx_buf_sz, base + NvRegOffloadConfig);
       
  2015 		setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
       
  2016 		writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
       
  2017 			base + NvRegRingSizes);
       
  2018 		pci_push(base);
       
  2019 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
       
  2020 		pci_push(base);
       
  2021 
       
  2022 		/* restart rx engine */
       
  2023 		nv_start_rx(dev);
       
  2024 		nv_start_tx(dev);
       
  2025 		spin_unlock(&np->lock);
       
  2026 		netif_tx_unlock_bh(dev);
       
  2027 		nv_enable_irq(dev);
       
  2028 	}
       
  2029 	return 0;
       
  2030 }
       
  2031 
       
  2032 static void nv_copy_mac_to_hw(struct net_device *dev)
       
  2033 {
       
  2034 	u8 __iomem *base = get_hwbase(dev);
       
  2035 	u32 mac[2];
       
  2036 
       
  2037 	mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
       
  2038 			(dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
       
  2039 	mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
       
  2040 
       
  2041 	writel(mac[0], base + NvRegMacAddrA);
       
  2042 	writel(mac[1], base + NvRegMacAddrB);
       
  2043 }
       
  2044 
       
  2045 /*
       
  2046  * nv_set_mac_address: dev->set_mac_address function
       
  2047  * Called with rtnl_lock() held.
       
  2048  */
       
  2049 static int nv_set_mac_address(struct net_device *dev, void *addr)
       
  2050 {
       
  2051 	struct fe_priv *np = netdev_priv(dev);
       
  2052 	struct sockaddr *macaddr = (struct sockaddr*)addr;
       
  2053 
       
  2054 	if (!is_valid_ether_addr(macaddr->sa_data))
       
  2055 		return -EADDRNOTAVAIL;
       
  2056 
       
  2057 	/* synchronized against open : rtnl_lock() held by caller */
       
  2058 	memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
       
  2059 
       
  2060 	if (netif_running(dev)) {
       
  2061 		netif_tx_lock_bh(dev);
       
  2062 		spin_lock_irq(&np->lock);
       
  2063 
       
  2064 		/* stop rx engine */
       
  2065 		nv_stop_rx(dev);
       
  2066 
       
  2067 		/* set mac address */
       
  2068 		nv_copy_mac_to_hw(dev);
       
  2069 
       
  2070 		/* restart rx engine */
       
  2071 		nv_start_rx(dev);
       
  2072 		spin_unlock_irq(&np->lock);
       
  2073 		netif_tx_unlock_bh(dev);
       
  2074 	} else {
       
  2075 		nv_copy_mac_to_hw(dev);
       
  2076 	}
       
  2077 	return 0;
       
  2078 }
       
  2079 
       
  2080 /*
       
  2081  * nv_set_multicast: dev->set_multicast function
       
  2082  * Called with netif_tx_lock held.
       
  2083  */
       
  2084 static void nv_set_multicast(struct net_device *dev)
       
  2085 {
       
  2086 	struct fe_priv *np = netdev_priv(dev);
       
  2087 	u8 __iomem *base = get_hwbase(dev);
       
  2088 	u32 addr[2];
       
  2089 	u32 mask[2];
       
  2090 	u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
       
  2091 
       
  2092 	memset(addr, 0, sizeof(addr));
       
  2093 	memset(mask, 0, sizeof(mask));
       
  2094 
       
  2095 	if (dev->flags & IFF_PROMISC) {
       
  2096 		pff |= NVREG_PFF_PROMISC;
       
  2097 	} else {
       
  2098 		pff |= NVREG_PFF_MYADDR;
       
  2099 
       
  2100 		if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
       
  2101 			u32 alwaysOff[2];
       
  2102 			u32 alwaysOn[2];
       
  2103 
       
  2104 			alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
       
  2105 			if (dev->flags & IFF_ALLMULTI) {
       
  2106 				alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
       
  2107 			} else {
       
  2108 				struct dev_mc_list *walk;
       
  2109 
       
  2110 				walk = dev->mc_list;
       
  2111 				while (walk != NULL) {
       
  2112 					u32 a, b;
       
  2113 					a = le32_to_cpu(*(u32 *) walk->dmi_addr);
       
  2114 					b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
       
  2115 					alwaysOn[0] &= a;
       
  2116 					alwaysOff[0] &= ~a;
       
  2117 					alwaysOn[1] &= b;
       
  2118 					alwaysOff[1] &= ~b;
       
  2119 					walk = walk->next;
       
  2120 				}
       
  2121 			}
       
  2122 			addr[0] = alwaysOn[0];
       
  2123 			addr[1] = alwaysOn[1];
       
  2124 			mask[0] = alwaysOn[0] | alwaysOff[0];
       
  2125 			mask[1] = alwaysOn[1] | alwaysOff[1];
       
  2126 		}
       
  2127 	}
       
  2128 	addr[0] |= NVREG_MCASTADDRA_FORCE;
       
  2129 	pff |= NVREG_PFF_ALWAYS;
       
  2130 	spin_lock_irq(&np->lock);
       
  2131 	nv_stop_rx(dev);
       
  2132 	writel(addr[0], base + NvRegMulticastAddrA);
       
  2133 	writel(addr[1], base + NvRegMulticastAddrB);
       
  2134 	writel(mask[0], base + NvRegMulticastMaskA);
       
  2135 	writel(mask[1], base + NvRegMulticastMaskB);
       
  2136 	writel(pff, base + NvRegPacketFilterFlags);
       
  2137 	dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
       
  2138 		dev->name);
       
  2139 	nv_start_rx(dev);
       
  2140 	spin_unlock_irq(&np->lock);
       
  2141 }
       
  2142 
       
  2143 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
       
  2144 {
       
  2145 	struct fe_priv *np = netdev_priv(dev);
       
  2146 	u8 __iomem *base = get_hwbase(dev);
       
  2147 
       
  2148 	np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
       
  2149 
       
  2150 	if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
       
  2151 		u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
       
  2152 		if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
       
  2153 			writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
       
  2154 			np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
       
  2155 		} else {
       
  2156 			writel(pff, base + NvRegPacketFilterFlags);
       
  2157 		}
       
  2158 	}
       
  2159 	if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
       
  2160 		u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
       
  2161 		if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
       
  2162 			writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
       
  2163 			writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
       
  2164 			np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
       
  2165 		} else {
       
  2166 			writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
       
  2167 			writel(regmisc, base + NvRegMisc1);
       
  2168 		}
       
  2169 	}
       
  2170 }
       
  2171 
       
  2172 /**
       
  2173  * nv_update_linkspeed: Setup the MAC according to the link partner
       
  2174  * @dev: Network device to be configured
       
  2175  *
       
  2176  * The function queries the PHY and checks if there is a link partner.
       
  2177  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
       
  2178  * set to 10 MBit HD.
       
  2179  *
       
  2180  * The function returns 0 if there is no link partner and 1 if there is
       
  2181  * a good link partner.
       
  2182  */
       
  2183 static int nv_update_linkspeed(struct net_device *dev)
       
  2184 {
       
  2185 	struct fe_priv *np = netdev_priv(dev);
       
  2186 	u8 __iomem *base = get_hwbase(dev);
       
  2187 	int adv = 0;
       
  2188 	int lpa = 0;
       
  2189 	int adv_lpa, adv_pause, lpa_pause;
       
  2190 	int newls = np->linkspeed;
       
  2191 	int newdup = np->duplex;
       
  2192 	int mii_status;
       
  2193 	int retval = 0;
       
  2194 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;
       
  2195 
       
  2196 	/* BMSR_LSTATUS is latched, read it twice:
       
  2197 	 * we want the current value.
       
  2198 	 */
       
  2199 	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
       
  2200 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
       
  2201 
       
  2202 	if (!(mii_status & BMSR_LSTATUS)) {
       
  2203 		dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
       
  2204 				dev->name);
       
  2205 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2206 		newdup = 0;
       
  2207 		retval = 0;
       
  2208 		goto set_speed;
       
  2209 	}
       
  2210 
       
  2211 	if (np->autoneg == 0) {
       
  2212 		dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
       
  2213 				dev->name, np->fixed_mode);
       
  2214 		if (np->fixed_mode & LPA_100FULL) {
       
  2215 			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
       
  2216 			newdup = 1;
       
  2217 		} else if (np->fixed_mode & LPA_100HALF) {
       
  2218 			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
       
  2219 			newdup = 0;
       
  2220 		} else if (np->fixed_mode & LPA_10FULL) {
       
  2221 			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2222 			newdup = 1;
       
  2223 		} else {
       
  2224 			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2225 			newdup = 0;
       
  2226 		}
       
  2227 		retval = 1;
       
  2228 		goto set_speed;
       
  2229 	}
       
  2230 	/* check auto negotiation is complete */
       
  2231 	if (!(mii_status & BMSR_ANEGCOMPLETE)) {
       
  2232 		/* still in autonegotiation - configure nic for 10 MBit HD and wait. */
       
  2233 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2234 		newdup = 0;
       
  2235 		retval = 0;
       
  2236 		dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
       
  2237 		goto set_speed;
       
  2238 	}
       
  2239 
       
  2240 	adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
       
  2241 	lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
       
  2242 	dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
       
  2243 				dev->name, adv, lpa);
       
  2244 
       
  2245 	retval = 1;
       
  2246 	if (np->gigabit == PHY_GIGABIT) {
       
  2247 		control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
       
  2248 		status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
       
  2249 
       
  2250 		if ((control_1000 & ADVERTISE_1000FULL) &&
       
  2251 			(status_1000 & LPA_1000FULL)) {
       
  2252 			dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
       
  2253 				dev->name);
       
  2254 			newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
       
  2255 			newdup = 1;
       
  2256 			goto set_speed;
       
  2257 		}
       
  2258 	}
       
  2259 
       
  2260 	/* FIXME: handle parallel detection properly */
       
  2261 	adv_lpa = lpa & adv;
       
  2262 	if (adv_lpa & LPA_100FULL) {
       
  2263 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
       
  2264 		newdup = 1;
       
  2265 	} else if (adv_lpa & LPA_100HALF) {
       
  2266 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
       
  2267 		newdup = 0;
       
  2268 	} else if (adv_lpa & LPA_10FULL) {
       
  2269 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2270 		newdup = 1;
       
  2271 	} else if (adv_lpa & LPA_10HALF) {
       
  2272 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2273 		newdup = 0;
       
  2274 	} else {
       
  2275 		dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
       
  2276 		newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  2277 		newdup = 0;
       
  2278 	}
       
  2279 
       
  2280 set_speed:
       
  2281 	if (np->duplex == newdup && np->linkspeed == newls)
       
  2282 		return retval;
       
  2283 
       
  2284 	dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
       
  2285 			dev->name, np->linkspeed, np->duplex, newls, newdup);
       
  2286 
       
  2287 	np->duplex = newdup;
       
  2288 	np->linkspeed = newls;
       
  2289 
       
  2290 	if (np->gigabit == PHY_GIGABIT) {
       
  2291 		phyreg = readl(base + NvRegRandomSeed);
       
  2292 		phyreg &= ~(0x3FF00);
       
  2293 		if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
       
  2294 			phyreg |= NVREG_RNDSEED_FORCE3;
       
  2295 		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
       
  2296 			phyreg |= NVREG_RNDSEED_FORCE2;
       
  2297 		else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
       
  2298 			phyreg |= NVREG_RNDSEED_FORCE;
       
  2299 		writel(phyreg, base + NvRegRandomSeed);
       
  2300 	}
       
  2301 
       
  2302 	phyreg = readl(base + NvRegPhyInterface);
       
  2303 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
       
  2304 	if (np->duplex == 0)
       
  2305 		phyreg |= PHY_HALF;
       
  2306 	if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
       
  2307 		phyreg |= PHY_100;
       
  2308 	else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
       
  2309 		phyreg |= PHY_1000;
       
  2310 	writel(phyreg, base + NvRegPhyInterface);
       
  2311 
       
  2312 	if (phyreg & PHY_RGMII) {
       
  2313 		if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
       
  2314 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;
       
  2315 		else
       
  2316 			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
       
  2317 	} else {
       
  2318 		txreg = NVREG_TX_DEFERRAL_DEFAULT;
       
  2319 	}
       
  2320 	writel(txreg, base + NvRegTxDeferral);
       
  2321 
       
  2322 	if (np->desc_ver == DESC_VER_1) {
       
  2323 		txreg = NVREG_TX_WM_DESC1_DEFAULT;
       
  2324 	} else {
       
  2325 		if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
       
  2326 			txreg = NVREG_TX_WM_DESC2_3_1000;
       
  2327 		else
       
  2328 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
       
  2329 	}
       
  2330 	writel(txreg, base + NvRegTxWatermark);
       
  2331 
       
  2332 	writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
       
  2333 		base + NvRegMisc1);
       
  2334 	pci_push(base);
       
  2335 	writel(np->linkspeed, base + NvRegLinkSpeed);
       
  2336 	pci_push(base);
       
  2337 
       
  2338 	pause_flags = 0;
       
  2339 	/* setup pause frame */
       
  2340 	if (np->duplex != 0) {
       
  2341 		if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
       
  2342 			adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
       
  2343 			lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
       
  2344 
       
  2345 			switch (adv_pause) {
       
  2346 			case ADVERTISE_PAUSE_CAP:
       
  2347 				if (lpa_pause & LPA_PAUSE_CAP) {
       
  2348 					pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
       
  2349 					if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
       
  2350 						pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
       
  2351 				}
       
  2352 				break;
       
  2353 			case ADVERTISE_PAUSE_ASYM:
       
  2354 				if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
       
  2355 				{
       
  2356 					pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
       
  2357 				}
       
  2358 				break;
       
  2359 			case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
       
  2360 				if (lpa_pause & LPA_PAUSE_CAP)
       
  2361 				{
       
  2362 					pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
       
  2363 					if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
       
  2364 						pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
       
  2365 				}
       
  2366 				if (lpa_pause == LPA_PAUSE_ASYM)
       
  2367 				{
       
  2368 					pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
       
  2369 				}
       
  2370 				break;
       
  2371 			}
       
  2372 		} else {
       
  2373 			pause_flags = np->pause_flags;
       
  2374 		}
       
  2375 	}
       
  2376 	nv_update_pause(dev, pause_flags);
       
  2377 
       
  2378 	return retval;
       
  2379 }
       
  2380 
       
  2381 static void nv_linkchange(struct net_device *dev)
       
  2382 {
       
  2383 	struct fe_priv *np = netdev_priv(dev);
       
  2384 
       
  2385     if (np->ecdev) {
       
  2386         nv_update_linkspeed(dev);
       
  2387         return;
       
  2388     }
       
  2389 
       
  2390 	if (nv_update_linkspeed(dev)) {
       
  2391 		if (!netif_carrier_ok(dev)) {
       
  2392 			netif_carrier_on(dev);
       
  2393 			printk(KERN_INFO "%s: link up.\n", dev->name);
       
  2394 			nv_start_rx(dev);
       
  2395 		}
       
  2396 	} else {
       
  2397 		if (netif_carrier_ok(dev)) {
       
  2398 			netif_carrier_off(dev);
       
  2399 			printk(KERN_INFO "%s: link down.\n", dev->name);
       
  2400 			nv_stop_rx(dev);
       
  2401 		}
       
  2402 	}
       
  2403 }
       
  2404 
       
  2405 static void nv_link_irq(struct net_device *dev)
       
  2406 {
       
  2407 	u8 __iomem *base = get_hwbase(dev);
       
  2408 	u32 miistat;
       
  2409 
       
  2410 	miistat = readl(base + NvRegMIIStatus);
       
  2411 	writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
       
  2412 	dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
       
  2413 
       
  2414 	if (miistat & (NVREG_MIISTAT_LINKCHANGE))
       
  2415 		nv_linkchange(dev);
       
  2416 	dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
       
  2417 }
       
  2418 
       
  2419 static irqreturn_t nv_nic_irq(int foo, void *data)
       
  2420 {
       
  2421 	struct net_device *dev = (struct net_device *) data;
       
  2422 	struct fe_priv *np = netdev_priv(dev);
       
  2423 	u8 __iomem *base = get_hwbase(dev);
       
  2424 	u32 events;
       
  2425 	int i;
       
  2426 
       
  2427 	dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
       
  2428 
       
  2429 	for (i=0; ; i++) {
       
  2430 		if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
       
  2431 			events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
       
  2432 			writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
       
  2433 		} else {
       
  2434 			events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
       
  2435 			writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
       
  2436 		}
       
  2437 		pci_push(base);
       
  2438 		dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
       
  2439 		if (!(events & np->irqmask))
       
  2440 			break;
       
  2441 
       
  2442 		spin_lock(&np->lock);
       
  2443 		nv_tx_done(dev);
       
  2444 		spin_unlock(&np->lock);
       
  2445 
       
  2446 		if (events & NVREG_IRQ_LINK) {
       
  2447 			spin_lock(&np->lock);
       
  2448 			nv_link_irq(dev);
       
  2449 			spin_unlock(&np->lock);
       
  2450 		}
       
  2451 		if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
       
  2452 			spin_lock(&np->lock);
       
  2453 			nv_linkchange(dev);
       
  2454 			spin_unlock(&np->lock);
       
  2455 			np->link_timeout = jiffies + LINK_TIMEOUT;
       
  2456 		}
       
  2457 		if (events & (NVREG_IRQ_TX_ERR)) {
       
  2458 			dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
       
  2459 						dev->name, events);
       
  2460 		}
       
  2461 		if (events & (NVREG_IRQ_UNKNOWN)) {
       
  2462 			printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
       
  2463 						dev->name, events);
       
  2464 		}
       
  2465 #ifdef CONFIG_FORCEDETH_NAPI
       
  2466 		if (events & NVREG_IRQ_RX_ALL) {
       
  2467 			netif_rx_schedule(dev);
       
  2468 
       
  2469 			/* Disable furthur receive irq's */
       
  2470 			spin_lock(&np->lock);
       
  2471 			np->irqmask &= ~NVREG_IRQ_RX_ALL;
       
  2472 
       
  2473 			if (np->msi_flags & NV_MSI_X_ENABLED)
       
  2474 				writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
       
  2475 			else
       
  2476 				writel(np->irqmask, base + NvRegIrqMask);
       
  2477 			spin_unlock(&np->lock);
       
  2478 		}
       
  2479 #else
       
  2480 		nv_rx_process(dev, dev->weight);
       
  2481 		if (nv_alloc_rx(dev)) {
       
  2482 			spin_lock(&np->lock);
       
  2483 			if (!np->in_shutdown)
       
  2484 				mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  2485 			spin_unlock(&np->lock);
       
  2486 		}
       
  2487 #endif
       
  2488 		if (i > max_interrupt_work) {
       
  2489 			spin_lock(&np->lock);
       
  2490 			/* disable interrupts on the nic */
       
  2491 			if (!(np->msi_flags & NV_MSI_X_ENABLED))
       
  2492 				writel(0, base + NvRegIrqMask);
       
  2493 			else
       
  2494 				writel(np->irqmask, base + NvRegIrqMask);
       
  2495 			pci_push(base);
       
  2496 
       
  2497 			if (!np->in_shutdown) {
       
  2498 				np->nic_poll_irq = np->irqmask;
       
  2499 				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
       
  2500 			}
       
  2501 			printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
       
  2502 			spin_unlock(&np->lock);
       
  2503 			break;
       
  2504 		}
       
  2505 
       
  2506 	}
       
  2507 	dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
       
  2508 
       
  2509 	return IRQ_RETVAL(i);
       
  2510 }
       
  2511 
       
  2512 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
       
  2513 {
       
  2514 	struct net_device *dev = (struct net_device *) data;
       
  2515 	struct fe_priv *np = netdev_priv(dev);
       
  2516 	u8 __iomem *base = get_hwbase(dev);
       
  2517 	u32 events;
       
  2518 	int i;
       
  2519 	unsigned long flags;
       
  2520 
       
  2521 	dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
       
  2522 
       
  2523 	for (i=0; ; i++) {
       
  2524 		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
       
  2525 		writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
       
  2526 		pci_push(base);
       
  2527 		dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
       
  2528 		if (!(events & np->irqmask))
       
  2529 			break;
       
  2530 
       
  2531 		spin_lock_irqsave(&np->lock, flags);
       
  2532 		nv_tx_done(dev);
       
  2533 		spin_unlock_irqrestore(&np->lock, flags);
       
  2534 
       
  2535 		if (events & (NVREG_IRQ_TX_ERR)) {
       
  2536 			dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
       
  2537 						dev->name, events);
       
  2538 		}
       
  2539 		if (i > max_interrupt_work) {
       
  2540 			spin_lock_irqsave(&np->lock, flags);
       
  2541 			/* disable interrupts on the nic */
       
  2542 			writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
       
  2543 			pci_push(base);
       
  2544 
       
  2545 			if (!np->in_shutdown) {
       
  2546 				np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
       
  2547 				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
       
  2548 			}
       
  2549 			printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
       
  2550 			spin_unlock_irqrestore(&np->lock, flags);
       
  2551 			break;
       
  2552 		}
       
  2553 
       
  2554 	}
       
  2555 	dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
       
  2556 
       
  2557 	return IRQ_RETVAL(i);
       
  2558 }
       
  2559 
       
  2560 #ifdef CONFIG_FORCEDETH_NAPI
       
  2561 static int nv_napi_poll(struct net_device *dev, int *budget)
       
  2562 {
       
  2563 	int pkts, limit = min(*budget, dev->quota);
       
  2564 	struct fe_priv *np = netdev_priv(dev);
       
  2565 	u8 __iomem *base = get_hwbase(dev);
       
  2566 
       
  2567 	pkts = nv_rx_process(dev, limit);
       
  2568 
       
  2569 	if (nv_alloc_rx(dev)) {
       
  2570 		spin_lock_irq(&np->lock);
       
  2571 		if (!np->in_shutdown)
       
  2572 			mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  2573 		spin_unlock_irq(&np->lock);
       
  2574 	}
       
  2575 
       
  2576 	if (pkts < limit) {
       
  2577 		/* all done, no more packets present */
       
  2578 		netif_rx_complete(dev);
       
  2579 
       
  2580 		/* re-enable receive interrupts */
       
  2581 		spin_lock_irq(&np->lock);
       
  2582 		np->irqmask |= NVREG_IRQ_RX_ALL;
       
  2583 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
  2584 			writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
       
  2585 		else
       
  2586 			writel(np->irqmask, base + NvRegIrqMask);
       
  2587 		spin_unlock_irq(&np->lock);
       
  2588 		return 0;
       
  2589 	} else {
       
  2590 		/* used up our quantum, so reschedule */
       
  2591 		dev->quota -= pkts;
       
  2592 		*budget -= pkts;
       
  2593 		return 1;
       
  2594 	}
       
  2595 }
       
  2596 #endif
       
  2597 
       
  2598 #ifdef CONFIG_FORCEDETH_NAPI
       
  2599 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
       
  2600 {
       
  2601 	struct net_device *dev = (struct net_device *) data;
       
  2602 	u8 __iomem *base = get_hwbase(dev);
       
  2603 	u32 events;
       
  2604 
       
  2605 	events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
       
  2606 	writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
       
  2607 
       
  2608 	if (events) {
       
  2609 		netif_rx_schedule(dev);
       
  2610 		/* disable receive interrupts on the nic */
       
  2611 		writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
       
  2612 		pci_push(base);
       
  2613 	}
       
  2614 	return IRQ_HANDLED;
       
  2615 }
       
  2616 #else
       
  2617 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
       
  2618 {
       
  2619 	struct net_device *dev = (struct net_device *) data;
       
  2620 	struct fe_priv *np = netdev_priv(dev);
       
  2621 	u8 __iomem *base = get_hwbase(dev);
       
  2622 	u32 events;
       
  2623 	int i;
       
  2624 	unsigned long flags;
       
  2625 
       
  2626 	dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
       
  2627 
       
  2628 	for (i=0; ; i++) {
       
  2629 		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
       
  2630 		writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
       
  2631 		pci_push(base);
       
  2632 		dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
       
  2633 		if (!(events & np->irqmask))
       
  2634 			break;
       
  2635 
       
  2636 		nv_rx_process(dev, dev->weight);
       
  2637 		if (nv_alloc_rx(dev)) {
       
  2638 			spin_lock_irqsave(&np->lock, flags);
       
  2639 			if (!np->in_shutdown)
       
  2640 				mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  2641 			spin_unlock_irqrestore(&np->lock, flags);
       
  2642 		}
       
  2643 
       
  2644 		if (i > max_interrupt_work) {
       
  2645 			spin_lock_irqsave(&np->lock, flags);
       
  2646 			/* disable interrupts on the nic */
       
  2647 			writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
       
  2648 			pci_push(base);
       
  2649 
       
  2650 			if (!np->in_shutdown) {
       
  2651 				np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
       
  2652 				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
       
  2653 			}
       
  2654 			printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
       
  2655 			spin_unlock_irqrestore(&np->lock, flags);
       
  2656 			break;
       
  2657 		}
       
  2658 	}
       
  2659 	dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
       
  2660 
       
  2661 	return IRQ_RETVAL(i);
       
  2662 }
       
  2663 #endif
       
  2664 
       
  2665 static irqreturn_t nv_nic_irq_other(int foo, void *data)
       
  2666 {
       
  2667 	struct net_device *dev = (struct net_device *) data;
       
  2668 	struct fe_priv *np = netdev_priv(dev);
       
  2669 	u8 __iomem *base = get_hwbase(dev);
       
  2670 	u32 events;
       
  2671 	int i;
       
  2672 	unsigned long flags;
       
  2673 
       
  2674 	dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
       
  2675 
       
  2676 	for (i=0; ; i++) {
       
  2677 		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
       
  2678 		writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
       
  2679 		pci_push(base);
       
  2680 		dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
       
  2681 		if (!(events & np->irqmask))
       
  2682 			break;
       
  2683 
       
  2684 		if (events & NVREG_IRQ_LINK) {
       
  2685 			spin_lock_irqsave(&np->lock, flags);
       
  2686 			nv_link_irq(dev);
       
  2687 			spin_unlock_irqrestore(&np->lock, flags);
       
  2688 		}
       
  2689 		if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
       
  2690 			spin_lock_irqsave(&np->lock, flags);
       
  2691 			nv_linkchange(dev);
       
  2692 			spin_unlock_irqrestore(&np->lock, flags);
       
  2693 			np->link_timeout = jiffies + LINK_TIMEOUT;
       
  2694 		}
       
  2695 		if (events & (NVREG_IRQ_UNKNOWN)) {
       
  2696 			printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
       
  2697 						dev->name, events);
       
  2698 		}
       
  2699 		if (i > max_interrupt_work) {
       
  2700 			spin_lock_irqsave(&np->lock, flags);
       
  2701 			/* disable interrupts on the nic */
       
  2702 			writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
       
  2703 			pci_push(base);
       
  2704 
       
  2705 			if (!np->in_shutdown) {
       
  2706 				np->nic_poll_irq |= NVREG_IRQ_OTHER;
       
  2707 				mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
       
  2708 			}
       
  2709 			printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
       
  2710 			spin_unlock_irqrestore(&np->lock, flags);
       
  2711 			break;
       
  2712 		}
       
  2713 
       
  2714 	}
       
  2715 	dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
       
  2716 
       
  2717 	return IRQ_RETVAL(i);
       
  2718 }
       
  2719 
       
  2720 static irqreturn_t nv_nic_irq_test(int foo, void *data)
       
  2721 {
       
  2722 	struct net_device *dev = (struct net_device *) data;
       
  2723 	struct fe_priv *np = netdev_priv(dev);
       
  2724 	u8 __iomem *base = get_hwbase(dev);
       
  2725 	u32 events;
       
  2726 
       
  2727 	dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
       
  2728 
       
  2729 	if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
       
  2730 		events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
       
  2731 		writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
       
  2732 	} else {
       
  2733 		events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
       
  2734 		writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
       
  2735 	}
       
  2736 	pci_push(base);
       
  2737 	dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
       
  2738 	if (!(events & NVREG_IRQ_TIMER))
       
  2739 		return IRQ_RETVAL(0);
       
  2740 
       
  2741 	spin_lock(&np->lock);
       
  2742 	np->intr_test = 1;
       
  2743 	spin_unlock(&np->lock);
       
  2744 
       
  2745 	dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
       
  2746 
       
  2747 	return IRQ_RETVAL(1);
       
  2748 }
       
  2749 
       
  2750 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
       
  2751 {
       
  2752 	u8 __iomem *base = get_hwbase(dev);
       
  2753 	int i;
       
  2754 	u32 msixmap = 0;
       
  2755 
       
  2756 	/* Each interrupt bit can be mapped to a MSIX vector (4 bits).
       
  2757 	 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
       
  2758 	 * the remaining 8 interrupts.
       
  2759 	 */
       
  2760 	for (i = 0; i < 8; i++) {
       
  2761 		if ((irqmask >> i) & 0x1) {
       
  2762 			msixmap |= vector << (i << 2);
       
  2763 		}
       
  2764 	}
       
  2765 	writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
       
  2766 
       
  2767 	msixmap = 0;
       
  2768 	for (i = 0; i < 8; i++) {
       
  2769 		if ((irqmask >> (i + 8)) & 0x1) {
       
  2770 			msixmap |= vector << (i << 2);
       
  2771 		}
       
  2772 	}
       
  2773 	writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
       
  2774 }
       
  2775 
       
  2776 static int nv_request_irq(struct net_device *dev, int intr_test)
       
  2777 {
       
  2778 	struct fe_priv *np = get_nvpriv(dev);
       
  2779 	u8 __iomem *base = get_hwbase(dev);
       
  2780 	int ret = 1;
       
  2781 	int i;
       
  2782 
       
  2783 	if (np->msi_flags & NV_MSI_X_CAPABLE) {
       
  2784 		for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
       
  2785 			np->msi_x_entry[i].entry = i;
       
  2786 		}
       
  2787 		if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
       
  2788 			np->msi_flags |= NV_MSI_X_ENABLED;
       
  2789 			if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
       
  2790 				/* Request irq for rx handling */
       
  2791 				if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
       
  2792 					printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
       
  2793 					pci_disable_msix(np->pci_dev);
       
  2794 					np->msi_flags &= ~NV_MSI_X_ENABLED;
       
  2795 					goto out_err;
       
  2796 				}
       
  2797 				/* Request irq for tx handling */
       
  2798 				if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
       
  2799 					printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
       
  2800 					pci_disable_msix(np->pci_dev);
       
  2801 					np->msi_flags &= ~NV_MSI_X_ENABLED;
       
  2802 					goto out_free_rx;
       
  2803 				}
       
  2804 				/* Request irq for link and timer handling */
       
  2805 				if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
       
  2806 					printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
       
  2807 					pci_disable_msix(np->pci_dev);
       
  2808 					np->msi_flags &= ~NV_MSI_X_ENABLED;
       
  2809 					goto out_free_tx;
       
  2810 				}
       
  2811 				/* map interrupts to their respective vector */
       
  2812 				writel(0, base + NvRegMSIXMap0);
       
  2813 				writel(0, base + NvRegMSIXMap1);
       
  2814 				set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
       
  2815 				set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
       
  2816 				set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
       
  2817 			} else {
       
  2818 				/* Request irq for all interrupts */
       
  2819 				if ((!intr_test &&
       
  2820 				     request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
       
  2821 				    (intr_test &&
       
  2822 				     request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
       
  2823 					printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
       
  2824 					pci_disable_msix(np->pci_dev);
       
  2825 					np->msi_flags &= ~NV_MSI_X_ENABLED;
       
  2826 					goto out_err;
       
  2827 				}
       
  2828 
       
  2829 				/* map interrupts to vector 0 */
       
  2830 				writel(0, base + NvRegMSIXMap0);
       
  2831 				writel(0, base + NvRegMSIXMap1);
       
  2832 			}
       
  2833 		}
       
  2834 	}
       
  2835 	if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
       
  2836 		if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
       
  2837 			pci_intx(np->pci_dev, 0);
       
  2838 			np->msi_flags |= NV_MSI_ENABLED;
       
  2839 			if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
       
  2840 			    (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
       
  2841 				printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
       
  2842 				pci_disable_msi(np->pci_dev);
       
  2843 				pci_intx(np->pci_dev, 1);
       
  2844 				np->msi_flags &= ~NV_MSI_ENABLED;
       
  2845 				goto out_err;
       
  2846 			}
       
  2847 
       
  2848 			/* map interrupts to vector 0 */
       
  2849 			writel(0, base + NvRegMSIMap0);
       
  2850 			writel(0, base + NvRegMSIMap1);
       
  2851 			/* enable msi vector 0 */
       
  2852 			writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
       
  2853 		}
       
  2854 	}
       
  2855 	if (ret != 0) {
       
  2856 		if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
       
  2857 		    (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
       
  2858 			goto out_err;
       
  2859 
       
  2860 	}
       
  2861 
       
  2862 	return 0;
       
  2863 out_free_tx:
       
  2864 	free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
       
  2865 out_free_rx:
       
  2866 	free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
       
  2867 out_err:
       
  2868 	return 1;
       
  2869 }
       
  2870 
       
  2871 static void nv_free_irq(struct net_device *dev)
       
  2872 {
       
  2873 	struct fe_priv *np = get_nvpriv(dev);
       
  2874 	int i;
       
  2875 
       
  2876 	if (np->msi_flags & NV_MSI_X_ENABLED) {
       
  2877 		for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
       
  2878 			free_irq(np->msi_x_entry[i].vector, dev);
       
  2879 		}
       
  2880 		pci_disable_msix(np->pci_dev);
       
  2881 		np->msi_flags &= ~NV_MSI_X_ENABLED;
       
  2882 	} else {
       
  2883 		free_irq(np->pci_dev->irq, dev);
       
  2884 		if (np->msi_flags & NV_MSI_ENABLED) {
       
  2885 			pci_disable_msi(np->pci_dev);
       
  2886 			pci_intx(np->pci_dev, 1);
       
  2887 			np->msi_flags &= ~NV_MSI_ENABLED;
       
  2888 		}
       
  2889 	}
       
  2890 }
       
  2891 
       
  2892 void ec_poll(struct net_device *dev)
       
  2893 {
       
  2894     nv_nic_irq((int) 0, dev, (struct pt_regs *) NULL);
       
  2895 }
       
  2896 
       
  2897 static void nv_do_nic_poll(unsigned long data)
       
  2898 {
       
  2899 	struct net_device *dev = (struct net_device *) data;
       
  2900 	struct fe_priv *np = netdev_priv(dev);
       
  2901 	u8 __iomem *base = get_hwbase(dev);
       
  2902 	u32 mask = 0;
       
  2903 
       
  2904 	/*
       
  2905 	 * First disable irq(s) and then
       
  2906 	 * reenable interrupts on the nic, we have to do this before calling
       
  2907 	 * nv_nic_irq because that may decide to do otherwise
       
  2908 	 */
       
  2909 
       
  2910 	if (!using_multi_irqs(dev)) {
       
  2911 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
  2912 			disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
       
  2913 		else
       
  2914 			disable_irq_lockdep(dev->irq);
       
  2915 		mask = np->irqmask;
       
  2916 	} else {
       
  2917 		if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
       
  2918 			disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
       
  2919 			mask |= NVREG_IRQ_RX_ALL;
       
  2920 		}
       
  2921 		if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
       
  2922 			disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
       
  2923 			mask |= NVREG_IRQ_TX_ALL;
       
  2924 		}
       
  2925 		if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
       
  2926 			disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
       
  2927 			mask |= NVREG_IRQ_OTHER;
       
  2928 		}
       
  2929 	}
       
  2930 	np->nic_poll_irq = 0;
       
  2931 
       
  2932 	/* FIXME: Do we need synchronize_irq(dev->irq) here? */
       
  2933 
       
  2934 	writel(mask, base + NvRegIrqMask);
       
  2935 	pci_push(base);
       
  2936 
       
  2937 	if (!using_multi_irqs(dev)) {
       
  2938 		nv_nic_irq(0, dev);
       
  2939 		if (np->msi_flags & NV_MSI_X_ENABLED)
       
  2940 			enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
       
  2941 		else
       
  2942 			enable_irq_lockdep(dev->irq);
       
  2943 	} else {
       
  2944 		if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
       
  2945 			nv_nic_irq_rx(0, dev);
       
  2946 			enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
       
  2947 		}
       
  2948 		if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
       
  2949 			nv_nic_irq_tx(0, dev);
       
  2950 			enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
       
  2951 		}
       
  2952 		if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
       
  2953 			nv_nic_irq_other(0, dev);
       
  2954 			enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
       
  2955 		}
       
  2956 	}
       
  2957 }
       
  2958 
       
  2959 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  2960 static void nv_poll_controller(struct net_device *dev)
       
  2961 {
       
  2962 	nv_do_nic_poll((unsigned long) dev);
       
  2963 }
       
  2964 #endif
       
  2965 
       
  2966 static void nv_do_stats_poll(unsigned long data)
       
  2967 {
       
  2968 	struct net_device *dev = (struct net_device *) data;
       
  2969 	struct fe_priv *np = netdev_priv(dev);
       
  2970 	u8 __iomem *base = get_hwbase(dev);
       
  2971 
       
  2972 	np->estats.tx_bytes += readl(base + NvRegTxCnt);
       
  2973 	np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
       
  2974 	np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
       
  2975 	np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
       
  2976 	np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
       
  2977 	np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
       
  2978 	np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
       
  2979 	np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
       
  2980 	np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
       
  2981 	np->estats.tx_deferral += readl(base + NvRegTxDef);
       
  2982 	np->estats.tx_packets += readl(base + NvRegTxFrame);
       
  2983 	np->estats.tx_pause += readl(base + NvRegTxPause);
       
  2984 	np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
       
  2985 	np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
       
  2986 	np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
       
  2987 	np->estats.rx_runt += readl(base + NvRegRxRunt);
       
  2988 	np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
       
  2989 	np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
       
  2990 	np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
       
  2991 	np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
       
  2992 	np->estats.rx_length_error += readl(base + NvRegRxLenErr);
       
  2993 	np->estats.rx_unicast += readl(base + NvRegRxUnicast);
       
  2994 	np->estats.rx_multicast += readl(base + NvRegRxMulticast);
       
  2995 	np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
       
  2996 	np->estats.rx_bytes += readl(base + NvRegRxCnt);
       
  2997 	np->estats.rx_pause += readl(base + NvRegRxPause);
       
  2998 	np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
       
  2999 	np->estats.rx_packets =
       
  3000 		np->estats.rx_unicast +
       
  3001 		np->estats.rx_multicast +
       
  3002 		np->estats.rx_broadcast;
       
  3003 	np->estats.rx_errors_total =
       
  3004 		np->estats.rx_crc_errors +
       
  3005 		np->estats.rx_over_errors +
       
  3006 		np->estats.rx_frame_error +
       
  3007 		(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
       
  3008 		np->estats.rx_late_collision +
       
  3009 		np->estats.rx_runt +
       
  3010 		np->estats.rx_frame_too_long;
       
  3011 
       
  3012 	if (!np->in_shutdown)
       
  3013 		mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
       
  3014 }
       
  3015 
       
  3016 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
       
  3017 {
       
  3018 	struct fe_priv *np = netdev_priv(dev);
       
  3019 	strcpy(info->driver, "forcedeth");
       
  3020 	strcpy(info->version, FORCEDETH_VERSION);
       
  3021 	strcpy(info->bus_info, pci_name(np->pci_dev));
       
  3022 }
       
  3023 
       
  3024 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
       
  3025 {
       
  3026 	struct fe_priv *np = netdev_priv(dev);
       
  3027 	wolinfo->supported = WAKE_MAGIC;
       
  3028 
       
  3029 	spin_lock_irq(&np->lock);
       
  3030 	if (np->wolenabled)
       
  3031 		wolinfo->wolopts = WAKE_MAGIC;
       
  3032 	spin_unlock_irq(&np->lock);
       
  3033 }
       
  3034 
       
  3035 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
       
  3036 {
       
  3037 	struct fe_priv *np = netdev_priv(dev);
       
  3038 	u8 __iomem *base = get_hwbase(dev);
       
  3039 	u32 flags = 0;
       
  3040 
       
  3041 	if (wolinfo->wolopts == 0) {
       
  3042 		np->wolenabled = 0;
       
  3043 	} else if (wolinfo->wolopts & WAKE_MAGIC) {
       
  3044 		np->wolenabled = 1;
       
  3045 		flags = NVREG_WAKEUPFLAGS_ENABLE;
       
  3046 	}
       
  3047 	if (netif_running(dev)) {
       
  3048 		spin_lock_irq(&np->lock);
       
  3049 		writel(flags, base + NvRegWakeUpFlags);
       
  3050 		spin_unlock_irq(&np->lock);
       
  3051 	}
       
  3052 	return 0;
       
  3053 }
       
  3054 
       
  3055 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
       
  3056 {
       
  3057 	struct fe_priv *np = netdev_priv(dev);
       
  3058 	int adv;
       
  3059 
       
  3060 	spin_lock_irq(&np->lock);
       
  3061 	ecmd->port = PORT_MII;
       
  3062 	if (!netif_running(dev)) {
       
  3063 		/* We do not track link speed / duplex setting if the
       
  3064 		 * interface is disabled. Force a link check */
       
  3065 		if (nv_update_linkspeed(dev)) {
       
  3066 			if (!netif_carrier_ok(dev))
       
  3067 				netif_carrier_on(dev);
       
  3068 		} else {
       
  3069 			if (netif_carrier_ok(dev))
       
  3070 				netif_carrier_off(dev);
       
  3071 		}
       
  3072 	}
       
  3073 
       
  3074 	if (netif_carrier_ok(dev)) {
       
  3075 		switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
       
  3076 		case NVREG_LINKSPEED_10:
       
  3077 			ecmd->speed = SPEED_10;
       
  3078 			break;
       
  3079 		case NVREG_LINKSPEED_100:
       
  3080 			ecmd->speed = SPEED_100;
       
  3081 			break;
       
  3082 		case NVREG_LINKSPEED_1000:
       
  3083 			ecmd->speed = SPEED_1000;
       
  3084 			break;
       
  3085 		}
       
  3086 		ecmd->duplex = DUPLEX_HALF;
       
  3087 		if (np->duplex)
       
  3088 			ecmd->duplex = DUPLEX_FULL;
       
  3089 	} else {
       
  3090 		ecmd->speed = -1;
       
  3091 		ecmd->duplex = -1;
       
  3092 	}
       
  3093 
       
  3094 	ecmd->autoneg = np->autoneg;
       
  3095 
       
  3096 	ecmd->advertising = ADVERTISED_MII;
       
  3097 	if (np->autoneg) {
       
  3098 		ecmd->advertising |= ADVERTISED_Autoneg;
       
  3099 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
       
  3100 		if (adv & ADVERTISE_10HALF)
       
  3101 			ecmd->advertising |= ADVERTISED_10baseT_Half;
       
  3102 		if (adv & ADVERTISE_10FULL)
       
  3103 			ecmd->advertising |= ADVERTISED_10baseT_Full;
       
  3104 		if (adv & ADVERTISE_100HALF)
       
  3105 			ecmd->advertising |= ADVERTISED_100baseT_Half;
       
  3106 		if (adv & ADVERTISE_100FULL)
       
  3107 			ecmd->advertising |= ADVERTISED_100baseT_Full;
       
  3108 		if (np->gigabit == PHY_GIGABIT) {
       
  3109 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
       
  3110 			if (adv & ADVERTISE_1000FULL)
       
  3111 				ecmd->advertising |= ADVERTISED_1000baseT_Full;
       
  3112 		}
       
  3113 	}
       
  3114 	ecmd->supported = (SUPPORTED_Autoneg |
       
  3115 		SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
       
  3116 		SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
       
  3117 		SUPPORTED_MII);
       
  3118 	if (np->gigabit == PHY_GIGABIT)
       
  3119 		ecmd->supported |= SUPPORTED_1000baseT_Full;
       
  3120 
       
  3121 	ecmd->phy_address = np->phyaddr;
       
  3122 	ecmd->transceiver = XCVR_EXTERNAL;
       
  3123 
       
  3124 	/* ignore maxtxpkt, maxrxpkt for now */
       
  3125 	spin_unlock_irq(&np->lock);
       
  3126 	return 0;
       
  3127 }
       
  3128 
       
  3129 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
       
  3130 {
       
  3131 	struct fe_priv *np = netdev_priv(dev);
       
  3132 
       
  3133 	if (ecmd->port != PORT_MII)
       
  3134 		return -EINVAL;
       
  3135 	if (ecmd->transceiver != XCVR_EXTERNAL)
       
  3136 		return -EINVAL;
       
  3137 	if (ecmd->phy_address != np->phyaddr) {
       
  3138 		/* TODO: support switching between multiple phys. Should be
       
  3139 		 * trivial, but not enabled due to lack of test hardware. */
       
  3140 		return -EINVAL;
       
  3141 	}
       
  3142 	if (ecmd->autoneg == AUTONEG_ENABLE) {
       
  3143 		u32 mask;
       
  3144 
       
  3145 		mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
       
  3146 			  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
       
  3147 		if (np->gigabit == PHY_GIGABIT)
       
  3148 			mask |= ADVERTISED_1000baseT_Full;
       
  3149 
       
  3150 		if ((ecmd->advertising & mask) == 0)
       
  3151 			return -EINVAL;
       
  3152 
       
  3153 	} else if (ecmd->autoneg == AUTONEG_DISABLE) {
       
  3154 		/* Note: autonegotiation disable, speed 1000 intentionally
       
  3155 		 * forbidden - noone should need that. */
       
  3156 
       
  3157 		if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
       
  3158 			return -EINVAL;
       
  3159 		if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
       
  3160 			return -EINVAL;
       
  3161 	} else {
       
  3162 		return -EINVAL;
       
  3163 	}
       
  3164 
       
  3165 	netif_carrier_off(dev);
       
  3166 	if (netif_running(dev)) {
       
  3167 		nv_disable_irq(dev);
       
  3168 		netif_tx_lock_bh(dev);
       
  3169 		spin_lock(&np->lock);
       
  3170 		/* stop engines */
       
  3171 		nv_stop_rx(dev);
       
  3172 		nv_stop_tx(dev);
       
  3173 		spin_unlock(&np->lock);
       
  3174 		netif_tx_unlock_bh(dev);
       
  3175 	}
       
  3176 
       
  3177 	if (ecmd->autoneg == AUTONEG_ENABLE) {
       
  3178 		int adv, bmcr;
       
  3179 
       
  3180 		np->autoneg = 1;
       
  3181 
       
  3182 		/* advertise only what has been requested */
       
  3183 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
       
  3184 		adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
       
  3185 		if (ecmd->advertising & ADVERTISED_10baseT_Half)
       
  3186 			adv |= ADVERTISE_10HALF;
       
  3187 		if (ecmd->advertising & ADVERTISED_10baseT_Full)
       
  3188 			adv |= ADVERTISE_10FULL;
       
  3189 		if (ecmd->advertising & ADVERTISED_100baseT_Half)
       
  3190 			adv |= ADVERTISE_100HALF;
       
  3191 		if (ecmd->advertising & ADVERTISED_100baseT_Full)
       
  3192 			adv |= ADVERTISE_100FULL;
       
  3193 		if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
       
  3194 			adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
       
  3195 		if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
       
  3196 			adv |=  ADVERTISE_PAUSE_ASYM;
       
  3197 		mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
       
  3198 
       
  3199 		if (np->gigabit == PHY_GIGABIT) {
       
  3200 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
       
  3201 			adv &= ~ADVERTISE_1000FULL;
       
  3202 			if (ecmd->advertising & ADVERTISED_1000baseT_Full)
       
  3203 				adv |= ADVERTISE_1000FULL;
       
  3204 			mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
       
  3205 		}
       
  3206 
       
  3207 		if (netif_running(dev))
       
  3208 			printk(KERN_INFO "%s: link down.\n", dev->name);
       
  3209 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  3210 		if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
       
  3211 			bmcr |= BMCR_ANENABLE;
       
  3212 			/* reset the phy in order for settings to stick,
       
  3213 			 * and cause autoneg to start */
       
  3214 			if (phy_reset(dev, bmcr)) {
       
  3215 				printk(KERN_INFO "%s: phy reset failed\n", dev->name);
       
  3216 				return -EINVAL;
       
  3217 			}
       
  3218 		} else {
       
  3219 			bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
       
  3220 			mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
       
  3221 		}
       
  3222 	} else {
       
  3223 		int adv, bmcr;
       
  3224 
       
  3225 		np->autoneg = 0;
       
  3226 
       
  3227 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
       
  3228 		adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
       
  3229 		if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
       
  3230 			adv |= ADVERTISE_10HALF;
       
  3231 		if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
       
  3232 			adv |= ADVERTISE_10FULL;
       
  3233 		if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
       
  3234 			adv |= ADVERTISE_100HALF;
       
  3235 		if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
       
  3236 			adv |= ADVERTISE_100FULL;
       
  3237 		np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
       
  3238 		if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
       
  3239 			adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
       
  3240 			np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
       
  3241 		}
       
  3242 		if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
       
  3243 			adv |=  ADVERTISE_PAUSE_ASYM;
       
  3244 			np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
       
  3245 		}
       
  3246 		mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
       
  3247 		np->fixed_mode = adv;
       
  3248 
       
  3249 		if (np->gigabit == PHY_GIGABIT) {
       
  3250 			adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
       
  3251 			adv &= ~ADVERTISE_1000FULL;
       
  3252 			mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
       
  3253 		}
       
  3254 
       
  3255 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  3256 		bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
       
  3257 		if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
       
  3258 			bmcr |= BMCR_FULLDPLX;
       
  3259 		if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
       
  3260 			bmcr |= BMCR_SPEED100;
       
  3261 		if (np->phy_oui == PHY_OUI_MARVELL) {
       
  3262 			/* reset the phy in order for forced mode settings to stick */
       
  3263 			if (phy_reset(dev, bmcr)) {
       
  3264 				printk(KERN_INFO "%s: phy reset failed\n", dev->name);
       
  3265 				return -EINVAL;
       
  3266 			}
       
  3267 		} else {
       
  3268 			mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
       
  3269 			if (netif_running(dev)) {
       
  3270 				/* Wait a bit and then reconfigure the nic. */
       
  3271 				udelay(10);
       
  3272 				nv_linkchange(dev);
       
  3273 			}
       
  3274 		}
       
  3275 	}
       
  3276 
       
  3277 	if (netif_running(dev)) {
       
  3278 		nv_start_rx(dev);
       
  3279 		nv_start_tx(dev);
       
  3280 		nv_enable_irq(dev);
       
  3281 	}
       
  3282 
       
  3283 	return 0;
       
  3284 }
       
  3285 
       
  3286 #define FORCEDETH_REGS_VER	1
       
  3287 
       
  3288 static int nv_get_regs_len(struct net_device *dev)
       
  3289 {
       
  3290 	struct fe_priv *np = netdev_priv(dev);
       
  3291 	return np->register_size;
       
  3292 }
       
  3293 
       
  3294 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
       
  3295 {
       
  3296 	struct fe_priv *np = netdev_priv(dev);
       
  3297 	u8 __iomem *base = get_hwbase(dev);
       
  3298 	u32 *rbuf = buf;
       
  3299 	int i;
       
  3300 
       
  3301 	regs->version = FORCEDETH_REGS_VER;
       
  3302 	spin_lock_irq(&np->lock);
       
  3303 	for (i = 0;i <= np->register_size/sizeof(u32); i++)
       
  3304 		rbuf[i] = readl(base + i*sizeof(u32));
       
  3305 	spin_unlock_irq(&np->lock);
       
  3306 }
       
  3307 
       
  3308 static int nv_nway_reset(struct net_device *dev)
       
  3309 {
       
  3310 	struct fe_priv *np = netdev_priv(dev);
       
  3311 	int ret;
       
  3312 
       
  3313 	if (np->autoneg) {
       
  3314 		int bmcr;
       
  3315 
       
  3316 		netif_carrier_off(dev);
       
  3317 		if (netif_running(dev)) {
       
  3318 			nv_disable_irq(dev);
       
  3319 			netif_tx_lock_bh(dev);
       
  3320 			spin_lock(&np->lock);
       
  3321 			/* stop engines */
       
  3322 			nv_stop_rx(dev);
       
  3323 			nv_stop_tx(dev);
       
  3324 			spin_unlock(&np->lock);
       
  3325 			netif_tx_unlock_bh(dev);
       
  3326 			printk(KERN_INFO "%s: link down.\n", dev->name);
       
  3327 		}
       
  3328 
       
  3329 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  3330 		if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
       
  3331 			bmcr |= BMCR_ANENABLE;
       
  3332 			/* reset the phy in order for settings to stick*/
       
  3333 			if (phy_reset(dev, bmcr)) {
       
  3334 				printk(KERN_INFO "%s: phy reset failed\n", dev->name);
       
  3335 				return -EINVAL;
       
  3336 			}
       
  3337 		} else {
       
  3338 			bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
       
  3339 			mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
       
  3340 		}
       
  3341 
       
  3342 		if (netif_running(dev)) {
       
  3343 			nv_start_rx(dev);
       
  3344 			nv_start_tx(dev);
       
  3345 			nv_enable_irq(dev);
       
  3346 		}
       
  3347 		ret = 0;
       
  3348 	} else {
       
  3349 		ret = -EINVAL;
       
  3350 	}
       
  3351 
       
  3352 	return ret;
       
  3353 }
       
  3354 
       
  3355 static int nv_set_tso(struct net_device *dev, u32 value)
       
  3356 {
       
  3357 	struct fe_priv *np = netdev_priv(dev);
       
  3358 
       
  3359 	if ((np->driver_data & DEV_HAS_CHECKSUM))
       
  3360 		return ethtool_op_set_tso(dev, value);
       
  3361 	else
       
  3362 		return -EOPNOTSUPP;
       
  3363 }
       
  3364 
       
  3365 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
       
  3366 {
       
  3367 	struct fe_priv *np = netdev_priv(dev);
       
  3368 
       
  3369 	ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
       
  3370 	ring->rx_mini_max_pending = 0;
       
  3371 	ring->rx_jumbo_max_pending = 0;
       
  3372 	ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
       
  3373 
       
  3374 	ring->rx_pending = np->rx_ring_size;
       
  3375 	ring->rx_mini_pending = 0;
       
  3376 	ring->rx_jumbo_pending = 0;
       
  3377 	ring->tx_pending = np->tx_ring_size;
       
  3378 }
       
  3379 
       
  3380 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
       
  3381 {
       
  3382 	struct fe_priv *np = netdev_priv(dev);
       
  3383 	u8 __iomem *base = get_hwbase(dev);
       
  3384 	u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
       
  3385 	dma_addr_t ring_addr;
       
  3386 
       
  3387 	if (ring->rx_pending < RX_RING_MIN ||
       
  3388 	    ring->tx_pending < TX_RING_MIN ||
       
  3389 	    ring->rx_mini_pending != 0 ||
       
  3390 	    ring->rx_jumbo_pending != 0 ||
       
  3391 	    (np->desc_ver == DESC_VER_1 &&
       
  3392 	     (ring->rx_pending > RING_MAX_DESC_VER_1 ||
       
  3393 	      ring->tx_pending > RING_MAX_DESC_VER_1)) ||
       
  3394 	    (np->desc_ver != DESC_VER_1 &&
       
  3395 	     (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
       
  3396 	      ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
       
  3397 		return -EINVAL;
       
  3398 	}
       
  3399 
       
  3400 	/* allocate new rings */
       
  3401 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  3402 		rxtx_ring = pci_alloc_consistent(np->pci_dev,
       
  3403 					    sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
       
  3404 					    &ring_addr);
       
  3405 	} else {
       
  3406 		rxtx_ring = pci_alloc_consistent(np->pci_dev,
       
  3407 					    sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
       
  3408 					    &ring_addr);
       
  3409 	}
       
  3410 	rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
       
  3411 	rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
       
  3412 	tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
       
  3413 	tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
       
  3414 	tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
       
  3415 	if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
       
  3416 		/* fall back to old rings */
       
  3417 		if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  3418 			if (rxtx_ring)
       
  3419 				pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
       
  3420 						    rxtx_ring, ring_addr);
       
  3421 		} else {
       
  3422 			if (rxtx_ring)
       
  3423 				pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
       
  3424 						    rxtx_ring, ring_addr);
       
  3425 		}
       
  3426 		if (rx_skbuff)
       
  3427 			kfree(rx_skbuff);
       
  3428 		if (rx_dma)
       
  3429 			kfree(rx_dma);
       
  3430 		if (tx_skbuff)
       
  3431 			kfree(tx_skbuff);
       
  3432 		if (tx_dma)
       
  3433 			kfree(tx_dma);
       
  3434 		if (tx_dma_len)
       
  3435 			kfree(tx_dma_len);
       
  3436 		goto exit;
       
  3437 	}
       
  3438 
       
  3439 	if (netif_running(dev)) {
       
  3440 		nv_disable_irq(dev);
       
  3441 		netif_tx_lock_bh(dev);
       
  3442 		spin_lock(&np->lock);
       
  3443 		/* stop engines */
       
  3444 		nv_stop_rx(dev);
       
  3445 		nv_stop_tx(dev);
       
  3446 		nv_txrx_reset(dev);
       
  3447 		/* drain queues */
       
  3448 		nv_drain_rx(dev);
       
  3449 		nv_drain_tx(dev);
       
  3450 		/* delete queues */
       
  3451 		free_rings(dev);
       
  3452 	}
       
  3453 
       
  3454 	/* set new values */
       
  3455 	np->rx_ring_size = ring->rx_pending;
       
  3456 	np->tx_ring_size = ring->tx_pending;
       
  3457 	np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
       
  3458 	np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
       
  3459 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  3460 		np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
       
  3461 		np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
       
  3462 	} else {
       
  3463 		np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
       
  3464 		np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
       
  3465 	}
       
  3466 	np->rx_skbuff = (struct sk_buff**)rx_skbuff;
       
  3467 	np->rx_dma = (dma_addr_t*)rx_dma;
       
  3468 	np->tx_skbuff = (struct sk_buff**)tx_skbuff;
       
  3469 	np->tx_dma = (dma_addr_t*)tx_dma;
       
  3470 	np->tx_dma_len = (unsigned int*)tx_dma_len;
       
  3471 	np->ring_addr = ring_addr;
       
  3472 
       
  3473 	memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
       
  3474 	memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
       
  3475 	memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
       
  3476 	memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
       
  3477 	memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
       
  3478 
       
  3479 	if (netif_running(dev)) {
       
  3480 		/* reinit driver view of the queues */
       
  3481 		set_bufsize(dev);
       
  3482 		if (nv_init_ring(dev)) {
       
  3483 			if (!np->in_shutdown)
       
  3484 				mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  3485 		}
       
  3486 
       
  3487 		/* reinit nic view of the queues */
       
  3488 		writel(np->rx_buf_sz, base + NvRegOffloadConfig);
       
  3489 		setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
       
  3490 		writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
       
  3491 			base + NvRegRingSizes);
       
  3492 		pci_push(base);
       
  3493 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
       
  3494 		pci_push(base);
       
  3495 
       
  3496 		/* restart engines */
       
  3497 		nv_start_rx(dev);
       
  3498 		nv_start_tx(dev);
       
  3499 		spin_unlock(&np->lock);
       
  3500 		netif_tx_unlock_bh(dev);
       
  3501 		nv_enable_irq(dev);
       
  3502 	}
       
  3503 	return 0;
       
  3504 exit:
       
  3505 	return -ENOMEM;
       
  3506 }
       
  3507 
       
  3508 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
       
  3509 {
       
  3510 	struct fe_priv *np = netdev_priv(dev);
       
  3511 
       
  3512 	pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
       
  3513 	pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
       
  3514 	pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
       
  3515 }
       
  3516 
       
  3517 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
       
  3518 {
       
  3519 	struct fe_priv *np = netdev_priv(dev);
       
  3520 	int adv, bmcr;
       
  3521 
       
  3522 	if ((!np->autoneg && np->duplex == 0) ||
       
  3523 	    (np->autoneg && !pause->autoneg && np->duplex == 0)) {
       
  3524 		printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
       
  3525 		       dev->name);
       
  3526 		return -EINVAL;
       
  3527 	}
       
  3528 	if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
       
  3529 		printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
       
  3530 		return -EINVAL;
       
  3531 	}
       
  3532 
       
  3533 	netif_carrier_off(dev);
       
  3534 	if (netif_running(dev)) {
       
  3535 		nv_disable_irq(dev);
       
  3536 		netif_tx_lock_bh(dev);
       
  3537 		spin_lock(&np->lock);
       
  3538 		/* stop engines */
       
  3539 		nv_stop_rx(dev);
       
  3540 		nv_stop_tx(dev);
       
  3541 		spin_unlock(&np->lock);
       
  3542 		netif_tx_unlock_bh(dev);
       
  3543 	}
       
  3544 
       
  3545 	np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
       
  3546 	if (pause->rx_pause)
       
  3547 		np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
       
  3548 	if (pause->tx_pause)
       
  3549 		np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
       
  3550 
       
  3551 	if (np->autoneg && pause->autoneg) {
       
  3552 		np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
       
  3553 
       
  3554 		adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
       
  3555 		adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
       
  3556 		if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
       
  3557 			adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
       
  3558 		if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
       
  3559 			adv |=  ADVERTISE_PAUSE_ASYM;
       
  3560 		mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
       
  3561 
       
  3562 		if (netif_running(dev))
       
  3563 			printk(KERN_INFO "%s: link down.\n", dev->name);
       
  3564 		bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
       
  3565 		bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
       
  3566 		mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
       
  3567 	} else {
       
  3568 		np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
       
  3569 		if (pause->rx_pause)
       
  3570 			np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
       
  3571 		if (pause->tx_pause)
       
  3572 			np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
       
  3573 
       
  3574 		if (!netif_running(dev))
       
  3575 			nv_update_linkspeed(dev);
       
  3576 		else
       
  3577 			nv_update_pause(dev, np->pause_flags);
       
  3578 	}
       
  3579 
       
  3580 	if (netif_running(dev)) {
       
  3581 		nv_start_rx(dev);
       
  3582 		nv_start_tx(dev);
       
  3583 		nv_enable_irq(dev);
       
  3584 	}
       
  3585 	return 0;
       
  3586 }
       
  3587 
       
  3588 static u32 nv_get_rx_csum(struct net_device *dev)
       
  3589 {
       
  3590 	struct fe_priv *np = netdev_priv(dev);
       
  3591 	return (np->rx_csum) != 0;
       
  3592 }
       
  3593 
       
  3594 static int nv_set_rx_csum(struct net_device *dev, u32 data)
       
  3595 {
       
  3596 	struct fe_priv *np = netdev_priv(dev);
       
  3597 	u8 __iomem *base = get_hwbase(dev);
       
  3598 	int retcode = 0;
       
  3599 
       
  3600 	if (np->driver_data & DEV_HAS_CHECKSUM) {
       
  3601 		if (data) {
       
  3602 			np->rx_csum = 1;
       
  3603 			np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
       
  3604 		} else {
       
  3605 			np->rx_csum = 0;
       
  3606 			/* vlan is dependent on rx checksum offload */
       
  3607 			if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
       
  3608 				np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
       
  3609 		}
       
  3610 		if (netif_running(dev)) {
       
  3611 			spin_lock_irq(&np->lock);
       
  3612 			writel(np->txrxctl_bits, base + NvRegTxRxControl);
       
  3613 			spin_unlock_irq(&np->lock);
       
  3614 		}
       
  3615 	} else {
       
  3616 		return -EINVAL;
       
  3617 	}
       
  3618 
       
  3619 	return retcode;
       
  3620 }
       
  3621 
       
  3622 static int nv_set_tx_csum(struct net_device *dev, u32 data)
       
  3623 {
       
  3624 	struct fe_priv *np = netdev_priv(dev);
       
  3625 
       
  3626 	if (np->driver_data & DEV_HAS_CHECKSUM)
       
  3627 		return ethtool_op_set_tx_hw_csum(dev, data);
       
  3628 	else
       
  3629 		return -EOPNOTSUPP;
       
  3630 }
       
  3631 
       
  3632 static int nv_set_sg(struct net_device *dev, u32 data)
       
  3633 {
       
  3634 	struct fe_priv *np = netdev_priv(dev);
       
  3635 
       
  3636 	if (np->driver_data & DEV_HAS_CHECKSUM)
       
  3637 		return ethtool_op_set_sg(dev, data);
       
  3638 	else
       
  3639 		return -EOPNOTSUPP;
       
  3640 }
       
  3641 
       
  3642 static int nv_get_stats_count(struct net_device *dev)
       
  3643 {
       
  3644 	struct fe_priv *np = netdev_priv(dev);
       
  3645 
       
  3646 	if (np->driver_data & DEV_HAS_STATISTICS)
       
  3647 		return sizeof(struct nv_ethtool_stats)/sizeof(u64);
       
  3648 	else
       
  3649 		return 0;
       
  3650 }
       
  3651 
       
  3652 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
       
  3653 {
       
  3654 	struct fe_priv *np = netdev_priv(dev);
       
  3655 
       
  3656 	/* update stats */
       
  3657 	nv_do_stats_poll((unsigned long)dev);
       
  3658 
       
  3659 	memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
       
  3660 }
       
  3661 
       
  3662 static int nv_self_test_count(struct net_device *dev)
       
  3663 {
       
  3664 	struct fe_priv *np = netdev_priv(dev);
       
  3665 
       
  3666 	if (np->driver_data & DEV_HAS_TEST_EXTENDED)
       
  3667 		return NV_TEST_COUNT_EXTENDED;
       
  3668 	else
       
  3669 		return NV_TEST_COUNT_BASE;
       
  3670 }
       
  3671 
       
  3672 static int nv_link_test(struct net_device *dev)
       
  3673 {
       
  3674 	struct fe_priv *np = netdev_priv(dev);
       
  3675 	int mii_status;
       
  3676 
       
  3677 	mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
       
  3678 	mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
       
  3679 
       
  3680 	/* check phy link status */
       
  3681 	if (!(mii_status & BMSR_LSTATUS))
       
  3682 		return 0;
       
  3683 	else
       
  3684 		return 1;
       
  3685 }
       
  3686 
       
  3687 static int nv_register_test(struct net_device *dev)
       
  3688 {
       
  3689 	u8 __iomem *base = get_hwbase(dev);
       
  3690 	int i = 0;
       
  3691 	u32 orig_read, new_read;
       
  3692 
       
  3693 	do {
       
  3694 		orig_read = readl(base + nv_registers_test[i].reg);
       
  3695 
       
  3696 		/* xor with mask to toggle bits */
       
  3697 		orig_read ^= nv_registers_test[i].mask;
       
  3698 
       
  3699 		writel(orig_read, base + nv_registers_test[i].reg);
       
  3700 
       
  3701 		new_read = readl(base + nv_registers_test[i].reg);
       
  3702 
       
  3703 		if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
       
  3704 			return 0;
       
  3705 
       
  3706 		/* restore original value */
       
  3707 		orig_read ^= nv_registers_test[i].mask;
       
  3708 		writel(orig_read, base + nv_registers_test[i].reg);
       
  3709 
       
  3710 	} while (nv_registers_test[++i].reg != 0);
       
  3711 
       
  3712 	return 1;
       
  3713 }
       
  3714 
       
  3715 static int nv_interrupt_test(struct net_device *dev)
       
  3716 {
       
  3717 	struct fe_priv *np = netdev_priv(dev);
       
  3718 	u8 __iomem *base = get_hwbase(dev);
       
  3719 	int ret = 1;
       
  3720 	int testcnt;
       
  3721 	u32 save_msi_flags, save_poll_interval = 0;
       
  3722 
       
  3723 	if (netif_running(dev)) {
       
  3724 		/* free current irq */
       
  3725 		nv_free_irq(dev);
       
  3726 		save_poll_interval = readl(base+NvRegPollingInterval);
       
  3727 	}
       
  3728 
       
  3729 	/* flag to test interrupt handler */
       
  3730 	np->intr_test = 0;
       
  3731 
       
  3732 	/* setup test irq */
       
  3733 	save_msi_flags = np->msi_flags;
       
  3734 	np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
       
  3735 	np->msi_flags |= 0x001; /* setup 1 vector */
       
  3736 	if (nv_request_irq(dev, 1))
       
  3737 		return 0;
       
  3738 
       
  3739 	/* setup timer interrupt */
       
  3740 	writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
       
  3741 	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
       
  3742 
       
  3743 	nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
       
  3744 
       
  3745 	/* wait for at least one interrupt */
       
  3746 	msleep(100);
       
  3747 
       
  3748 	spin_lock_irq(&np->lock);
       
  3749 
       
  3750 	/* flag should be set within ISR */
       
  3751 	testcnt = np->intr_test;
       
  3752 	if (!testcnt)
       
  3753 		ret = 2;
       
  3754 
       
  3755 	nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
       
  3756 	if (!(np->msi_flags & NV_MSI_X_ENABLED))
       
  3757 		writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
       
  3758 	else
       
  3759 		writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
       
  3760 
       
  3761 	spin_unlock_irq(&np->lock);
       
  3762 
       
  3763 	nv_free_irq(dev);
       
  3764 
       
  3765 	np->msi_flags = save_msi_flags;
       
  3766 
       
  3767 	if (netif_running(dev)) {
       
  3768 		writel(save_poll_interval, base + NvRegPollingInterval);
       
  3769 		writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
       
  3770 		/* restore original irq */
       
  3771 		if (nv_request_irq(dev, 0))
       
  3772 			return 0;
       
  3773 	}
       
  3774 
       
  3775 	return ret;
       
  3776 }
       
  3777 
       
  3778 static int nv_loopback_test(struct net_device *dev)
       
  3779 {
       
  3780 	struct fe_priv *np = netdev_priv(dev);
       
  3781 	u8 __iomem *base = get_hwbase(dev);
       
  3782 	struct sk_buff *tx_skb, *rx_skb;
       
  3783 	dma_addr_t test_dma_addr;
       
  3784 	u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
       
  3785 	u32 flags;
       
  3786 	int len, i, pkt_len;
       
  3787 	u8 *pkt_data;
       
  3788 	u32 filter_flags = 0;
       
  3789 	u32 misc1_flags = 0;
       
  3790 	int ret = 1;
       
  3791 
       
  3792 	if (netif_running(dev)) {
       
  3793 		nv_disable_irq(dev);
       
  3794 		filter_flags = readl(base + NvRegPacketFilterFlags);
       
  3795 		misc1_flags = readl(base + NvRegMisc1);
       
  3796 	} else {
       
  3797 		nv_txrx_reset(dev);
       
  3798 	}
       
  3799 
       
  3800 	/* reinit driver view of the rx queue */
       
  3801 	set_bufsize(dev);
       
  3802 	nv_init_ring(dev);
       
  3803 
       
  3804 	/* setup hardware for loopback */
       
  3805 	writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
       
  3806 	writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
       
  3807 
       
  3808 	/* reinit nic view of the rx queue */
       
  3809 	writel(np->rx_buf_sz, base + NvRegOffloadConfig);
       
  3810 	setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
       
  3811 	writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
       
  3812 		base + NvRegRingSizes);
       
  3813 	pci_push(base);
       
  3814 
       
  3815 	/* restart rx engine */
       
  3816 	nv_start_rx(dev);
       
  3817 	nv_start_tx(dev);
       
  3818 
       
  3819 	/* setup packet for tx */
       
  3820 	pkt_len = ETH_DATA_LEN;
       
  3821 	tx_skb = dev_alloc_skb(pkt_len);
       
  3822 	if (!tx_skb) {
       
  3823 		printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
       
  3824 			 " of %s\n", dev->name);
       
  3825 		ret = 0;
       
  3826 		goto out;
       
  3827 	}
       
  3828 	pkt_data = skb_put(tx_skb, pkt_len);
       
  3829 	for (i = 0; i < pkt_len; i++)
       
  3830 		pkt_data[i] = (u8)(i & 0xff);
       
  3831 	test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
       
  3832 				       tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
       
  3833 
       
  3834 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  3835 		np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
       
  3836 		np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
       
  3837 	} else {
       
  3838 		np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
       
  3839 		np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
       
  3840 		np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
       
  3841 	}
       
  3842 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
       
  3843 	pci_push(get_hwbase(dev));
       
  3844 
       
  3845 	msleep(500);
       
  3846 
       
  3847 	/* check for rx of the packet */
       
  3848 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  3849 		flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
       
  3850 		len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
       
  3851 
       
  3852 	} else {
       
  3853 		flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
       
  3854 		len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
       
  3855 	}
       
  3856 
       
  3857 	if (flags & NV_RX_AVAIL) {
       
  3858 		ret = 0;
       
  3859 	} else if (np->desc_ver == DESC_VER_1) {
       
  3860 		if (flags & NV_RX_ERROR)
       
  3861 			ret = 0;
       
  3862 	} else {
       
  3863 		if (flags & NV_RX2_ERROR) {
       
  3864 			ret = 0;
       
  3865 		}
       
  3866 	}
       
  3867 
       
  3868 	if (ret) {
       
  3869 		if (len != pkt_len) {
       
  3870 			ret = 0;
       
  3871 			dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
       
  3872 				dev->name, len, pkt_len);
       
  3873 		} else {
       
  3874 			rx_skb = np->rx_skbuff[0];
       
  3875 			for (i = 0; i < pkt_len; i++) {
       
  3876 				if (rx_skb->data[i] != (u8)(i & 0xff)) {
       
  3877 					ret = 0;
       
  3878 					dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
       
  3879 						dev->name, i);
       
  3880 					break;
       
  3881 				}
       
  3882 			}
       
  3883 		}
       
  3884 	} else {
       
  3885 		dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
       
  3886 	}
       
  3887 
       
  3888 	pci_unmap_page(np->pci_dev, test_dma_addr,
       
  3889 		       tx_skb->end-tx_skb->data,
       
  3890 		       PCI_DMA_TODEVICE);
       
  3891 	dev_kfree_skb_any(tx_skb);
       
  3892  out:
       
  3893 	/* stop engines */
       
  3894 	nv_stop_rx(dev);
       
  3895 	nv_stop_tx(dev);
       
  3896 	nv_txrx_reset(dev);
       
  3897 	/* drain rx queue */
       
  3898 	nv_drain_rx(dev);
       
  3899 	nv_drain_tx(dev);
       
  3900 
       
  3901 	if (netif_running(dev)) {
       
  3902 		writel(misc1_flags, base + NvRegMisc1);
       
  3903 		writel(filter_flags, base + NvRegPacketFilterFlags);
       
  3904 		nv_enable_irq(dev);
       
  3905 	}
       
  3906 
       
  3907 	return ret;
       
  3908 }
       
  3909 
       
  3910 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
       
  3911 {
       
  3912 	struct fe_priv *np = netdev_priv(dev);
       
  3913 	u8 __iomem *base = get_hwbase(dev);
       
  3914 	int result;
       
  3915 	memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
       
  3916 
       
  3917 	if (!nv_link_test(dev)) {
       
  3918 		test->flags |= ETH_TEST_FL_FAILED;
       
  3919 		buffer[0] = 1;
       
  3920 	}
       
  3921 
       
  3922 	if (test->flags & ETH_TEST_FL_OFFLINE) {
       
  3923 		if (netif_running(dev)) {
       
  3924 			netif_stop_queue(dev);
       
  3925 			netif_poll_disable(dev);
       
  3926 			netif_tx_lock_bh(dev);
       
  3927 			spin_lock_irq(&np->lock);
       
  3928 			nv_disable_hw_interrupts(dev, np->irqmask);
       
  3929 			if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
       
  3930 				writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
       
  3931 			} else {
       
  3932 				writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
       
  3933 			}
       
  3934 			/* stop engines */
       
  3935 			nv_stop_rx(dev);
       
  3936 			nv_stop_tx(dev);
       
  3937 			nv_txrx_reset(dev);
       
  3938 			/* drain rx queue */
       
  3939 			nv_drain_rx(dev);
       
  3940 			nv_drain_tx(dev);
       
  3941 			spin_unlock_irq(&np->lock);
       
  3942 			netif_tx_unlock_bh(dev);
       
  3943 		}
       
  3944 
       
  3945 		if (!nv_register_test(dev)) {
       
  3946 			test->flags |= ETH_TEST_FL_FAILED;
       
  3947 			buffer[1] = 1;
       
  3948 		}
       
  3949 
       
  3950 		result = nv_interrupt_test(dev);
       
  3951 		if (result != 1) {
       
  3952 			test->flags |= ETH_TEST_FL_FAILED;
       
  3953 			buffer[2] = 1;
       
  3954 		}
       
  3955 		if (result == 0) {
       
  3956 			/* bail out */
       
  3957 			return;
       
  3958 		}
       
  3959 
       
  3960 		if (!nv_loopback_test(dev)) {
       
  3961 			test->flags |= ETH_TEST_FL_FAILED;
       
  3962 			buffer[3] = 1;
       
  3963 		}
       
  3964 
       
  3965 		if (netif_running(dev)) {
       
  3966 			/* reinit driver view of the rx queue */
       
  3967 			set_bufsize(dev);
       
  3968 			if (nv_init_ring(dev)) {
       
  3969 				if (!np->in_shutdown)
       
  3970 					mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  3971 			}
       
  3972 			/* reinit nic view of the rx queue */
       
  3973 			writel(np->rx_buf_sz, base + NvRegOffloadConfig);
       
  3974 			setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
       
  3975 			writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
       
  3976 				base + NvRegRingSizes);
       
  3977 			pci_push(base);
       
  3978 			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
       
  3979 			pci_push(base);
       
  3980 			/* restart rx engine */
       
  3981 			nv_start_rx(dev);
       
  3982 			nv_start_tx(dev);
       
  3983 			netif_start_queue(dev);
       
  3984 			netif_poll_enable(dev);
       
  3985 			nv_enable_hw_interrupts(dev, np->irqmask);
       
  3986 		}
       
  3987 	}
       
  3988 }
       
  3989 
       
  3990 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
       
  3991 {
       
  3992 	switch (stringset) {
       
  3993 	case ETH_SS_STATS:
       
  3994 		memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
       
  3995 		break;
       
  3996 	case ETH_SS_TEST:
       
  3997 		memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
       
  3998 		break;
       
  3999 	}
       
  4000 }
       
  4001 
       
  4002 static const struct ethtool_ops ops = {
       
  4003 	.get_drvinfo = nv_get_drvinfo,
       
  4004 	.get_link = ethtool_op_get_link,
       
  4005 	.get_wol = nv_get_wol,
       
  4006 	.set_wol = nv_set_wol,
       
  4007 	.get_settings = nv_get_settings,
       
  4008 	.set_settings = nv_set_settings,
       
  4009 	.get_regs_len = nv_get_regs_len,
       
  4010 	.get_regs = nv_get_regs,
       
  4011 	.nway_reset = nv_nway_reset,
       
  4012 	.get_perm_addr = ethtool_op_get_perm_addr,
       
  4013 	.get_tso = ethtool_op_get_tso,
       
  4014 	.set_tso = nv_set_tso,
       
  4015 	.get_ringparam = nv_get_ringparam,
       
  4016 	.set_ringparam = nv_set_ringparam,
       
  4017 	.get_pauseparam = nv_get_pauseparam,
       
  4018 	.set_pauseparam = nv_set_pauseparam,
       
  4019 	.get_rx_csum = nv_get_rx_csum,
       
  4020 	.set_rx_csum = nv_set_rx_csum,
       
  4021 	.get_tx_csum = ethtool_op_get_tx_csum,
       
  4022 	.set_tx_csum = nv_set_tx_csum,
       
  4023 	.get_sg = ethtool_op_get_sg,
       
  4024 	.set_sg = nv_set_sg,
       
  4025 	.get_strings = nv_get_strings,
       
  4026 	.get_stats_count = nv_get_stats_count,
       
  4027 	.get_ethtool_stats = nv_get_ethtool_stats,
       
  4028 	.self_test_count = nv_self_test_count,
       
  4029 	.self_test = nv_self_test,
       
  4030 };
       
  4031 
       
  4032 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
       
  4033 {
       
  4034 	struct fe_priv *np = get_nvpriv(dev);
       
  4035 
       
  4036 	spin_lock_irq(&np->lock);
       
  4037 
       
  4038 	/* save vlan group */
       
  4039 	np->vlangrp = grp;
       
  4040 
       
  4041 	if (grp) {
       
  4042 		/* enable vlan on MAC */
       
  4043 		np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
       
  4044 	} else {
       
  4045 		/* disable vlan on MAC */
       
  4046 		np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
       
  4047 		np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
       
  4048 	}
       
  4049 
       
  4050 	writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
       
  4051 
       
  4052 	spin_unlock_irq(&np->lock);
       
  4053 };
       
  4054 
       
  4055 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
       
  4056 {
       
  4057 	/* nothing to do */
       
  4058 };
       
  4059 
       
  4060 static int nv_open(struct net_device *dev)
       
  4061 {
       
  4062 	struct fe_priv *np = netdev_priv(dev);
       
  4063 	u8 __iomem *base = get_hwbase(dev);
       
  4064 	int ret = 1;
       
  4065 	int oom, i;
       
  4066 
       
  4067 	dprintk(KERN_DEBUG "nv_open: begin\n");
       
  4068 
       
  4069 	/* erase previous misconfiguration */
       
  4070 	if (np->driver_data & DEV_HAS_POWER_CNTRL)
       
  4071 		nv_mac_reset(dev);
       
  4072 	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
       
  4073 	writel(0, base + NvRegMulticastAddrB);
       
  4074 	writel(0, base + NvRegMulticastMaskA);
       
  4075 	writel(0, base + NvRegMulticastMaskB);
       
  4076 	writel(0, base + NvRegPacketFilterFlags);
       
  4077 
       
  4078 	writel(0, base + NvRegTransmitterControl);
       
  4079 	writel(0, base + NvRegReceiverControl);
       
  4080 
       
  4081 	writel(0, base + NvRegAdapterControl);
       
  4082 
       
  4083 	if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
       
  4084 		writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
       
  4085 
       
  4086 	/* initialize descriptor rings */
       
  4087 	set_bufsize(dev);
       
  4088 	oom = nv_init_ring(dev);
       
  4089 
       
  4090 	writel(0, base + NvRegLinkSpeed);
       
  4091 	writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
       
  4092 	nv_txrx_reset(dev);
       
  4093 	writel(0, base + NvRegUnknownSetupReg6);
       
  4094 
       
  4095 	np->in_shutdown = 0;
       
  4096 
       
  4097 	/* give hw rings */
       
  4098 	setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
       
  4099 	writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
       
  4100 		base + NvRegRingSizes);
       
  4101 
       
  4102 	writel(np->linkspeed, base + NvRegLinkSpeed);
       
  4103 	if (np->desc_ver == DESC_VER_1)
       
  4104 		writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
       
  4105 	else
       
  4106 		writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
       
  4107 	writel(np->txrxctl_bits, base + NvRegTxRxControl);
       
  4108 	writel(np->vlanctl_bits, base + NvRegVlanControl);
       
  4109 	pci_push(base);
       
  4110 	writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
       
  4111 	reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
       
  4112 			NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
       
  4113 			KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
       
  4114 
       
  4115 	writel(0, base + NvRegUnknownSetupReg4);
       
  4116 	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
       
  4117 	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
       
  4118 
       
  4119 	writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
       
  4120 	writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
       
  4121 	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
       
  4122 	writel(np->rx_buf_sz, base + NvRegOffloadConfig);
       
  4123 
       
  4124 	writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
       
  4125 	get_random_bytes(&i, sizeof(i));
       
  4126 	writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
       
  4127 	writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
       
  4128 	writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
       
  4129 	if (poll_interval == -1) {
       
  4130 		if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
       
  4131 			writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
       
  4132 		else
       
  4133 			writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
       
  4134 	}
       
  4135 	else
       
  4136 		writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
       
  4137 	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
       
  4138 	writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
       
  4139 			base + NvRegAdapterControl);
       
  4140 	writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
       
  4141 	writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
       
  4142 	if (np->wolenabled)
       
  4143 		writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
       
  4144 
       
  4145 	i = readl(base + NvRegPowerState);
       
  4146 	if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
       
  4147 		writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
       
  4148 
       
  4149 	pci_push(base);
       
  4150 	udelay(10);
       
  4151 	writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
       
  4152 
       
  4153 	nv_disable_hw_interrupts(dev, np->irqmask);
       
  4154 	pci_push(base);
       
  4155 	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
       
  4156 	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
       
  4157 	pci_push(base);
       
  4158 
       
  4159 	if (nv_request_irq(dev, 0)) {
       
  4160 		goto out_drain;
       
  4161 	}
       
  4162 
       
  4163 	/* ask for interrupts */
       
  4164 	nv_enable_hw_interrupts(dev, np->irqmask);
       
  4165 
       
  4166 	spin_lock_irq(&np->lock);
       
  4167 	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
       
  4168 	writel(0, base + NvRegMulticastAddrB);
       
  4169 	writel(0, base + NvRegMulticastMaskA);
       
  4170 	writel(0, base + NvRegMulticastMaskB);
       
  4171 	writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
       
  4172 	/* One manual link speed update: Interrupts are enabled, future link
       
  4173 	 * speed changes cause interrupts and are handled by nv_link_irq().
       
  4174 	 */
       
  4175 	{
       
  4176 		u32 miistat;
       
  4177 		miistat = readl(base + NvRegMIIStatus);
       
  4178 		writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
       
  4179 		dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
       
  4180 	}
       
  4181 	/* set linkspeed to invalid value, thus force nv_update_linkspeed
       
  4182 	 * to init hw */
       
  4183 	np->linkspeed = 0;
       
  4184 	ret = nv_update_linkspeed(dev);
       
  4185 	nv_start_rx(dev);
       
  4186 	nv_start_tx(dev);
       
  4187 	netif_start_queue(dev);
       
  4188 	netif_poll_enable(dev);
       
  4189 
       
  4190 	if (ret) {
       
  4191 		netif_carrier_on(dev);
       
  4192 	} else {
       
  4193 		printk("%s: no link during initialization.\n", dev->name);
       
  4194 		netif_carrier_off(dev);
       
  4195 	}
       
  4196 	if (oom)
       
  4197 		mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
       
  4198 
       
  4199 	/* start statistics timer */
       
  4200 	if (np->driver_data & DEV_HAS_STATISTICS)
       
  4201 		mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
       
  4202 
       
  4203 	spin_unlock_irq(&np->lock);
       
  4204 
       
  4205 	return 0;
       
  4206 out_drain:
       
  4207 	drain_ring(dev);
       
  4208 	return ret;
       
  4209 }
       
  4210 
       
  4211 static int nv_close(struct net_device *dev)
       
  4212 {
       
  4213 	struct fe_priv *np = netdev_priv(dev);
       
  4214 	u8 __iomem *base;
       
  4215 
       
  4216 	spin_lock_irq(&np->lock);
       
  4217 	np->in_shutdown = 1;
       
  4218 	spin_unlock_irq(&np->lock);
       
  4219 	netif_poll_disable(dev);
       
  4220 	synchronize_irq(dev->irq);
       
  4221 
       
  4222 	del_timer_sync(&np->oom_kick);
       
  4223 	del_timer_sync(&np->nic_poll);
       
  4224 	del_timer_sync(&np->stats_poll);
       
  4225 
       
  4226 	netif_stop_queue(dev);
       
  4227 	spin_lock_irq(&np->lock);
       
  4228 	nv_stop_tx(dev);
       
  4229 	nv_stop_rx(dev);
       
  4230 	nv_txrx_reset(dev);
       
  4231 
       
  4232 	/* disable interrupts on the nic or we will lock up */
       
  4233 	base = get_hwbase(dev);
       
  4234 	nv_disable_hw_interrupts(dev, np->irqmask);
       
  4235 	pci_push(base);
       
  4236 	dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
       
  4237 
       
  4238 	spin_unlock_irq(&np->lock);
       
  4239 
       
  4240 	nv_free_irq(dev);
       
  4241 
       
  4242 	drain_ring(dev);
       
  4243 
       
  4244 	if (np->wolenabled)
       
  4245 		nv_start_rx(dev);
       
  4246 
       
  4247 	/* FIXME: power down nic */
       
  4248 
       
  4249 	return 0;
       
  4250 }
       
  4251 
       
  4252 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
       
  4253 {
       
  4254 	struct net_device *dev;
       
  4255 	struct fe_priv *np;
       
  4256 	unsigned long addr;
       
  4257 	u8 __iomem *base;
       
  4258 	int err, i;
       
  4259 	u32 powerstate, txreg;
       
  4260 
       
  4261     board_idx++;
       
  4262 
       
  4263 	dev = alloc_etherdev(sizeof(struct fe_priv));
       
  4264 	err = -ENOMEM;
       
  4265 	if (!dev)
       
  4266 		goto out;
       
  4267 
       
  4268 	np = netdev_priv(dev);
       
  4269 	np->pci_dev = pci_dev;
       
  4270 	spin_lock_init(&np->lock);
       
  4271 	SET_MODULE_OWNER(dev);
       
  4272 	SET_NETDEV_DEV(dev, &pci_dev->dev);
       
  4273 
       
  4274 	init_timer(&np->oom_kick);
       
  4275 	np->oom_kick.data = (unsigned long) dev;
       
  4276 	np->oom_kick.function = &nv_do_rx_refill;	/* timer handler */
       
  4277 	init_timer(&np->nic_poll);
       
  4278 	np->nic_poll.data = (unsigned long) dev;
       
  4279 	np->nic_poll.function = &nv_do_nic_poll;	/* timer handler */
       
  4280 	init_timer(&np->stats_poll);
       
  4281 	np->stats_poll.data = (unsigned long) dev;
       
  4282 	np->stats_poll.function = &nv_do_stats_poll;	/* timer handler */
       
  4283 
       
  4284 	err = pci_enable_device(pci_dev);
       
  4285 	if (err) {
       
  4286 		printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
       
  4287 				err, pci_name(pci_dev));
       
  4288 		goto out_free;
       
  4289 	}
       
  4290 
       
  4291 	pci_set_master(pci_dev);
       
  4292 
       
  4293 	err = pci_request_regions(pci_dev, DRV_NAME);
       
  4294 	if (err < 0)
       
  4295 		goto out_disable;
       
  4296 
       
  4297 	if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
       
  4298 		np->register_size = NV_PCI_REGSZ_VER2;
       
  4299 	else
       
  4300 		np->register_size = NV_PCI_REGSZ_VER1;
       
  4301 
       
  4302 	err = -EINVAL;
       
  4303 	addr = 0;
       
  4304 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
       
  4305 		dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
       
  4306 				pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
       
  4307 				pci_resource_len(pci_dev, i),
       
  4308 				pci_resource_flags(pci_dev, i));
       
  4309 		if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
       
  4310 				pci_resource_len(pci_dev, i) >= np->register_size) {
       
  4311 			addr = pci_resource_start(pci_dev, i);
       
  4312 			break;
       
  4313 		}
       
  4314 	}
       
  4315 	if (i == DEVICE_COUNT_RESOURCE) {
       
  4316 		printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
       
  4317 					pci_name(pci_dev));
       
  4318 		goto out_relreg;
       
  4319 	}
       
  4320 
       
  4321 	/* copy of driver data */
       
  4322 	np->driver_data = id->driver_data;
       
  4323 
       
  4324 	/* handle different descriptor versions */
       
  4325 	if (id->driver_data & DEV_HAS_HIGH_DMA) {
       
  4326 		/* packet format 3: supports 40-bit addressing */
       
  4327 		np->desc_ver = DESC_VER_3;
       
  4328 		np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
       
  4329 		if (dma_64bit) {
       
  4330 			if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
       
  4331 				printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
       
  4332 				       pci_name(pci_dev));
       
  4333 			} else {
       
  4334 				dev->features |= NETIF_F_HIGHDMA;
       
  4335 				printk(KERN_INFO "forcedeth: using HIGHDMA\n");
       
  4336 			}
       
  4337 			if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
       
  4338 				printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
       
  4339 				       pci_name(pci_dev));
       
  4340 			}
       
  4341 		}
       
  4342 	} else if (id->driver_data & DEV_HAS_LARGEDESC) {
       
  4343 		/* packet format 2: supports jumbo frames */
       
  4344 		np->desc_ver = DESC_VER_2;
       
  4345 		np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
       
  4346 	} else {
       
  4347 		/* original packet format */
       
  4348 		np->desc_ver = DESC_VER_1;
       
  4349 		np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
       
  4350 	}
       
  4351 
       
  4352 	np->pkt_limit = NV_PKTLIMIT_1;
       
  4353 	if (id->driver_data & DEV_HAS_LARGEDESC)
       
  4354 		np->pkt_limit = NV_PKTLIMIT_2;
       
  4355 
       
  4356 	if (id->driver_data & DEV_HAS_CHECKSUM) {
       
  4357 		np->rx_csum = 1;
       
  4358 		np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
       
  4359 		dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
       
  4360 #ifdef NETIF_F_TSO
       
  4361 		dev->features |= NETIF_F_TSO;
       
  4362 #endif
       
  4363  	}
       
  4364 
       
  4365 	np->vlanctl_bits = 0;
       
  4366 	if (id->driver_data & DEV_HAS_VLAN) {
       
  4367 		np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
       
  4368 		dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
       
  4369 		dev->vlan_rx_register = nv_vlan_rx_register;
       
  4370 		dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
       
  4371 	}
       
  4372 
       
  4373 	np->msi_flags = 0;
       
  4374 	if ((id->driver_data & DEV_HAS_MSI) && msi) {
       
  4375 		np->msi_flags |= NV_MSI_CAPABLE;
       
  4376 	}
       
  4377 	if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
       
  4378 		np->msi_flags |= NV_MSI_X_CAPABLE;
       
  4379 	}
       
  4380 
       
  4381 	np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
       
  4382 	if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
       
  4383 		np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
       
  4384 	}
       
  4385 
       
  4386 
       
  4387 	err = -ENOMEM;
       
  4388 	np->base = ioremap(addr, np->register_size);
       
  4389 	if (!np->base)
       
  4390 		goto out_relreg;
       
  4391 	dev->base_addr = (unsigned long)np->base;
       
  4392 
       
  4393 	dev->irq = pci_dev->irq;
       
  4394 
       
  4395 	np->rx_ring_size = RX_RING_DEFAULT;
       
  4396 	np->tx_ring_size = TX_RING_DEFAULT;
       
  4397 	np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
       
  4398 	np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
       
  4399 
       
  4400 	if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
       
  4401 		np->rx_ring.orig = pci_alloc_consistent(pci_dev,
       
  4402 					sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
       
  4403 					&np->ring_addr);
       
  4404 		if (!np->rx_ring.orig)
       
  4405 			goto out_unmap;
       
  4406 		np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
       
  4407 	} else {
       
  4408 		np->rx_ring.ex = pci_alloc_consistent(pci_dev,
       
  4409 					sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
       
  4410 					&np->ring_addr);
       
  4411 		if (!np->rx_ring.ex)
       
  4412 			goto out_unmap;
       
  4413 		np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
       
  4414 	}
       
  4415 	np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
       
  4416 	np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
       
  4417 	np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
       
  4418 	np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
       
  4419 	np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
       
  4420 	if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
       
  4421 		goto out_freering;
       
  4422 	memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
       
  4423 	memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
       
  4424 	memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
       
  4425 	memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
       
  4426 	memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
       
  4427 
       
  4428 	dev->open = nv_open;
       
  4429 	dev->stop = nv_close;
       
  4430 	dev->hard_start_xmit = nv_start_xmit;
       
  4431 	dev->get_stats = nv_get_stats;
       
  4432 	dev->change_mtu = nv_change_mtu;
       
  4433 	dev->set_mac_address = nv_set_mac_address;
       
  4434 	dev->set_multicast_list = nv_set_multicast;
       
  4435 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  4436 	dev->poll_controller = nv_poll_controller;
       
  4437 #endif
       
  4438 	dev->weight = 64;
       
  4439 #ifdef CONFIG_FORCEDETH_NAPI
       
  4440 	dev->poll = nv_napi_poll;
       
  4441 #endif
       
  4442 	SET_ETHTOOL_OPS(dev, &ops);
       
  4443 	dev->tx_timeout = nv_tx_timeout;
       
  4444 	dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
       
  4445 
       
  4446 	pci_set_drvdata(pci_dev, dev);
       
  4447 
       
  4448 	/* read the mac address */
       
  4449 	base = get_hwbase(dev);
       
  4450 	np->orig_mac[0] = readl(base + NvRegMacAddrA);
       
  4451 	np->orig_mac[1] = readl(base + NvRegMacAddrB);
       
  4452 
       
  4453 	/* check the workaround bit for correct mac address order */
       
  4454 	txreg = readl(base + NvRegTransmitPoll);
       
  4455 	if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
       
  4456 		/* mac address is already in correct order */
       
  4457 		dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
       
  4458 		dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
       
  4459 		dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
       
  4460 		dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
       
  4461 		dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
       
  4462 		dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
       
  4463 	} else {
       
  4464 		/* need to reverse mac address to correct order */
       
  4465 		dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
       
  4466 		dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
       
  4467 		dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
       
  4468 		dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
       
  4469 		dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
       
  4470 		dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
       
  4471 		/* set permanent address to be correct aswell */
       
  4472 		np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
       
  4473 			(dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
       
  4474 		np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
       
  4475 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
       
  4476 	}
       
  4477 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
       
  4478 
       
  4479 	if (!is_valid_ether_addr(dev->perm_addr)) {
       
  4480 		/*
       
  4481 		 * Bad mac address. At least one bios sets the mac address
       
  4482 		 * to 01:23:45:67:89:ab
       
  4483 		 */
       
  4484 		printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
       
  4485 			pci_name(pci_dev),
       
  4486 			dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
       
  4487 			dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
       
  4488 		printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
       
  4489 		dev->dev_addr[0] = 0x00;
       
  4490 		dev->dev_addr[1] = 0x00;
       
  4491 		dev->dev_addr[2] = 0x6c;
       
  4492 		get_random_bytes(&dev->dev_addr[3], 3);
       
  4493 	}
       
  4494 
       
  4495 	dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
       
  4496 			dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
       
  4497 			dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
       
  4498 
       
  4499 	/* set mac address */
       
  4500 	nv_copy_mac_to_hw(dev);
       
  4501 
       
  4502 	/* disable WOL */
       
  4503 	writel(0, base + NvRegWakeUpFlags);
       
  4504 	np->wolenabled = 0;
       
  4505 
       
  4506 	if (id->driver_data & DEV_HAS_POWER_CNTRL) {
       
  4507 		u8 revision_id;
       
  4508 		pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
       
  4509 
       
  4510 		/* take phy and nic out of low power mode */
       
  4511 		powerstate = readl(base + NvRegPowerState2);
       
  4512 		powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
       
  4513 		if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
       
  4514 		     id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
       
  4515 		    revision_id >= 0xA3)
       
  4516 			powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
       
  4517 		writel(powerstate, base + NvRegPowerState2);
       
  4518 	}
       
  4519 
       
  4520 	if (np->desc_ver == DESC_VER_1) {
       
  4521 		np->tx_flags = NV_TX_VALID;
       
  4522 	} else {
       
  4523 		np->tx_flags = NV_TX2_VALID;
       
  4524 	}
       
  4525 	if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
       
  4526 		np->irqmask = NVREG_IRQMASK_THROUGHPUT;
       
  4527 		if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
       
  4528 			np->msi_flags |= 0x0003;
       
  4529 	} else {
       
  4530 		np->irqmask = NVREG_IRQMASK_CPU;
       
  4531 		if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
       
  4532 			np->msi_flags |= 0x0001;
       
  4533 	}
       
  4534 
       
  4535 	if (id->driver_data & DEV_NEED_TIMERIRQ)
       
  4536 		np->irqmask |= NVREG_IRQ_TIMER;
       
  4537 	if (id->driver_data & DEV_NEED_LINKTIMER) {
       
  4538 		dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
       
  4539 		np->need_linktimer = 1;
       
  4540 		np->link_timeout = jiffies + LINK_TIMEOUT;
       
  4541 	} else {
       
  4542 		dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
       
  4543 		np->need_linktimer = 0;
       
  4544 	}
       
  4545 
       
  4546 	/* find a suitable phy */
       
  4547 	for (i = 1; i <= 32; i++) {
       
  4548 		int id1, id2;
       
  4549 		int phyaddr = i & 0x1F;
       
  4550 
       
  4551 		spin_lock_irq(&np->lock);
       
  4552 		id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
       
  4553 		spin_unlock_irq(&np->lock);
       
  4554 		if (id1 < 0 || id1 == 0xffff)
       
  4555 			continue;
       
  4556 		spin_lock_irq(&np->lock);
       
  4557 		id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
       
  4558 		spin_unlock_irq(&np->lock);
       
  4559 		if (id2 < 0 || id2 == 0xffff)
       
  4560 			continue;
       
  4561 
       
  4562 		np->phy_model = id2 & PHYID2_MODEL_MASK;
       
  4563 		id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
       
  4564 		id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
       
  4565 		dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
       
  4566 			pci_name(pci_dev), id1, id2, phyaddr);
       
  4567 		np->phyaddr = phyaddr;
       
  4568 		np->phy_oui = id1 | id2;
       
  4569 		break;
       
  4570 	}
       
  4571 	if (i == 33) {
       
  4572 		printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
       
  4573 		       pci_name(pci_dev));
       
  4574 		goto out_error;
       
  4575 	}
       
  4576 
       
  4577 	/* reset it */
       
  4578 	phy_init(dev);
       
  4579 
       
  4580 	/* set default link speed settings */
       
  4581 	np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
       
  4582 	np->duplex = 0;
       
  4583 	np->autoneg = 1;
       
  4584 
       
  4585 	// offer device to EtherCAT master module
       
  4586 	if (ecdev_offer(dev, &np->ecdev, "forcedeth", board_idx,
       
  4587 				ec_poll, THIS_MODULE)) {
       
  4588 		printk(KERN_ERR "forcedeth: Failed to offer device.\n");
       
  4589 		goto out_error;
       
  4590 	}
       
  4591 
       
  4592 	if (!np->ecdev) {
       
  4593 		err = register_netdev(dev);
       
  4594 		if (err) {
       
  4595 			printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
       
  4596 			goto out_freering;
       
  4597 		}
       
  4598 	}
       
  4599 	printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
       
  4600 			dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
       
  4601 			pci_name(pci_dev));
       
  4602 
       
  4603 	return 0;
       
  4604 
       
  4605 out_error:
       
  4606 	pci_set_drvdata(pci_dev, NULL);
       
  4607 out_freering:
       
  4608 	free_rings(dev);
       
  4609 out_unmap:
       
  4610 	iounmap(get_hwbase(dev));
       
  4611 out_relreg:
       
  4612 	pci_release_regions(pci_dev);
       
  4613 out_disable:
       
  4614 	pci_disable_device(pci_dev);
       
  4615 out_free:
       
  4616 	free_netdev(dev);
       
  4617 out:
       
  4618 	return err;
       
  4619 }
       
  4620 
       
  4621 static void __devexit nv_remove(struct pci_dev *pci_dev)
       
  4622 {
       
  4623 	struct net_device *dev = pci_get_drvdata(pci_dev);
       
  4624 	struct fe_priv *np = netdev_priv(dev);
       
  4625 	u8 __iomem *base = get_hwbase(dev);
       
  4626 
       
  4627 	if (np->ecdev) {
       
  4628 		ecdev_close(np->ecdev);
       
  4629 		ecdev_withdraw(np->ecdev);
       
  4630 	}
       
  4631 	else {
       
  4632 		unregister_netdev(dev);
       
  4633 	}
       
  4634 
       
  4635 	/* special op: write back the misordered MAC address - otherwise
       
  4636 	 * the next nv_probe would see a wrong address.
       
  4637 	 */
       
  4638 	writel(np->orig_mac[0], base + NvRegMacAddrA);
       
  4639 	writel(np->orig_mac[1], base + NvRegMacAddrB);
       
  4640 
       
  4641 	/* free all structures */
       
  4642 	free_rings(dev);
       
  4643 	iounmap(get_hwbase(dev));
       
  4644 	pci_release_regions(pci_dev);
       
  4645 	pci_disable_device(pci_dev);
       
  4646 	free_netdev(dev);
       
  4647 	pci_set_drvdata(pci_dev, NULL);
       
  4648 }
       
  4649 
       
  4650 static struct pci_device_id pci_tbl[] = {
       
  4651 	{	/* nForce Ethernet Controller */
       
  4652 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
       
  4653 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
       
  4654 	},
       
  4655 	{	/* nForce2 Ethernet Controller */
       
  4656 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
       
  4657 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
       
  4658 	},
       
  4659 	{	/* nForce3 Ethernet Controller */
       
  4660 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
       
  4661 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
       
  4662 	},
       
  4663 	{	/* nForce3 Ethernet Controller */
       
  4664 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
       
  4665 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
       
  4666 	},
       
  4667 	{	/* nForce3 Ethernet Controller */
       
  4668 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
       
  4669 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
       
  4670 	},
       
  4671 	{	/* nForce3 Ethernet Controller */
       
  4672 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
       
  4673 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
       
  4674 	},
       
  4675 	{	/* nForce3 Ethernet Controller */
       
  4676 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
       
  4677 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
       
  4678 	},
       
  4679 	{	/* CK804 Ethernet Controller */
       
  4680 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
       
  4681 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
       
  4682 	},
       
  4683 	{	/* CK804 Ethernet Controller */
       
  4684 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
       
  4685 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
       
  4686 	},
       
  4687 	{	/* MCP04 Ethernet Controller */
       
  4688 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
       
  4689 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
       
  4690 	},
       
  4691 	{	/* MCP04 Ethernet Controller */
       
  4692 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
       
  4693 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
       
  4694 	},
       
  4695 	{	/* MCP51 Ethernet Controller */
       
  4696 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
       
  4697 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
       
  4698 	},
       
  4699 	{	/* MCP51 Ethernet Controller */
       
  4700 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
       
  4701 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
       
  4702 	},
       
  4703 	{	/* MCP55 Ethernet Controller */
       
  4704 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
       
  4705 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4706 	},
       
  4707 	{	/* MCP55 Ethernet Controller */
       
  4708 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
       
  4709 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4710 	},
       
  4711 	{	/* MCP61 Ethernet Controller */
       
  4712 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
       
  4713 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4714 	},
       
  4715 	{	/* MCP61 Ethernet Controller */
       
  4716 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
       
  4717 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4718 	},
       
  4719 	{	/* MCP61 Ethernet Controller */
       
  4720 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
       
  4721 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4722 	},
       
  4723 	{	/* MCP61 Ethernet Controller */
       
  4724 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
       
  4725 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4726 	},
       
  4727 	{	/* MCP65 Ethernet Controller */
       
  4728 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
       
  4729 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4730 	},
       
  4731 	{	/* MCP65 Ethernet Controller */
       
  4732 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
       
  4733 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4734 	},
       
  4735 	{	/* MCP65 Ethernet Controller */
       
  4736 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
       
  4737 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4738 	},
       
  4739 	{	/* MCP65 Ethernet Controller */
       
  4740 		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
       
  4741 		.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
       
  4742 	},
       
  4743 	{0,},
       
  4744 };
       
  4745 
       
  4746 static struct pci_driver driver = {
       
  4747 	.name = "forcedeth",
       
  4748 	.id_table = pci_tbl,
       
  4749 	.probe = nv_probe,
       
  4750 	.remove = __devexit_p(nv_remove),
       
  4751 };
       
  4752 
       
  4753 
       
  4754 static int __init init_nic(void)
       
  4755 {
       
  4756 	printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
       
  4757 	return pci_register_driver(&driver);
       
  4758 }
       
  4759 
       
  4760 static void __exit exit_nic(void)
       
  4761 {
       
  4762 	pci_unregister_driver(&driver);
       
  4763 }
       
  4764 
       
  4765 module_param(max_interrupt_work, int, 0);
       
  4766 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
       
  4767 module_param(optimization_mode, int, 0);
       
  4768 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
       
  4769 module_param(poll_interval, int, 0);
       
  4770 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
       
  4771 module_param(msi, int, 0);
       
  4772 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
       
  4773 module_param(msix, int, 0);
       
  4774 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
       
  4775 module_param(dma_64bit, int, 0);
       
  4776 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
       
  4777 
       
  4778 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
       
  4779 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
       
  4780 MODULE_LICENSE("GPL");
       
  4781 
       
  4782 //MODULE_DEVICE_TABLE(pci, pci_tbl); // prevent auto-loading
       
  4783 
       
  4784 module_init(init_nic);
       
  4785 module_exit(exit_nic);