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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2012 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #include "e1000-3.8-ethercat.h" |
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30 |
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31 /** |
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32 * e1000e_get_bus_info_pcie - Get PCIe bus information |
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33 * @hw: pointer to the HW structure |
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34 * |
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35 * Determines and stores the system bus information for a particular |
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36 * network interface. The following bus information is determined and stored: |
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37 * bus speed, bus width, type (PCIe), and PCIe function. |
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38 **/ |
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39 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) |
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40 { |
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41 struct e1000_mac_info *mac = &hw->mac; |
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42 struct e1000_bus_info *bus = &hw->bus; |
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43 struct e1000_adapter *adapter = hw->adapter; |
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44 u16 pcie_link_status, cap_offset; |
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45 |
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46 cap_offset = adapter->pdev->pcie_cap; |
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47 if (!cap_offset) { |
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48 bus->width = e1000_bus_width_unknown; |
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49 } else { |
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50 pci_read_config_word(adapter->pdev, |
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51 cap_offset + PCIE_LINK_STATUS, |
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52 &pcie_link_status); |
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53 bus->width = (enum e1000_bus_width)((pcie_link_status & |
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54 PCIE_LINK_WIDTH_MASK) >> |
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55 PCIE_LINK_WIDTH_SHIFT); |
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56 } |
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57 |
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58 mac->ops.set_lan_id(hw); |
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59 |
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60 return 0; |
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61 } |
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62 |
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63 /** |
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64 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices |
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65 * |
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66 * @hw: pointer to the HW structure |
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67 * |
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68 * Determines the LAN function id by reading memory-mapped registers |
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69 * and swaps the port value if requested. |
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70 **/ |
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71 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) |
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72 { |
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73 struct e1000_bus_info *bus = &hw->bus; |
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74 u32 reg; |
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75 |
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76 /* The status register reports the correct function number |
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77 * for the device regardless of function swap state. |
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78 */ |
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79 reg = er32(STATUS); |
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80 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; |
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81 } |
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82 |
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83 /** |
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84 * e1000_set_lan_id_single_port - Set LAN id for a single port device |
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85 * @hw: pointer to the HW structure |
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86 * |
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87 * Sets the LAN function id to zero for a single port device. |
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88 **/ |
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89 void e1000_set_lan_id_single_port(struct e1000_hw *hw) |
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90 { |
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91 struct e1000_bus_info *bus = &hw->bus; |
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92 |
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93 bus->func = 0; |
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94 } |
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95 |
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96 /** |
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97 * e1000_clear_vfta_generic - Clear VLAN filter table |
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98 * @hw: pointer to the HW structure |
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99 * |
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100 * Clears the register array which contains the VLAN filter table by |
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101 * setting all the values to 0. |
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102 **/ |
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103 void e1000_clear_vfta_generic(struct e1000_hw *hw) |
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104 { |
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105 u32 offset; |
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106 |
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107 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
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108 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); |
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109 e1e_flush(); |
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110 } |
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111 } |
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112 |
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113 /** |
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114 * e1000_write_vfta_generic - Write value to VLAN filter table |
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115 * @hw: pointer to the HW structure |
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116 * @offset: register offset in VLAN filter table |
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117 * @value: register value written to VLAN filter table |
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118 * |
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119 * Writes value at the given offset in the register array which stores |
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120 * the VLAN filter table. |
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121 **/ |
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122 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) |
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123 { |
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124 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); |
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125 e1e_flush(); |
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126 } |
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127 |
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128 /** |
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129 * e1000e_init_rx_addrs - Initialize receive address's |
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130 * @hw: pointer to the HW structure |
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131 * @rar_count: receive address registers |
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132 * |
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133 * Setup the receive address registers by setting the base receive address |
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134 * register to the devices MAC address and clearing all the other receive |
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135 * address registers to 0. |
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136 **/ |
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137 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
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138 { |
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139 u32 i; |
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140 u8 mac_addr[ETH_ALEN] = { 0 }; |
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141 |
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142 /* Setup the receive address */ |
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143 e_dbg("Programming MAC Address into RAR[0]\n"); |
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144 |
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145 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
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146 |
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147 /* Zero out the other (rar_entry_count - 1) receive addresses */ |
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148 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); |
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149 for (i = 1; i < rar_count; i++) |
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150 hw->mac.ops.rar_set(hw, mac_addr, i); |
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151 } |
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152 |
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153 /** |
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154 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr |
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155 * @hw: pointer to the HW structure |
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156 * |
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157 * Checks the nvm for an alternate MAC address. An alternate MAC address |
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158 * can be setup by pre-boot software and must be treated like a permanent |
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159 * address and must override the actual permanent MAC address. If an |
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160 * alternate MAC address is found it is programmed into RAR0, replacing |
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161 * the permanent address that was installed into RAR0 by the Si on reset. |
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162 * This function will return SUCCESS unless it encounters an error while |
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163 * reading the EEPROM. |
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164 **/ |
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165 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) |
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166 { |
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167 u32 i; |
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168 s32 ret_val = 0; |
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169 u16 offset, nvm_alt_mac_addr_offset, nvm_data; |
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170 u8 alt_mac_addr[ETH_ALEN]; |
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171 |
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172 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); |
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173 if (ret_val) |
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174 return ret_val; |
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175 |
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176 /* not supported on 82573 */ |
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177 if (hw->mac.type == e1000_82573) |
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178 return 0; |
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179 |
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180 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
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181 &nvm_alt_mac_addr_offset); |
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182 if (ret_val) { |
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183 e_dbg("NVM Read Error\n"); |
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184 return ret_val; |
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185 } |
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186 |
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187 if ((nvm_alt_mac_addr_offset == 0xFFFF) || |
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188 (nvm_alt_mac_addr_offset == 0x0000)) |
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189 /* There is no Alternate MAC Address */ |
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190 return 0; |
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191 |
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192 if (hw->bus.func == E1000_FUNC_1) |
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193 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; |
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194 for (i = 0; i < ETH_ALEN; i += 2) { |
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195 offset = nvm_alt_mac_addr_offset + (i >> 1); |
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196 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); |
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197 if (ret_val) { |
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198 e_dbg("NVM Read Error\n"); |
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199 return ret_val; |
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200 } |
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201 |
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202 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); |
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203 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); |
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204 } |
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205 |
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206 /* if multicast bit is set, the alternate address will not be used */ |
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207 if (is_multicast_ether_addr(alt_mac_addr)) { |
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208 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); |
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209 return 0; |
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210 } |
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211 |
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212 /* We have a valid alternate MAC address, and we want to treat it the |
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213 * same as the normal permanent MAC address stored by the HW into the |
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214 * RAR. Do this by mapping this address into RAR0. |
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215 */ |
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216 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); |
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217 |
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218 return 0; |
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219 } |
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220 |
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221 /** |
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222 * e1000e_rar_set_generic - Set receive address register |
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223 * @hw: pointer to the HW structure |
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224 * @addr: pointer to the receive address |
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225 * @index: receive address array register |
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226 * |
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227 * Sets the receive address array register at index to the address passed |
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228 * in by addr. |
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229 **/ |
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230 void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) |
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231 { |
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232 u32 rar_low, rar_high; |
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233 |
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234 /* HW expects these in little endian so we reverse the byte order |
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235 * from network order (big endian) to little endian |
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236 */ |
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237 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | |
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238 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
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239 |
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240 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
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241 |
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242 /* If MAC address zero, no need to set the AV bit */ |
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243 if (rar_low || rar_high) |
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244 rar_high |= E1000_RAH_AV; |
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245 |
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246 /* Some bridges will combine consecutive 32-bit writes into |
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247 * a single burst write, which will malfunction on some parts. |
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248 * The flushes avoid this. |
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249 */ |
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250 ew32(RAL(index), rar_low); |
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251 e1e_flush(); |
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252 ew32(RAH(index), rar_high); |
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253 e1e_flush(); |
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254 } |
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255 |
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256 /** |
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257 * e1000_hash_mc_addr - Generate a multicast hash value |
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258 * @hw: pointer to the HW structure |
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259 * @mc_addr: pointer to a multicast address |
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260 * |
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261 * Generates a multicast address hash value which is used to determine |
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262 * the multicast filter table array address and new table value. |
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263 **/ |
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264 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
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265 { |
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266 u32 hash_value, hash_mask; |
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267 u8 bit_shift = 0; |
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268 |
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269 /* Register count multiplied by bits per register */ |
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270 hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
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271 |
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272 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts |
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273 * where 0xFF would still fall within the hash mask. |
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274 */ |
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275 while (hash_mask >> bit_shift != 0xFF) |
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276 bit_shift++; |
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277 |
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278 /* The portion of the address that is used for the hash table |
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279 * is determined by the mc_filter_type setting. |
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280 * The algorithm is such that there is a total of 8 bits of shifting. |
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281 * The bit_shift for a mc_filter_type of 0 represents the number of |
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282 * left-shifts where the MSB of mc_addr[5] would still fall within |
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283 * the hash_mask. Case 0 does this exactly. Since there are a total |
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284 * of 8 bits of shifting, then mc_addr[4] will shift right the |
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285 * remaining number of bits. Thus 8 - bit_shift. The rest of the |
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286 * cases are a variation of this algorithm...essentially raising the |
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287 * number of bits to shift mc_addr[5] left, while still keeping the |
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288 * 8-bit shifting total. |
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289 * |
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290 * For example, given the following Destination MAC Address and an |
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291 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
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292 * we can see that the bit_shift for case 0 is 4. These are the hash |
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293 * values resulting from each mc_filter_type... |
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294 * [0] [1] [2] [3] [4] [5] |
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295 * 01 AA 00 12 34 56 |
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296 * LSB MSB |
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297 * |
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298 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
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299 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
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300 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
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301 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
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302 */ |
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303 switch (hw->mac.mc_filter_type) { |
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304 default: |
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305 case 0: |
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306 break; |
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307 case 1: |
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308 bit_shift += 1; |
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309 break; |
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310 case 2: |
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311 bit_shift += 2; |
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312 break; |
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313 case 3: |
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314 bit_shift += 4; |
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315 break; |
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316 } |
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317 |
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318 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
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319 (((u16)mc_addr[5]) << bit_shift))); |
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320 |
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321 return hash_value; |
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322 } |
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323 |
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324 /** |
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325 * e1000e_update_mc_addr_list_generic - Update Multicast addresses |
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326 * @hw: pointer to the HW structure |
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327 * @mc_addr_list: array of multicast addresses to program |
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328 * @mc_addr_count: number of multicast addresses to program |
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329 * |
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330 * Updates entire Multicast Table Array. |
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331 * The caller must have a packed mc_addr_list of multicast addresses. |
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332 **/ |
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333 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, |
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334 u8 *mc_addr_list, u32 mc_addr_count) |
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335 { |
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336 u32 hash_value, hash_bit, hash_reg; |
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337 int i; |
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338 |
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339 /* clear mta_shadow */ |
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340 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); |
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341 |
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342 /* update mta_shadow from mc_addr_list */ |
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343 for (i = 0; (u32)i < mc_addr_count; i++) { |
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344 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); |
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345 |
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346 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
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347 hash_bit = hash_value & 0x1F; |
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348 |
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349 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); |
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350 mc_addr_list += (ETH_ALEN); |
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351 } |
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352 |
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353 /* replace the entire MTA table */ |
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354 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) |
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355 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); |
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356 e1e_flush(); |
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357 } |
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358 |
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359 /** |
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360 * e1000e_clear_hw_cntrs_base - Clear base hardware counters |
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361 * @hw: pointer to the HW structure |
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362 * |
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363 * Clears the base hardware counters by reading the counter registers. |
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364 **/ |
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365 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) |
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366 { |
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367 er32(CRCERRS); |
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368 er32(SYMERRS); |
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369 er32(MPC); |
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370 er32(SCC); |
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371 er32(ECOL); |
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372 er32(MCC); |
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373 er32(LATECOL); |
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374 er32(COLC); |
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375 er32(DC); |
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376 er32(SEC); |
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377 er32(RLEC); |
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378 er32(XONRXC); |
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379 er32(XONTXC); |
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380 er32(XOFFRXC); |
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381 er32(XOFFTXC); |
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382 er32(FCRUC); |
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383 er32(GPRC); |
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384 er32(BPRC); |
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385 er32(MPRC); |
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386 er32(GPTC); |
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387 er32(GORCL); |
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388 er32(GORCH); |
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389 er32(GOTCL); |
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390 er32(GOTCH); |
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391 er32(RNBC); |
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392 er32(RUC); |
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393 er32(RFC); |
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394 er32(ROC); |
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395 er32(RJC); |
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396 er32(TORL); |
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397 er32(TORH); |
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398 er32(TOTL); |
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399 er32(TOTH); |
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400 er32(TPR); |
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401 er32(TPT); |
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402 er32(MPTC); |
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403 er32(BPTC); |
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404 } |
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405 |
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406 /** |
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407 * e1000e_check_for_copper_link - Check for link (Copper) |
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408 * @hw: pointer to the HW structure |
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409 * |
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410 * Checks to see of the link status of the hardware has changed. If a |
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411 * change in link status has been detected, then we read the PHY registers |
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412 * to get the current speed/duplex if link exists. |
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413 **/ |
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414 s32 e1000e_check_for_copper_link(struct e1000_hw *hw) |
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415 { |
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416 struct e1000_mac_info *mac = &hw->mac; |
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417 s32 ret_val; |
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418 bool link; |
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419 |
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420 /* We only want to go out to the PHY registers to see if Auto-Neg |
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421 * has completed and/or if our link status has changed. The |
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422 * get_link_status flag is set upon receiving a Link Status |
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423 * Change or Rx Sequence Error interrupt. |
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424 */ |
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425 if (!mac->get_link_status) |
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426 return 0; |
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427 |
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428 /* First we want to see if the MII Status Register reports |
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429 * link. If so, then we want to get the current speed/duplex |
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430 * of the PHY. |
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431 */ |
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432 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
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433 if (ret_val) |
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434 return ret_val; |
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435 |
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436 if (!link) |
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437 return 0; /* No link detected */ |
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438 |
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439 mac->get_link_status = false; |
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440 |
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441 /* Check if there was DownShift, must be checked |
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442 * immediately after link-up |
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443 */ |
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444 e1000e_check_downshift(hw); |
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445 |
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446 /* If we are forcing speed/duplex, then we simply return since |
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447 * we have already determined whether we have link or not. |
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448 */ |
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449 if (!mac->autoneg) |
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450 return -E1000_ERR_CONFIG; |
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451 |
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452 /* Auto-Neg is enabled. Auto Speed Detection takes care |
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453 * of MAC speed/duplex configuration. So we only need to |
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454 * configure Collision Distance in the MAC. |
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455 */ |
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456 mac->ops.config_collision_dist(hw); |
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457 |
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458 /* Configure Flow Control now that Auto-Neg has completed. |
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459 * First, we need to restore the desired flow control |
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460 * settings because we may have had to re-autoneg with a |
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461 * different link partner. |
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462 */ |
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463 ret_val = e1000e_config_fc_after_link_up(hw); |
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464 if (ret_val) |
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465 e_dbg("Error configuring flow control\n"); |
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466 |
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467 return ret_val; |
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468 } |
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469 |
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470 /** |
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471 * e1000e_check_for_fiber_link - Check for link (Fiber) |
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472 * @hw: pointer to the HW structure |
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473 * |
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474 * Checks for link up on the hardware. If link is not up and we have |
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475 * a signal, then we need to force link up. |
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476 **/ |
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477 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) |
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478 { |
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479 struct e1000_mac_info *mac = &hw->mac; |
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480 u32 rxcw; |
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481 u32 ctrl; |
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482 u32 status; |
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483 s32 ret_val; |
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484 |
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485 ctrl = er32(CTRL); |
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486 status = er32(STATUS); |
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487 rxcw = er32(RXCW); |
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488 |
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489 /* If we don't have link (auto-negotiation failed or link partner |
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490 * cannot auto-negotiate), the cable is plugged in (we have signal), |
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491 * and our link partner is not trying to auto-negotiate with us (we |
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492 * are receiving idles or data), we need to force link up. We also |
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493 * need to give auto-negotiation time to complete, in case the cable |
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494 * was just plugged in. The autoneg_failed flag does this. |
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495 */ |
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496 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
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497 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && |
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498 !(rxcw & E1000_RXCW_C)) { |
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499 if (!mac->autoneg_failed) { |
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500 mac->autoneg_failed = true; |
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501 return 0; |
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502 } |
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503 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); |
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504 |
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505 /* Disable auto-negotiation in the TXCW register */ |
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506 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
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507 |
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508 /* Force link-up and also force full-duplex. */ |
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509 ctrl = er32(CTRL); |
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510 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
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511 ew32(CTRL, ctrl); |
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512 |
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513 /* Configure Flow Control after forcing link up. */ |
|
514 ret_val = e1000e_config_fc_after_link_up(hw); |
|
515 if (ret_val) { |
|
516 e_dbg("Error configuring flow control\n"); |
|
517 return ret_val; |
|
518 } |
|
519 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
520 /* If we are forcing link and we are receiving /C/ ordered |
|
521 * sets, re-enable auto-negotiation in the TXCW register |
|
522 * and disable forced link in the Device Control register |
|
523 * in an attempt to auto-negotiate with our link partner. |
|
524 */ |
|
525 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); |
|
526 ew32(TXCW, mac->txcw); |
|
527 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
528 |
|
529 mac->serdes_has_link = true; |
|
530 } |
|
531 |
|
532 return 0; |
|
533 } |
|
534 |
|
535 /** |
|
536 * e1000e_check_for_serdes_link - Check for link (Serdes) |
|
537 * @hw: pointer to the HW structure |
|
538 * |
|
539 * Checks for link up on the hardware. If link is not up and we have |
|
540 * a signal, then we need to force link up. |
|
541 **/ |
|
542 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) |
|
543 { |
|
544 struct e1000_mac_info *mac = &hw->mac; |
|
545 u32 rxcw; |
|
546 u32 ctrl; |
|
547 u32 status; |
|
548 s32 ret_val; |
|
549 |
|
550 ctrl = er32(CTRL); |
|
551 status = er32(STATUS); |
|
552 rxcw = er32(RXCW); |
|
553 |
|
554 /* If we don't have link (auto-negotiation failed or link partner |
|
555 * cannot auto-negotiate), and our link partner is not trying to |
|
556 * auto-negotiate with us (we are receiving idles or data), |
|
557 * we need to force link up. We also need to give auto-negotiation |
|
558 * time to complete. |
|
559 */ |
|
560 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
|
561 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { |
|
562 if (!mac->autoneg_failed) { |
|
563 mac->autoneg_failed = true; |
|
564 return 0; |
|
565 } |
|
566 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); |
|
567 |
|
568 /* Disable auto-negotiation in the TXCW register */ |
|
569 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
|
570 |
|
571 /* Force link-up and also force full-duplex. */ |
|
572 ctrl = er32(CTRL); |
|
573 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
574 ew32(CTRL, ctrl); |
|
575 |
|
576 /* Configure Flow Control after forcing link up. */ |
|
577 ret_val = e1000e_config_fc_after_link_up(hw); |
|
578 if (ret_val) { |
|
579 e_dbg("Error configuring flow control\n"); |
|
580 return ret_val; |
|
581 } |
|
582 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
583 /* If we are forcing link and we are receiving /C/ ordered |
|
584 * sets, re-enable auto-negotiation in the TXCW register |
|
585 * and disable forced link in the Device Control register |
|
586 * in an attempt to auto-negotiate with our link partner. |
|
587 */ |
|
588 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); |
|
589 ew32(TXCW, mac->txcw); |
|
590 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
591 |
|
592 mac->serdes_has_link = true; |
|
593 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { |
|
594 /* If we force link for non-auto-negotiation switch, check |
|
595 * link status based on MAC synchronization for internal |
|
596 * serdes media type. |
|
597 */ |
|
598 /* SYNCH bit and IV bit are sticky. */ |
|
599 udelay(10); |
|
600 rxcw = er32(RXCW); |
|
601 if (rxcw & E1000_RXCW_SYNCH) { |
|
602 if (!(rxcw & E1000_RXCW_IV)) { |
|
603 mac->serdes_has_link = true; |
|
604 e_dbg("SERDES: Link up - forced.\n"); |
|
605 } |
|
606 } else { |
|
607 mac->serdes_has_link = false; |
|
608 e_dbg("SERDES: Link down - force failed.\n"); |
|
609 } |
|
610 } |
|
611 |
|
612 if (E1000_TXCW_ANE & er32(TXCW)) { |
|
613 status = er32(STATUS); |
|
614 if (status & E1000_STATUS_LU) { |
|
615 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ |
|
616 udelay(10); |
|
617 rxcw = er32(RXCW); |
|
618 if (rxcw & E1000_RXCW_SYNCH) { |
|
619 if (!(rxcw & E1000_RXCW_IV)) { |
|
620 mac->serdes_has_link = true; |
|
621 e_dbg("SERDES: Link up - autoneg completed successfully.\n"); |
|
622 } else { |
|
623 mac->serdes_has_link = false; |
|
624 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); |
|
625 } |
|
626 } else { |
|
627 mac->serdes_has_link = false; |
|
628 e_dbg("SERDES: Link down - no sync.\n"); |
|
629 } |
|
630 } else { |
|
631 mac->serdes_has_link = false; |
|
632 e_dbg("SERDES: Link down - autoneg failed\n"); |
|
633 } |
|
634 } |
|
635 |
|
636 return 0; |
|
637 } |
|
638 |
|
639 /** |
|
640 * e1000_set_default_fc_generic - Set flow control default values |
|
641 * @hw: pointer to the HW structure |
|
642 * |
|
643 * Read the EEPROM for the default values for flow control and store the |
|
644 * values. |
|
645 **/ |
|
646 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) |
|
647 { |
|
648 s32 ret_val; |
|
649 u16 nvm_data; |
|
650 |
|
651 /* Read and store word 0x0F of the EEPROM. This word contains bits |
|
652 * that determine the hardware's default PAUSE (flow control) mode, |
|
653 * a bit that determines whether the HW defaults to enabling or |
|
654 * disabling auto-negotiation, and the direction of the |
|
655 * SW defined pins. If there is no SW over-ride of the flow |
|
656 * control setting, then the variable hw->fc will |
|
657 * be initialized based on a value in the EEPROM. |
|
658 */ |
|
659 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); |
|
660 |
|
661 if (ret_val) { |
|
662 e_dbg("NVM Read Error\n"); |
|
663 return ret_val; |
|
664 } |
|
665 |
|
666 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) |
|
667 hw->fc.requested_mode = e1000_fc_none; |
|
668 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) |
|
669 hw->fc.requested_mode = e1000_fc_tx_pause; |
|
670 else |
|
671 hw->fc.requested_mode = e1000_fc_full; |
|
672 |
|
673 return 0; |
|
674 } |
|
675 |
|
676 /** |
|
677 * e1000e_setup_link_generic - Setup flow control and link settings |
|
678 * @hw: pointer to the HW structure |
|
679 * |
|
680 * Determines which flow control settings to use, then configures flow |
|
681 * control. Calls the appropriate media-specific link configuration |
|
682 * function. Assuming the adapter has a valid link partner, a valid link |
|
683 * should be established. Assumes the hardware has previously been reset |
|
684 * and the transmitter and receiver are not enabled. |
|
685 **/ |
|
686 s32 e1000e_setup_link_generic(struct e1000_hw *hw) |
|
687 { |
|
688 s32 ret_val; |
|
689 |
|
690 /* In the case of the phy reset being blocked, we already have a link. |
|
691 * We do not need to set it up again. |
|
692 */ |
|
693 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) |
|
694 return 0; |
|
695 |
|
696 /* If requested flow control is set to default, set flow control |
|
697 * based on the EEPROM flow control settings. |
|
698 */ |
|
699 if (hw->fc.requested_mode == e1000_fc_default) { |
|
700 ret_val = e1000_set_default_fc_generic(hw); |
|
701 if (ret_val) |
|
702 return ret_val; |
|
703 } |
|
704 |
|
705 /* Save off the requested flow control mode for use later. Depending |
|
706 * on the link partner's capabilities, we may or may not use this mode. |
|
707 */ |
|
708 hw->fc.current_mode = hw->fc.requested_mode; |
|
709 |
|
710 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); |
|
711 |
|
712 /* Call the necessary media_type subroutine to configure the link. */ |
|
713 ret_val = hw->mac.ops.setup_physical_interface(hw); |
|
714 if (ret_val) |
|
715 return ret_val; |
|
716 |
|
717 /* Initialize the flow control address, type, and PAUSE timer |
|
718 * registers to their default values. This is done even if flow |
|
719 * control is disabled, because it does not hurt anything to |
|
720 * initialize these registers. |
|
721 */ |
|
722 e_dbg("Initializing the Flow Control address, type and timer regs\n"); |
|
723 ew32(FCT, FLOW_CONTROL_TYPE); |
|
724 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
|
725 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
|
726 |
|
727 ew32(FCTTV, hw->fc.pause_time); |
|
728 |
|
729 return e1000e_set_fc_watermarks(hw); |
|
730 } |
|
731 |
|
732 /** |
|
733 * e1000_commit_fc_settings_generic - Configure flow control |
|
734 * @hw: pointer to the HW structure |
|
735 * |
|
736 * Write the flow control settings to the Transmit Config Word Register (TXCW) |
|
737 * base on the flow control settings in e1000_mac_info. |
|
738 **/ |
|
739 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) |
|
740 { |
|
741 struct e1000_mac_info *mac = &hw->mac; |
|
742 u32 txcw; |
|
743 |
|
744 /* Check for a software override of the flow control settings, and |
|
745 * setup the device accordingly. If auto-negotiation is enabled, then |
|
746 * software will have to set the "PAUSE" bits to the correct value in |
|
747 * the Transmit Config Word Register (TXCW) and re-start auto- |
|
748 * negotiation. However, if auto-negotiation is disabled, then |
|
749 * software will have to manually configure the two flow control enable |
|
750 * bits in the CTRL register. |
|
751 * |
|
752 * The possible values of the "fc" parameter are: |
|
753 * 0: Flow control is completely disabled |
|
754 * 1: Rx flow control is enabled (we can receive pause frames, |
|
755 * but not send pause frames). |
|
756 * 2: Tx flow control is enabled (we can send pause frames but we |
|
757 * do not support receiving pause frames). |
|
758 * 3: Both Rx and Tx flow control (symmetric) are enabled. |
|
759 */ |
|
760 switch (hw->fc.current_mode) { |
|
761 case e1000_fc_none: |
|
762 /* Flow control completely disabled by a software over-ride. */ |
|
763 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
|
764 break; |
|
765 case e1000_fc_rx_pause: |
|
766 /* Rx Flow control is enabled and Tx Flow control is disabled |
|
767 * by a software over-ride. Since there really isn't a way to |
|
768 * advertise that we are capable of Rx Pause ONLY, we will |
|
769 * advertise that we support both symmetric and asymmetric Rx |
|
770 * PAUSE. Later, we will disable the adapter's ability to send |
|
771 * PAUSE frames. |
|
772 */ |
|
773 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
774 break; |
|
775 case e1000_fc_tx_pause: |
|
776 /* Tx Flow control is enabled, and Rx Flow control is disabled, |
|
777 * by a software over-ride. |
|
778 */ |
|
779 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
|
780 break; |
|
781 case e1000_fc_full: |
|
782 /* Flow control (both Rx and Tx) is enabled by a software |
|
783 * over-ride. |
|
784 */ |
|
785 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
786 break; |
|
787 default: |
|
788 e_dbg("Flow control param set incorrectly\n"); |
|
789 return -E1000_ERR_CONFIG; |
|
790 break; |
|
791 } |
|
792 |
|
793 ew32(TXCW, txcw); |
|
794 mac->txcw = txcw; |
|
795 |
|
796 return 0; |
|
797 } |
|
798 |
|
799 /** |
|
800 * e1000_poll_fiber_serdes_link_generic - Poll for link up |
|
801 * @hw: pointer to the HW structure |
|
802 * |
|
803 * Polls for link up by reading the status register, if link fails to come |
|
804 * up with auto-negotiation, then the link is forced if a signal is detected. |
|
805 **/ |
|
806 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) |
|
807 { |
|
808 struct e1000_mac_info *mac = &hw->mac; |
|
809 u32 i, status; |
|
810 s32 ret_val; |
|
811 |
|
812 /* If we have a signal (the cable is plugged in, or assumed true for |
|
813 * serdes media) then poll for a "Link-Up" indication in the Device |
|
814 * Status Register. Time-out if a link isn't seen in 500 milliseconds |
|
815 * seconds (Auto-negotiation should complete in less than 500 |
|
816 * milliseconds even if the other end is doing it in SW). |
|
817 */ |
|
818 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { |
|
819 usleep_range(10000, 20000); |
|
820 status = er32(STATUS); |
|
821 if (status & E1000_STATUS_LU) |
|
822 break; |
|
823 } |
|
824 if (i == FIBER_LINK_UP_LIMIT) { |
|
825 e_dbg("Never got a valid link from auto-neg!!!\n"); |
|
826 mac->autoneg_failed = true; |
|
827 /* AutoNeg failed to achieve a link, so we'll call |
|
828 * mac->check_for_link. This routine will force the |
|
829 * link up if we detect a signal. This will allow us to |
|
830 * communicate with non-autonegotiating link partners. |
|
831 */ |
|
832 ret_val = mac->ops.check_for_link(hw); |
|
833 if (ret_val) { |
|
834 e_dbg("Error while checking for link\n"); |
|
835 return ret_val; |
|
836 } |
|
837 mac->autoneg_failed = false; |
|
838 } else { |
|
839 mac->autoneg_failed = false; |
|
840 e_dbg("Valid Link Found\n"); |
|
841 } |
|
842 |
|
843 return 0; |
|
844 } |
|
845 |
|
846 /** |
|
847 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes |
|
848 * @hw: pointer to the HW structure |
|
849 * |
|
850 * Configures collision distance and flow control for fiber and serdes |
|
851 * links. Upon successful setup, poll for link. |
|
852 **/ |
|
853 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) |
|
854 { |
|
855 u32 ctrl; |
|
856 s32 ret_val; |
|
857 |
|
858 ctrl = er32(CTRL); |
|
859 |
|
860 /* Take the link out of reset */ |
|
861 ctrl &= ~E1000_CTRL_LRST; |
|
862 |
|
863 hw->mac.ops.config_collision_dist(hw); |
|
864 |
|
865 ret_val = e1000_commit_fc_settings_generic(hw); |
|
866 if (ret_val) |
|
867 return ret_val; |
|
868 |
|
869 /* Since auto-negotiation is enabled, take the link out of reset (the |
|
870 * link will be in reset, because we previously reset the chip). This |
|
871 * will restart auto-negotiation. If auto-negotiation is successful |
|
872 * then the link-up status bit will be set and the flow control enable |
|
873 * bits (RFCE and TFCE) will be set according to their negotiated value. |
|
874 */ |
|
875 e_dbg("Auto-negotiation enabled\n"); |
|
876 |
|
877 ew32(CTRL, ctrl); |
|
878 e1e_flush(); |
|
879 usleep_range(1000, 2000); |
|
880 |
|
881 /* For these adapters, the SW definable pin 1 is set when the optics |
|
882 * detect a signal. If we have a signal, then poll for a "Link-Up" |
|
883 * indication. |
|
884 */ |
|
885 if (hw->phy.media_type == e1000_media_type_internal_serdes || |
|
886 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { |
|
887 ret_val = e1000_poll_fiber_serdes_link_generic(hw); |
|
888 } else { |
|
889 e_dbg("No signal detected\n"); |
|
890 } |
|
891 |
|
892 return ret_val; |
|
893 } |
|
894 |
|
895 /** |
|
896 * e1000e_config_collision_dist_generic - Configure collision distance |
|
897 * @hw: pointer to the HW structure |
|
898 * |
|
899 * Configures the collision distance to the default value and is used |
|
900 * during link setup. |
|
901 **/ |
|
902 void e1000e_config_collision_dist_generic(struct e1000_hw *hw) |
|
903 { |
|
904 u32 tctl; |
|
905 |
|
906 tctl = er32(TCTL); |
|
907 |
|
908 tctl &= ~E1000_TCTL_COLD; |
|
909 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
|
910 |
|
911 ew32(TCTL, tctl); |
|
912 e1e_flush(); |
|
913 } |
|
914 |
|
915 /** |
|
916 * e1000e_set_fc_watermarks - Set flow control high/low watermarks |
|
917 * @hw: pointer to the HW structure |
|
918 * |
|
919 * Sets the flow control high/low threshold (watermark) registers. If |
|
920 * flow control XON frame transmission is enabled, then set XON frame |
|
921 * transmission as well. |
|
922 **/ |
|
923 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) |
|
924 { |
|
925 u32 fcrtl = 0, fcrth = 0; |
|
926 |
|
927 /* Set the flow control receive threshold registers. Normally, |
|
928 * these registers will be set to a default threshold that may be |
|
929 * adjusted later by the driver's runtime code. However, if the |
|
930 * ability to transmit pause frames is not enabled, then these |
|
931 * registers will be set to 0. |
|
932 */ |
|
933 if (hw->fc.current_mode & e1000_fc_tx_pause) { |
|
934 /* We need to set up the Receive Threshold high and low water |
|
935 * marks as well as (optionally) enabling the transmission of |
|
936 * XON frames. |
|
937 */ |
|
938 fcrtl = hw->fc.low_water; |
|
939 if (hw->fc.send_xon) |
|
940 fcrtl |= E1000_FCRTL_XONE; |
|
941 |
|
942 fcrth = hw->fc.high_water; |
|
943 } |
|
944 ew32(FCRTL, fcrtl); |
|
945 ew32(FCRTH, fcrth); |
|
946 |
|
947 return 0; |
|
948 } |
|
949 |
|
950 /** |
|
951 * e1000e_force_mac_fc - Force the MAC's flow control settings |
|
952 * @hw: pointer to the HW structure |
|
953 * |
|
954 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
|
955 * device control register to reflect the adapter settings. TFCE and RFCE |
|
956 * need to be explicitly set by software when a copper PHY is used because |
|
957 * autonegotiation is managed by the PHY rather than the MAC. Software must |
|
958 * also configure these bits when link is forced on a fiber connection. |
|
959 **/ |
|
960 s32 e1000e_force_mac_fc(struct e1000_hw *hw) |
|
961 { |
|
962 u32 ctrl; |
|
963 |
|
964 ctrl = er32(CTRL); |
|
965 |
|
966 /* Because we didn't get link via the internal auto-negotiation |
|
967 * mechanism (we either forced link or we got link via PHY |
|
968 * auto-neg), we have to manually enable/disable transmit an |
|
969 * receive flow control. |
|
970 * |
|
971 * The "Case" statement below enables/disable flow control |
|
972 * according to the "hw->fc.current_mode" parameter. |
|
973 * |
|
974 * The possible values of the "fc" parameter are: |
|
975 * 0: Flow control is completely disabled |
|
976 * 1: Rx flow control is enabled (we can receive pause |
|
977 * frames but not send pause frames). |
|
978 * 2: Tx flow control is enabled (we can send pause frames |
|
979 * frames but we do not receive pause frames). |
|
980 * 3: Both Rx and Tx flow control (symmetric) is enabled. |
|
981 * other: No other values should be possible at this point. |
|
982 */ |
|
983 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); |
|
984 |
|
985 switch (hw->fc.current_mode) { |
|
986 case e1000_fc_none: |
|
987 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
|
988 break; |
|
989 case e1000_fc_rx_pause: |
|
990 ctrl &= (~E1000_CTRL_TFCE); |
|
991 ctrl |= E1000_CTRL_RFCE; |
|
992 break; |
|
993 case e1000_fc_tx_pause: |
|
994 ctrl &= (~E1000_CTRL_RFCE); |
|
995 ctrl |= E1000_CTRL_TFCE; |
|
996 break; |
|
997 case e1000_fc_full: |
|
998 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
|
999 break; |
|
1000 default: |
|
1001 e_dbg("Flow control param set incorrectly\n"); |
|
1002 return -E1000_ERR_CONFIG; |
|
1003 } |
|
1004 |
|
1005 ew32(CTRL, ctrl); |
|
1006 |
|
1007 return 0; |
|
1008 } |
|
1009 |
|
1010 /** |
|
1011 * e1000e_config_fc_after_link_up - Configures flow control after link |
|
1012 * @hw: pointer to the HW structure |
|
1013 * |
|
1014 * Checks the status of auto-negotiation after link up to ensure that the |
|
1015 * speed and duplex were not forced. If the link needed to be forced, then |
|
1016 * flow control needs to be forced also. If auto-negotiation is enabled |
|
1017 * and did not fail, then we configure flow control based on our link |
|
1018 * partner. |
|
1019 **/ |
|
1020 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) |
|
1021 { |
|
1022 struct e1000_mac_info *mac = &hw->mac; |
|
1023 s32 ret_val = 0; |
|
1024 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
|
1025 u16 speed, duplex; |
|
1026 |
|
1027 /* Check for the case where we have fiber media and auto-neg failed |
|
1028 * so we had to force link. In this case, we need to force the |
|
1029 * configuration of the MAC to match the "fc" parameter. |
|
1030 */ |
|
1031 if (mac->autoneg_failed) { |
|
1032 if (hw->phy.media_type == e1000_media_type_fiber || |
|
1033 hw->phy.media_type == e1000_media_type_internal_serdes) |
|
1034 ret_val = e1000e_force_mac_fc(hw); |
|
1035 } else { |
|
1036 if (hw->phy.media_type == e1000_media_type_copper) |
|
1037 ret_val = e1000e_force_mac_fc(hw); |
|
1038 } |
|
1039 |
|
1040 if (ret_val) { |
|
1041 e_dbg("Error forcing flow control settings\n"); |
|
1042 return ret_val; |
|
1043 } |
|
1044 |
|
1045 /* Check for the case where we have copper media and auto-neg is |
|
1046 * enabled. In this case, we need to check and see if Auto-Neg |
|
1047 * has completed, and if so, how the PHY and link partner has |
|
1048 * flow control configured. |
|
1049 */ |
|
1050 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
|
1051 /* Read the MII Status Register and check to see if AutoNeg |
|
1052 * has completed. We read this twice because this reg has |
|
1053 * some "sticky" (latched) bits. |
|
1054 */ |
|
1055 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
|
1056 if (ret_val) |
|
1057 return ret_val; |
|
1058 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
|
1059 if (ret_val) |
|
1060 return ret_val; |
|
1061 |
|
1062 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
|
1063 e_dbg("Copper PHY and Auto Neg has not completed.\n"); |
|
1064 return ret_val; |
|
1065 } |
|
1066 |
|
1067 /* The AutoNeg process has completed, so we now need to |
|
1068 * read both the Auto Negotiation Advertisement |
|
1069 * Register (Address 4) and the Auto_Negotiation Base |
|
1070 * Page Ability Register (Address 5) to determine how |
|
1071 * flow control was negotiated. |
|
1072 */ |
|
1073 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); |
|
1074 if (ret_val) |
|
1075 return ret_val; |
|
1076 ret_val = |
|
1077 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); |
|
1078 if (ret_val) |
|
1079 return ret_val; |
|
1080 |
|
1081 /* Two bits in the Auto Negotiation Advertisement Register |
|
1082 * (Address 4) and two bits in the Auto Negotiation Base |
|
1083 * Page Ability Register (Address 5) determine flow control |
|
1084 * for both the PHY and the link partner. The following |
|
1085 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
|
1086 * 1999, describes these PAUSE resolution bits and how flow |
|
1087 * control is determined based upon these settings. |
|
1088 * NOTE: DC = Don't Care |
|
1089 * |
|
1090 * LOCAL DEVICE | LINK PARTNER |
|
1091 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
|
1092 *-------|---------|-------|---------|-------------------- |
|
1093 * 0 | 0 | DC | DC | e1000_fc_none |
|
1094 * 0 | 1 | 0 | DC | e1000_fc_none |
|
1095 * 0 | 1 | 1 | 0 | e1000_fc_none |
|
1096 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
|
1097 * 1 | 0 | 0 | DC | e1000_fc_none |
|
1098 * 1 | DC | 1 | DC | e1000_fc_full |
|
1099 * 1 | 1 | 0 | 0 | e1000_fc_none |
|
1100 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
|
1101 * |
|
1102 * Are both PAUSE bits set to 1? If so, this implies |
|
1103 * Symmetric Flow Control is enabled at both ends. The |
|
1104 * ASM_DIR bits are irrelevant per the spec. |
|
1105 * |
|
1106 * For Symmetric Flow Control: |
|
1107 * |
|
1108 * LOCAL DEVICE | LINK PARTNER |
|
1109 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
1110 *-------|---------|-------|---------|-------------------- |
|
1111 * 1 | DC | 1 | DC | E1000_fc_full |
|
1112 * |
|
1113 */ |
|
1114 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
1115 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
|
1116 /* Now we need to check if the user selected Rx ONLY |
|
1117 * of pause frames. In this case, we had to advertise |
|
1118 * FULL flow control because we could not advertise Rx |
|
1119 * ONLY. Hence, we must now check to see if we need to |
|
1120 * turn OFF the TRANSMISSION of PAUSE frames. |
|
1121 */ |
|
1122 if (hw->fc.requested_mode == e1000_fc_full) { |
|
1123 hw->fc.current_mode = e1000_fc_full; |
|
1124 e_dbg("Flow Control = FULL.\n"); |
|
1125 } else { |
|
1126 hw->fc.current_mode = e1000_fc_rx_pause; |
|
1127 e_dbg("Flow Control = Rx PAUSE frames only.\n"); |
|
1128 } |
|
1129 } |
|
1130 /* For receiving PAUSE frames ONLY. |
|
1131 * |
|
1132 * LOCAL DEVICE | LINK PARTNER |
|
1133 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
1134 *-------|---------|-------|---------|-------------------- |
|
1135 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
|
1136 */ |
|
1137 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
1138 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
1139 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
1140 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
1141 hw->fc.current_mode = e1000_fc_tx_pause; |
|
1142 e_dbg("Flow Control = Tx PAUSE frames only.\n"); |
|
1143 } |
|
1144 /* For transmitting PAUSE frames ONLY. |
|
1145 * |
|
1146 * LOCAL DEVICE | LINK PARTNER |
|
1147 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
1148 *-------|---------|-------|---------|-------------------- |
|
1149 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
|
1150 */ |
|
1151 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
1152 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
1153 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
1154 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
1155 hw->fc.current_mode = e1000_fc_rx_pause; |
|
1156 e_dbg("Flow Control = Rx PAUSE frames only.\n"); |
|
1157 } else { |
|
1158 /* Per the IEEE spec, at this point flow control |
|
1159 * should be disabled. |
|
1160 */ |
|
1161 hw->fc.current_mode = e1000_fc_none; |
|
1162 e_dbg("Flow Control = NONE.\n"); |
|
1163 } |
|
1164 |
|
1165 /* Now we need to do one last check... If we auto- |
|
1166 * negotiated to HALF DUPLEX, flow control should not be |
|
1167 * enabled per IEEE 802.3 spec. |
|
1168 */ |
|
1169 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); |
|
1170 if (ret_val) { |
|
1171 e_dbg("Error getting link speed and duplex\n"); |
|
1172 return ret_val; |
|
1173 } |
|
1174 |
|
1175 if (duplex == HALF_DUPLEX) |
|
1176 hw->fc.current_mode = e1000_fc_none; |
|
1177 |
|
1178 /* Now we call a subroutine to actually force the MAC |
|
1179 * controller to use the correct flow control settings. |
|
1180 */ |
|
1181 ret_val = e1000e_force_mac_fc(hw); |
|
1182 if (ret_val) { |
|
1183 e_dbg("Error forcing flow control settings\n"); |
|
1184 return ret_val; |
|
1185 } |
|
1186 } |
|
1187 |
|
1188 return 0; |
|
1189 } |
|
1190 |
|
1191 /** |
|
1192 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex |
|
1193 * @hw: pointer to the HW structure |
|
1194 * @speed: stores the current speed |
|
1195 * @duplex: stores the current duplex |
|
1196 * |
|
1197 * Read the status register for the current speed/duplex and store the current |
|
1198 * speed and duplex for copper connections. |
|
1199 **/ |
|
1200 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, |
|
1201 u16 *duplex) |
|
1202 { |
|
1203 u32 status; |
|
1204 |
|
1205 status = er32(STATUS); |
|
1206 if (status & E1000_STATUS_SPEED_1000) |
|
1207 *speed = SPEED_1000; |
|
1208 else if (status & E1000_STATUS_SPEED_100) |
|
1209 *speed = SPEED_100; |
|
1210 else |
|
1211 *speed = SPEED_10; |
|
1212 |
|
1213 if (status & E1000_STATUS_FD) |
|
1214 *duplex = FULL_DUPLEX; |
|
1215 else |
|
1216 *duplex = HALF_DUPLEX; |
|
1217 |
|
1218 e_dbg("%u Mbps, %s Duplex\n", |
|
1219 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, |
|
1220 *duplex == FULL_DUPLEX ? "Full" : "Half"); |
|
1221 |
|
1222 return 0; |
|
1223 } |
|
1224 |
|
1225 /** |
|
1226 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex |
|
1227 * @hw: pointer to the HW structure |
|
1228 * @speed: stores the current speed |
|
1229 * @duplex: stores the current duplex |
|
1230 * |
|
1231 * Sets the speed and duplex to gigabit full duplex (the only possible option) |
|
1232 * for fiber/serdes links. |
|
1233 **/ |
|
1234 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, |
|
1235 u16 *duplex) |
|
1236 { |
|
1237 *speed = SPEED_1000; |
|
1238 *duplex = FULL_DUPLEX; |
|
1239 |
|
1240 return 0; |
|
1241 } |
|
1242 |
|
1243 /** |
|
1244 * e1000e_get_hw_semaphore - Acquire hardware semaphore |
|
1245 * @hw: pointer to the HW structure |
|
1246 * |
|
1247 * Acquire the HW semaphore to access the PHY or NVM |
|
1248 **/ |
|
1249 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) |
|
1250 { |
|
1251 u32 swsm; |
|
1252 s32 timeout = hw->nvm.word_size + 1; |
|
1253 s32 i = 0; |
|
1254 |
|
1255 /* Get the SW semaphore */ |
|
1256 while (i < timeout) { |
|
1257 swsm = er32(SWSM); |
|
1258 if (!(swsm & E1000_SWSM_SMBI)) |
|
1259 break; |
|
1260 |
|
1261 udelay(50); |
|
1262 i++; |
|
1263 } |
|
1264 |
|
1265 if (i == timeout) { |
|
1266 e_dbg("Driver can't access device - SMBI bit is set.\n"); |
|
1267 return -E1000_ERR_NVM; |
|
1268 } |
|
1269 |
|
1270 /* Get the FW semaphore. */ |
|
1271 for (i = 0; i < timeout; i++) { |
|
1272 swsm = er32(SWSM); |
|
1273 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); |
|
1274 |
|
1275 /* Semaphore acquired if bit latched */ |
|
1276 if (er32(SWSM) & E1000_SWSM_SWESMBI) |
|
1277 break; |
|
1278 |
|
1279 udelay(50); |
|
1280 } |
|
1281 |
|
1282 if (i == timeout) { |
|
1283 /* Release semaphores */ |
|
1284 e1000e_put_hw_semaphore(hw); |
|
1285 e_dbg("Driver can't access the NVM\n"); |
|
1286 return -E1000_ERR_NVM; |
|
1287 } |
|
1288 |
|
1289 return 0; |
|
1290 } |
|
1291 |
|
1292 /** |
|
1293 * e1000e_put_hw_semaphore - Release hardware semaphore |
|
1294 * @hw: pointer to the HW structure |
|
1295 * |
|
1296 * Release hardware semaphore used to access the PHY or NVM |
|
1297 **/ |
|
1298 void e1000e_put_hw_semaphore(struct e1000_hw *hw) |
|
1299 { |
|
1300 u32 swsm; |
|
1301 |
|
1302 swsm = er32(SWSM); |
|
1303 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
|
1304 ew32(SWSM, swsm); |
|
1305 } |
|
1306 |
|
1307 /** |
|
1308 * e1000e_get_auto_rd_done - Check for auto read completion |
|
1309 * @hw: pointer to the HW structure |
|
1310 * |
|
1311 * Check EEPROM for Auto Read done bit. |
|
1312 **/ |
|
1313 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) |
|
1314 { |
|
1315 s32 i = 0; |
|
1316 |
|
1317 while (i < AUTO_READ_DONE_TIMEOUT) { |
|
1318 if (er32(EECD) & E1000_EECD_AUTO_RD) |
|
1319 break; |
|
1320 usleep_range(1000, 2000); |
|
1321 i++; |
|
1322 } |
|
1323 |
|
1324 if (i == AUTO_READ_DONE_TIMEOUT) { |
|
1325 e_dbg("Auto read by HW from NVM has not completed.\n"); |
|
1326 return -E1000_ERR_RESET; |
|
1327 } |
|
1328 |
|
1329 return 0; |
|
1330 } |
|
1331 |
|
1332 /** |
|
1333 * e1000e_valid_led_default - Verify a valid default LED config |
|
1334 * @hw: pointer to the HW structure |
|
1335 * @data: pointer to the NVM (EEPROM) |
|
1336 * |
|
1337 * Read the EEPROM for the current default LED configuration. If the |
|
1338 * LED configuration is not valid, set to a valid LED configuration. |
|
1339 **/ |
|
1340 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) |
|
1341 { |
|
1342 s32 ret_val; |
|
1343 |
|
1344 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
|
1345 if (ret_val) { |
|
1346 e_dbg("NVM Read Error\n"); |
|
1347 return ret_val; |
|
1348 } |
|
1349 |
|
1350 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
|
1351 *data = ID_LED_DEFAULT; |
|
1352 |
|
1353 return 0; |
|
1354 } |
|
1355 |
|
1356 /** |
|
1357 * e1000e_id_led_init_generic - |
|
1358 * @hw: pointer to the HW structure |
|
1359 * |
|
1360 **/ |
|
1361 s32 e1000e_id_led_init_generic(struct e1000_hw *hw) |
|
1362 { |
|
1363 struct e1000_mac_info *mac = &hw->mac; |
|
1364 s32 ret_val; |
|
1365 const u32 ledctl_mask = 0x000000FF; |
|
1366 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
|
1367 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
|
1368 u16 data, i, temp; |
|
1369 const u16 led_mask = 0x0F; |
|
1370 |
|
1371 ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
|
1372 if (ret_val) |
|
1373 return ret_val; |
|
1374 |
|
1375 mac->ledctl_default = er32(LEDCTL); |
|
1376 mac->ledctl_mode1 = mac->ledctl_default; |
|
1377 mac->ledctl_mode2 = mac->ledctl_default; |
|
1378 |
|
1379 for (i = 0; i < 4; i++) { |
|
1380 temp = (data >> (i << 2)) & led_mask; |
|
1381 switch (temp) { |
|
1382 case ID_LED_ON1_DEF2: |
|
1383 case ID_LED_ON1_ON2: |
|
1384 case ID_LED_ON1_OFF2: |
|
1385 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
1386 mac->ledctl_mode1 |= ledctl_on << (i << 3); |
|
1387 break; |
|
1388 case ID_LED_OFF1_DEF2: |
|
1389 case ID_LED_OFF1_ON2: |
|
1390 case ID_LED_OFF1_OFF2: |
|
1391 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
1392 mac->ledctl_mode1 |= ledctl_off << (i << 3); |
|
1393 break; |
|
1394 default: |
|
1395 /* Do nothing */ |
|
1396 break; |
|
1397 } |
|
1398 switch (temp) { |
|
1399 case ID_LED_DEF1_ON2: |
|
1400 case ID_LED_ON1_ON2: |
|
1401 case ID_LED_OFF1_ON2: |
|
1402 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
1403 mac->ledctl_mode2 |= ledctl_on << (i << 3); |
|
1404 break; |
|
1405 case ID_LED_DEF1_OFF2: |
|
1406 case ID_LED_ON1_OFF2: |
|
1407 case ID_LED_OFF1_OFF2: |
|
1408 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
1409 mac->ledctl_mode2 |= ledctl_off << (i << 3); |
|
1410 break; |
|
1411 default: |
|
1412 /* Do nothing */ |
|
1413 break; |
|
1414 } |
|
1415 } |
|
1416 |
|
1417 return 0; |
|
1418 } |
|
1419 |
|
1420 /** |
|
1421 * e1000e_setup_led_generic - Configures SW controllable LED |
|
1422 * @hw: pointer to the HW structure |
|
1423 * |
|
1424 * This prepares the SW controllable LED for use and saves the current state |
|
1425 * of the LED so it can be later restored. |
|
1426 **/ |
|
1427 s32 e1000e_setup_led_generic(struct e1000_hw *hw) |
|
1428 { |
|
1429 u32 ledctl; |
|
1430 |
|
1431 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) |
|
1432 return -E1000_ERR_CONFIG; |
|
1433 |
|
1434 if (hw->phy.media_type == e1000_media_type_fiber) { |
|
1435 ledctl = er32(LEDCTL); |
|
1436 hw->mac.ledctl_default = ledctl; |
|
1437 /* Turn off LED0 */ |
|
1438 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | |
|
1439 E1000_LEDCTL_LED0_MODE_MASK); |
|
1440 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
|
1441 E1000_LEDCTL_LED0_MODE_SHIFT); |
|
1442 ew32(LEDCTL, ledctl); |
|
1443 } else if (hw->phy.media_type == e1000_media_type_copper) { |
|
1444 ew32(LEDCTL, hw->mac.ledctl_mode1); |
|
1445 } |
|
1446 |
|
1447 return 0; |
|
1448 } |
|
1449 |
|
1450 /** |
|
1451 * e1000e_cleanup_led_generic - Set LED config to default operation |
|
1452 * @hw: pointer to the HW structure |
|
1453 * |
|
1454 * Remove the current LED configuration and set the LED configuration |
|
1455 * to the default value, saved from the EEPROM. |
|
1456 **/ |
|
1457 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) |
|
1458 { |
|
1459 ew32(LEDCTL, hw->mac.ledctl_default); |
|
1460 return 0; |
|
1461 } |
|
1462 |
|
1463 /** |
|
1464 * e1000e_blink_led_generic - Blink LED |
|
1465 * @hw: pointer to the HW structure |
|
1466 * |
|
1467 * Blink the LEDs which are set to be on. |
|
1468 **/ |
|
1469 s32 e1000e_blink_led_generic(struct e1000_hw *hw) |
|
1470 { |
|
1471 u32 ledctl_blink = 0; |
|
1472 u32 i; |
|
1473 |
|
1474 if (hw->phy.media_type == e1000_media_type_fiber) { |
|
1475 /* always blink LED0 for PCI-E fiber */ |
|
1476 ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
|
1477 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
|
1478 } else { |
|
1479 /* set the blink bit for each LED that's "on" (0x0E) |
|
1480 * in ledctl_mode2 |
|
1481 */ |
|
1482 ledctl_blink = hw->mac.ledctl_mode2; |
|
1483 for (i = 0; i < 4; i++) |
|
1484 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
|
1485 E1000_LEDCTL_MODE_LED_ON) |
|
1486 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
|
1487 (i * 8)); |
|
1488 } |
|
1489 |
|
1490 ew32(LEDCTL, ledctl_blink); |
|
1491 |
|
1492 return 0; |
|
1493 } |
|
1494 |
|
1495 /** |
|
1496 * e1000e_led_on_generic - Turn LED on |
|
1497 * @hw: pointer to the HW structure |
|
1498 * |
|
1499 * Turn LED on. |
|
1500 **/ |
|
1501 s32 e1000e_led_on_generic(struct e1000_hw *hw) |
|
1502 { |
|
1503 u32 ctrl; |
|
1504 |
|
1505 switch (hw->phy.media_type) { |
|
1506 case e1000_media_type_fiber: |
|
1507 ctrl = er32(CTRL); |
|
1508 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
1509 ctrl |= E1000_CTRL_SWDPIO0; |
|
1510 ew32(CTRL, ctrl); |
|
1511 break; |
|
1512 case e1000_media_type_copper: |
|
1513 ew32(LEDCTL, hw->mac.ledctl_mode2); |
|
1514 break; |
|
1515 default: |
|
1516 break; |
|
1517 } |
|
1518 |
|
1519 return 0; |
|
1520 } |
|
1521 |
|
1522 /** |
|
1523 * e1000e_led_off_generic - Turn LED off |
|
1524 * @hw: pointer to the HW structure |
|
1525 * |
|
1526 * Turn LED off. |
|
1527 **/ |
|
1528 s32 e1000e_led_off_generic(struct e1000_hw *hw) |
|
1529 { |
|
1530 u32 ctrl; |
|
1531 |
|
1532 switch (hw->phy.media_type) { |
|
1533 case e1000_media_type_fiber: |
|
1534 ctrl = er32(CTRL); |
|
1535 ctrl |= E1000_CTRL_SWDPIN0; |
|
1536 ctrl |= E1000_CTRL_SWDPIO0; |
|
1537 ew32(CTRL, ctrl); |
|
1538 break; |
|
1539 case e1000_media_type_copper: |
|
1540 ew32(LEDCTL, hw->mac.ledctl_mode1); |
|
1541 break; |
|
1542 default: |
|
1543 break; |
|
1544 } |
|
1545 |
|
1546 return 0; |
|
1547 } |
|
1548 |
|
1549 /** |
|
1550 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities |
|
1551 * @hw: pointer to the HW structure |
|
1552 * @no_snoop: bitmap of snoop events |
|
1553 * |
|
1554 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. |
|
1555 **/ |
|
1556 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) |
|
1557 { |
|
1558 u32 gcr; |
|
1559 |
|
1560 if (no_snoop) { |
|
1561 gcr = er32(GCR); |
|
1562 gcr &= ~(PCIE_NO_SNOOP_ALL); |
|
1563 gcr |= no_snoop; |
|
1564 ew32(GCR, gcr); |
|
1565 } |
|
1566 } |
|
1567 |
|
1568 /** |
|
1569 * e1000e_disable_pcie_master - Disables PCI-express master access |
|
1570 * @hw: pointer to the HW structure |
|
1571 * |
|
1572 * Returns 0 if successful, else returns -10 |
|
1573 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
|
1574 * the master requests to be disabled. |
|
1575 * |
|
1576 * Disables PCI-Express master access and verifies there are no pending |
|
1577 * requests. |
|
1578 **/ |
|
1579 s32 e1000e_disable_pcie_master(struct e1000_hw *hw) |
|
1580 { |
|
1581 u32 ctrl; |
|
1582 s32 timeout = MASTER_DISABLE_TIMEOUT; |
|
1583 |
|
1584 ctrl = er32(CTRL); |
|
1585 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
|
1586 ew32(CTRL, ctrl); |
|
1587 |
|
1588 while (timeout) { |
|
1589 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
|
1590 break; |
|
1591 udelay(100); |
|
1592 timeout--; |
|
1593 } |
|
1594 |
|
1595 if (!timeout) { |
|
1596 e_dbg("Master requests are pending.\n"); |
|
1597 return -E1000_ERR_MASTER_REQUESTS_PENDING; |
|
1598 } |
|
1599 |
|
1600 return 0; |
|
1601 } |
|
1602 |
|
1603 /** |
|
1604 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing |
|
1605 * @hw: pointer to the HW structure |
|
1606 * |
|
1607 * Reset the Adaptive Interframe Spacing throttle to default values. |
|
1608 **/ |
|
1609 void e1000e_reset_adaptive(struct e1000_hw *hw) |
|
1610 { |
|
1611 struct e1000_mac_info *mac = &hw->mac; |
|
1612 |
|
1613 if (!mac->adaptive_ifs) { |
|
1614 e_dbg("Not in Adaptive IFS mode!\n"); |
|
1615 return; |
|
1616 } |
|
1617 |
|
1618 mac->current_ifs_val = 0; |
|
1619 mac->ifs_min_val = IFS_MIN; |
|
1620 mac->ifs_max_val = IFS_MAX; |
|
1621 mac->ifs_step_size = IFS_STEP; |
|
1622 mac->ifs_ratio = IFS_RATIO; |
|
1623 |
|
1624 mac->in_ifs_mode = false; |
|
1625 ew32(AIT, 0); |
|
1626 } |
|
1627 |
|
1628 /** |
|
1629 * e1000e_update_adaptive - Update Adaptive Interframe Spacing |
|
1630 * @hw: pointer to the HW structure |
|
1631 * |
|
1632 * Update the Adaptive Interframe Spacing Throttle value based on the |
|
1633 * time between transmitted packets and time between collisions. |
|
1634 **/ |
|
1635 void e1000e_update_adaptive(struct e1000_hw *hw) |
|
1636 { |
|
1637 struct e1000_mac_info *mac = &hw->mac; |
|
1638 |
|
1639 if (!mac->adaptive_ifs) { |
|
1640 e_dbg("Not in Adaptive IFS mode!\n"); |
|
1641 return; |
|
1642 } |
|
1643 |
|
1644 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
|
1645 if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
|
1646 mac->in_ifs_mode = true; |
|
1647 if (mac->current_ifs_val < mac->ifs_max_val) { |
|
1648 if (!mac->current_ifs_val) |
|
1649 mac->current_ifs_val = mac->ifs_min_val; |
|
1650 else |
|
1651 mac->current_ifs_val += |
|
1652 mac->ifs_step_size; |
|
1653 ew32(AIT, mac->current_ifs_val); |
|
1654 } |
|
1655 } |
|
1656 } else { |
|
1657 if (mac->in_ifs_mode && |
|
1658 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { |
|
1659 mac->current_ifs_val = 0; |
|
1660 mac->in_ifs_mode = false; |
|
1661 ew32(AIT, 0); |
|
1662 } |
|
1663 } |
|
1664 } |