1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2012 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* 82571EB Gigabit Ethernet Controller

    30  * 82571EB Gigabit Ethernet Controller (Copper)

    31  * 82571EB Gigabit Ethernet Controller (Fiber)

    32  * 82571EB Dual Port Gigabit Mezzanine Adapter

    33  * 82571EB Quad Port Gigabit Mezzanine Adapter

    34  * 82571PT Gigabit PT Quad Port Server ExpressModule

    35  * 82572EI Gigabit Ethernet Controller (Copper)

    36  * 82572EI Gigabit Ethernet Controller (Fiber)

    37  * 82572EI Gigabit Ethernet Controller

    38  * 82573V Gigabit Ethernet Controller (Copper)

    39  * 82573E Gigabit Ethernet Controller (Copper)

    40  * 82573L Gigabit Ethernet Controller

    41  * 82574L Gigabit Network Connection

    42  * 82583V Gigabit Network Connection

    43  */

    44 

    45 #include "e1000.h"

    46 

    47 #define ID_LED_RESERVED_F746 0xF746

    48 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \

    49 			      (ID_LED_OFF1_ON2  <<  8) | \

    50 			      (ID_LED_DEF1_DEF2 <<  4) | \

    51 			      (ID_LED_DEF1_DEF2))

    52 

    53 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000

    54 #define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */

    55 #define E1000_BASE1000T_STATUS          10

    56 #define E1000_IDLE_ERROR_COUNT_MASK     0xFF

    57 #define E1000_RECEIVE_ERROR_COUNTER     21

    58 #define E1000_RECEIVE_ERROR_MAX         0xFFFF

    59 

    60 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */

    61 

    62 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);

    63 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);

    64 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);

    65 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

    66 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

    67 				      u16 words, u16 *data);

    68 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);

    69 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);

    70 static s32 e1000_setup_link_82571(struct e1000_hw *hw);

    71 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);

    72 static void e1000_clear_vfta_82571(struct e1000_hw *hw);

    73 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);

    74 static s32 e1000_led_on_82574(struct e1000_hw *hw);

    75 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);

    76 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);

    77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);

    78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);

    79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);

    80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);

    81 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);

    82 

    83 /**

    84  *  e1000_init_phy_params_82571 - Init PHY func ptrs.

    85  *  @hw: pointer to the HW structure

    86  **/

    87 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)

    88 {

    89 	struct e1000_phy_info *phy = &hw->phy;

    90 	s32 ret_val;

    91 

    92 	if (hw->phy.media_type != e1000_media_type_copper) {

    93 		phy->type = e1000_phy_none;

    94 		return 0;

    95 	}

    96 

    97 	phy->addr			 = 1;

    98 	phy->autoneg_mask		 = AUTONEG_ADVERTISE_SPEED_DEFAULT;

    99 	phy->reset_delay_us		 = 100;

   100 

   101 	phy->ops.power_up		 = e1000_power_up_phy_copper;

   102 	phy->ops.power_down		 = e1000_power_down_phy_copper_82571;

   103 

   104 	switch (hw->mac.type) {

   105 	case e1000_82571:

   106 	case e1000_82572:

   107 		phy->type		 = e1000_phy_igp_2;

   108 		break;

   109 	case e1000_82573:

   110 		phy->type		 = e1000_phy_m88;

   111 		break;

   112 	case e1000_82574:

   113 	case e1000_82583:

   114 		phy->type		 = e1000_phy_bm;

   115 		phy->ops.acquire = e1000_get_hw_semaphore_82574;

   116 		phy->ops.release = e1000_put_hw_semaphore_82574;

   117 		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;

   118 		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;

   119 		break;

   120 	default:

   121 		return -E1000_ERR_PHY;

   122 		break;

   123 	}

   124 

   125 	/* This can only be done after all function pointers are setup. */

   126 	ret_val = e1000_get_phy_id_82571(hw);

   127 	if (ret_val) {

   128 		e_dbg("Error getting PHY ID\n");

   129 		return ret_val;

   130 	}

   131 

   132 	/* Verify phy id */

   133 	switch (hw->mac.type) {

   134 	case e1000_82571:

   135 	case e1000_82572:

   136 		if (phy->id != IGP01E1000_I_PHY_ID)

   137 			ret_val = -E1000_ERR_PHY;

   138 		break;

   139 	case e1000_82573:

   140 		if (phy->id != M88E1111_I_PHY_ID)

   141 			ret_val = -E1000_ERR_PHY;

   142 		break;

   143 	case e1000_82574:

   144 	case e1000_82583:

   145 		if (phy->id != BME1000_E_PHY_ID_R2)

   146 			ret_val = -E1000_ERR_PHY;

   147 		break;

   148 	default:

   149 		ret_val = -E1000_ERR_PHY;

   150 		break;

   151 	}

   152 

   153 	if (ret_val)

   154 		e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);

   155 

   156 	return ret_val;

   157 }

   158 

   159 /**

   160  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.

   161  *  @hw: pointer to the HW structure

   162  **/

   163 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)

   164 {

   165 	struct e1000_nvm_info *nvm = &hw->nvm;

   166 	u32 eecd = er32(EECD);

   167 	u16 size;

   168 

   169 	nvm->opcode_bits = 8;

   170 	nvm->delay_usec = 1;

   171 	switch (nvm->override) {

   172 	case e1000_nvm_override_spi_large:

   173 		nvm->page_size = 32;

   174 		nvm->address_bits = 16;

   175 		break;

   176 	case e1000_nvm_override_spi_small:

   177 		nvm->page_size = 8;

   178 		nvm->address_bits = 8;

   179 		break;

   180 	default:

   181 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   182 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   183 		break;

   184 	}

   185 

   186 	switch (hw->mac.type) {

   187 	case e1000_82573:

   188 	case e1000_82574:

   189 	case e1000_82583:

   190 		if (((eecd >> 15) & 0x3) == 0x3) {

   191 			nvm->type = e1000_nvm_flash_hw;

   192 			nvm->word_size = 2048;

   193 			/* Autonomous Flash update bit must be cleared due

   194 			 * to Flash update issue.

   195 			 */

   196 			eecd &= ~E1000_EECD_AUPDEN;

   197 			ew32(EECD, eecd);

   198 			break;

   199 		}

   200 		/* Fall Through */

   201 	default:

   202 		nvm->type = e1000_nvm_eeprom_spi;

   203 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   204 				  E1000_EECD_SIZE_EX_SHIFT);

   205 		/* Added to a constant, "size" becomes the left-shift value

   206 		 * for setting word_size.

   207 		 */

   208 		size += NVM_WORD_SIZE_BASE_SHIFT;

   209 

   210 		/* EEPROM access above 16k is unsupported */

   211 		if (size > 14)

   212 			size = 14;

   213 		nvm->word_size	= 1 << size;

   214 		break;

   215 	}

   216 

   217 	/* Function Pointers */

   218 	switch (hw->mac.type) {

   219 	case e1000_82574:

   220 	case e1000_82583:

   221 		nvm->ops.acquire = e1000_get_hw_semaphore_82574;

   222 		nvm->ops.release = e1000_put_hw_semaphore_82574;

   223 		break;

   224 	default:

   225 		break;

   226 	}

   227 

   228 	return 0;

   229 }

   230 

   231 /**

   232  *  e1000_init_mac_params_82571 - Init MAC func ptrs.

   233  *  @hw: pointer to the HW structure

   234  **/

   235 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)

   236 {

   237 	struct e1000_mac_info *mac = &hw->mac;

   238 	u32 swsm = 0;

   239 	u32 swsm2 = 0;

   240 	bool force_clear_smbi = false;

   241 

   242 	/* Set media type and media-dependent function pointers */

   243 	switch (hw->adapter->pdev->device) {

   244 	case E1000_DEV_ID_82571EB_FIBER:

   245 	case E1000_DEV_ID_82572EI_FIBER:

   246 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   247 		hw->phy.media_type = e1000_media_type_fiber;

   248 		mac->ops.setup_physical_interface =

   249 		    e1000_setup_fiber_serdes_link_82571;

   250 		mac->ops.check_for_link = e1000e_check_for_fiber_link;

   251 		mac->ops.get_link_up_info =

   252 		    e1000e_get_speed_and_duplex_fiber_serdes;

   253 		break;

   254 	case E1000_DEV_ID_82571EB_SERDES:

   255 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   256 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   257 	case E1000_DEV_ID_82572EI_SERDES:

   258 		hw->phy.media_type = e1000_media_type_internal_serdes;

   259 		mac->ops.setup_physical_interface =

   260 		    e1000_setup_fiber_serdes_link_82571;

   261 		mac->ops.check_for_link = e1000_check_for_serdes_link_82571;

   262 		mac->ops.get_link_up_info =

   263 		    e1000e_get_speed_and_duplex_fiber_serdes;

   264 		break;

   265 	default:

   266 		hw->phy.media_type = e1000_media_type_copper;

   267 		mac->ops.setup_physical_interface =

   268 		    e1000_setup_copper_link_82571;

   269 		mac->ops.check_for_link = e1000e_check_for_copper_link;

   270 		mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;

   271 		break;

   272 	}

   273 

   274 	/* Set mta register count */

   275 	mac->mta_reg_count = 128;

   276 	/* Set rar entry count */

   277 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   278 	/* Adaptive IFS supported */

   279 	mac->adaptive_ifs = true;

   280 

   281 	/* MAC-specific function pointers */

   282 	switch (hw->mac.type) {

   283 	case e1000_82573:

   284 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;

   285 		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;

   286 		mac->ops.led_on = e1000e_led_on_generic;

   287 		mac->ops.blink_led = e1000e_blink_led_generic;

   288 

   289 		/* FWSM register */

   290 		mac->has_fwsm = true;

   291 		/* ARC supported; valid only if manageability features are

   292 		 * enabled.

   293 		 */

   294 		mac->arc_subsystem_valid = !!(er32(FWSM) &

   295 					      E1000_FWSM_MODE_MASK);

   296 		break;

   297 	case e1000_82574:

   298 	case e1000_82583:

   299 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;

   300 		mac->ops.check_mng_mode = e1000_check_mng_mode_82574;

   301 		mac->ops.led_on = e1000_led_on_82574;

   302 		break;

   303 	default:

   304 		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;

   305 		mac->ops.led_on = e1000e_led_on_generic;

   306 		mac->ops.blink_led = e1000e_blink_led_generic;

   307 

   308 		/* FWSM register */

   309 		mac->has_fwsm = true;

   310 		break;

   311 	}

   312 

   313 	/* Ensure that the inter-port SWSM.SMBI lock bit is clear before

   314 	 * first NVM or PHY access. This should be done for single-port

   315 	 * devices, and for one port only on dual-port devices so that

   316 	 * for those devices we can still use the SMBI lock to synchronize

   317 	 * inter-port accesses to the PHY & NVM.

   318 	 */

   319 	switch (hw->mac.type) {

   320 	case e1000_82571:

   321 	case e1000_82572:

   322 		swsm2 = er32(SWSM2);

   323 

   324 		if (!(swsm2 & E1000_SWSM2_LOCK)) {

   325 			/* Only do this for the first interface on this card */

   326 			ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);

   327 			force_clear_smbi = true;

   328 		} else {

   329 			force_clear_smbi = false;

   330 		}

   331 		break;

   332 	default:

   333 		force_clear_smbi = true;

   334 		break;

   335 	}

   336 

   337 	if (force_clear_smbi) {

   338 		/* Make sure SWSM.SMBI is clear */

   339 		swsm = er32(SWSM);

   340 		if (swsm & E1000_SWSM_SMBI) {

   341 			/* This bit should not be set on a first interface, and

   342 			 * indicates that the bootagent or EFI code has

   343 			 * improperly left this bit enabled

   344 			 */

   345 			e_dbg("Please update your 82571 Bootagent\n");

   346 		}

   347 		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);

   348 	}

   349 

   350 	/* Initialize device specific counter of SMBI acquisition timeouts. */

   351 	hw->dev_spec.e82571.smb_counter = 0;

   352 

   353 	return 0;

   354 }

   355 

   356 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)

   357 {

   358 	struct e1000_hw *hw = &adapter->hw;

   359 	static int global_quad_port_a; /* global port a indication */

   360 	struct pci_dev *pdev = adapter->pdev;

   361 	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;

   362 	s32 rc;

   363 

   364 	rc = e1000_init_mac_params_82571(hw);

   365 	if (rc)

   366 		return rc;

   367 

   368 	rc = e1000_init_nvm_params_82571(hw);

   369 	if (rc)

   370 		return rc;

   371 

   372 	rc = e1000_init_phy_params_82571(hw);

   373 	if (rc)

   374 		return rc;

   375 

   376 	/* tag quad port adapters first, it's used below */

   377 	switch (pdev->device) {

   378 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   379 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   380 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:

   381 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   382 		adapter->flags |= FLAG_IS_QUAD_PORT;

   383 		/* mark the first port */

   384 		if (global_quad_port_a == 0)

   385 			adapter->flags |= FLAG_IS_QUAD_PORT_A;

   386 		/* Reset for multiple quad port adapters */

   387 		global_quad_port_a++;

   388 		if (global_quad_port_a == 4)

   389 			global_quad_port_a = 0;

   390 		break;

   391 	default:

   392 		break;

   393 	}

   394 

   395 	switch (adapter->hw.mac.type) {

   396 	case e1000_82571:

   397 		/* these dual ports don't have WoL on port B at all */

   398 		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||

   399 		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||

   400 		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&

   401 		    (is_port_b))

   402 			adapter->flags &= ~FLAG_HAS_WOL;

   403 		/* quad ports only support WoL on port A */

   404 		if (adapter->flags & FLAG_IS_QUAD_PORT &&

   405 		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))

   406 			adapter->flags &= ~FLAG_HAS_WOL;

   407 		/* Does not support WoL on any port */

   408 		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)

   409 			adapter->flags &= ~FLAG_HAS_WOL;

   410 		break;

   411 	case e1000_82573:

   412 		if (pdev->device == E1000_DEV_ID_82573L) {

   413 			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;

   414 			adapter->max_hw_frame_size = DEFAULT_JUMBO;

   415 		}

   416 		break;

   417 	default:

   418 		break;

   419 	}

   420 

   421 	return 0;

   422 }

   423 

   424 /**

   425  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision

   426  *  @hw: pointer to the HW structure

   427  *

   428  *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   429  *  revision in the hardware structure.

   430  **/

   431 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)

   432 {

   433 	struct e1000_phy_info *phy = &hw->phy;

   434 	s32 ret_val;

   435 	u16 phy_id = 0;

   436 

   437 	switch (hw->mac.type) {

   438 	case e1000_82571:

   439 	case e1000_82572:

   440 		/* The 82571 firmware may still be configuring the PHY.

   441 		 * In this case, we cannot access the PHY until the

   442 		 * configuration is done.  So we explicitly set the

   443 		 * PHY ID.

   444 		 */

   445 		phy->id = IGP01E1000_I_PHY_ID;

   446 		break;

   447 	case e1000_82573:

   448 		return e1000e_get_phy_id(hw);

   449 		break;

   450 	case e1000_82574:

   451 	case e1000_82583:

   452 		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   453 		if (ret_val)

   454 			return ret_val;

   455 

   456 		phy->id = (u32)(phy_id << 16);

   457 		udelay(20);

   458 		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   459 		if (ret_val)

   460 			return ret_val;

   461 

   462 		phy->id |= (u32)(phy_id);

   463 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   464 		break;

   465 	default:

   466 		return -E1000_ERR_PHY;

   467 		break;

   468 	}

   469 

   470 	return 0;

   471 }

   472 

   473 /**

   474  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore

   475  *  @hw: pointer to the HW structure

   476  *

   477  *  Acquire the HW semaphore to access the PHY or NVM

   478  **/

   479 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)

   480 {

   481 	u32 swsm;

   482 	s32 sw_timeout = hw->nvm.word_size + 1;

   483 	s32 fw_timeout = hw->nvm.word_size + 1;

   484 	s32 i = 0;

   485 

   486 	/* If we have timedout 3 times on trying to acquire

   487 	 * the inter-port SMBI semaphore, there is old code

   488 	 * operating on the other port, and it is not

   489 	 * releasing SMBI. Modify the number of times that

   490 	 * we try for the semaphore to interwork with this

   491 	 * older code.

   492 	 */

   493 	if (hw->dev_spec.e82571.smb_counter > 2)

   494 		sw_timeout = 1;

   495 

   496 	/* Get the SW semaphore */

   497 	while (i < sw_timeout) {

   498 		swsm = er32(SWSM);

   499 		if (!(swsm & E1000_SWSM_SMBI))

   500 			break;

   501 

   502 		udelay(50);

   503 		i++;

   504 	}

   505 

   506 	if (i == sw_timeout) {

   507 		e_dbg("Driver can't access device - SMBI bit is set.\n");

   508 		hw->dev_spec.e82571.smb_counter++;

   509 	}

   510 	/* Get the FW semaphore. */

   511 	for (i = 0; i < fw_timeout; i++) {

   512 		swsm = er32(SWSM);

   513 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

   514 

   515 		/* Semaphore acquired if bit latched */

   516 		if (er32(SWSM) & E1000_SWSM_SWESMBI)

   517 			break;

   518 

   519 		udelay(50);

   520 	}

   521 

   522 	if (i == fw_timeout) {

   523 		/* Release semaphores */

   524 		e1000_put_hw_semaphore_82571(hw);

   525 		e_dbg("Driver can't access the NVM\n");

   526 		return -E1000_ERR_NVM;

   527 	}

   528 

   529 	return 0;

   530 }

   531 

   532 /**

   533  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore

   534  *  @hw: pointer to the HW structure

   535  *

   536  *  Release hardware semaphore used to access the PHY or NVM

   537  **/

   538 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)

   539 {

   540 	u32 swsm;

   541 

   542 	swsm = er32(SWSM);

   543 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

   544 	ew32(SWSM, swsm);

   545 }

   546 /**

   547  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore

   548  *  @hw: pointer to the HW structure

   549  *

   550  *  Acquire the HW semaphore during reset.

   551  *

   552  **/

   553 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)

   554 {

   555 	u32 extcnf_ctrl;

   556 	s32 i = 0;

   557 

   558 	extcnf_ctrl = er32(EXTCNF_CTRL);

   559 	extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   560 	do {

   561 		ew32(EXTCNF_CTRL, extcnf_ctrl);

   562 		extcnf_ctrl = er32(EXTCNF_CTRL);

   563 

   564 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   565 			break;

   566 

   567 		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   568 

   569 		usleep_range(2000, 4000);

   570 		i++;

   571 	} while (i < MDIO_OWNERSHIP_TIMEOUT);

   572 

   573 	if (i == MDIO_OWNERSHIP_TIMEOUT) {

   574 		/* Release semaphores */

   575 		e1000_put_hw_semaphore_82573(hw);

   576 		e_dbg("Driver can't access the PHY\n");

   577 		return -E1000_ERR_PHY;

   578 	}

   579 

   580 	return 0;

   581 }

   582 

   583 /**

   584  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore

   585  *  @hw: pointer to the HW structure

   586  *

   587  *  Release hardware semaphore used during reset.

   588  *

   589  **/

   590 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)

   591 {

   592 	u32 extcnf_ctrl;

   593 

   594 	extcnf_ctrl = er32(EXTCNF_CTRL);

   595 	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   596 	ew32(EXTCNF_CTRL, extcnf_ctrl);

   597 }

   598 

   599 static DEFINE_MUTEX(swflag_mutex);

   600 

   601 /**

   602  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore

   603  *  @hw: pointer to the HW structure

   604  *

   605  *  Acquire the HW semaphore to access the PHY or NVM.

   606  *

   607  **/

   608 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)

   609 {

   610 	s32 ret_val;

   611 

   612 	mutex_lock(&swflag_mutex);

   613 	ret_val = e1000_get_hw_semaphore_82573(hw);

   614 	if (ret_val)

   615 		mutex_unlock(&swflag_mutex);

   616 	return ret_val;

   617 }

   618 

   619 /**

   620  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore

   621  *  @hw: pointer to the HW structure

   622  *

   623  *  Release hardware semaphore used to access the PHY or NVM

   624  *

   625  **/

   626 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)

   627 {

   628 	e1000_put_hw_semaphore_82573(hw);

   629 	mutex_unlock(&swflag_mutex);

   630 }

   631 

   632 /**

   633  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state

   634  *  @hw: pointer to the HW structure

   635  *  @active: true to enable LPLU, false to disable

   636  *

   637  *  Sets the LPLU D0 state according to the active flag.

   638  *  LPLU will not be activated unless the

   639  *  device autonegotiation advertisement meets standards of

   640  *  either 10 or 10/100 or 10/100/1000 at all duplexes.

   641  *  This is a function pointer entry point only called by

   642  *  PHY setup routines.

   643  **/

   644 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)

   645 {

   646 	u32 data = er32(POEMB);

   647 

   648 	if (active)

   649 		data |= E1000_PHY_CTRL_D0A_LPLU;

   650 	else

   651 		data &= ~E1000_PHY_CTRL_D0A_LPLU;

   652 

   653 	ew32(POEMB, data);

   654 	return 0;

   655 }

   656 

   657 /**

   658  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3

   659  *  @hw: pointer to the HW structure

   660  *  @active: boolean used to enable/disable lplu

   661  *

   662  *  The low power link up (lplu) state is set to the power management level D3

   663  *  when active is true, else clear lplu for D3. LPLU

   664  *  is used during Dx states where the power conservation is most important.

   665  *  During driver activity, SmartSpeed should be enabled so performance is

   666  *  maintained.

   667  **/

   668 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)

   669 {

   670 	u32 data = er32(POEMB);

   671 

   672 	if (!active) {

   673 		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;

   674 	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

   675 		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||

   676 		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {

   677 		data |= E1000_PHY_CTRL_NOND0A_LPLU;

   678 	}

   679 

   680 	ew32(POEMB, data);

   681 	return 0;

   682 }

   683 

   684 /**

   685  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM

   686  *  @hw: pointer to the HW structure

   687  *

   688  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.

   689  *  Then for non-82573 hardware, set the EEPROM access request bit and wait

   690  *  for EEPROM access grant bit.  If the access grant bit is not set, release

   691  *  hardware semaphore.

   692  **/

   693 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)

   694 {

   695 	s32 ret_val;

   696 

   697 	ret_val = e1000_get_hw_semaphore_82571(hw);

   698 	if (ret_val)

   699 		return ret_val;

   700 

   701 	switch (hw->mac.type) {

   702 	case e1000_82573:

   703 		break;

   704 	default:

   705 		ret_val = e1000e_acquire_nvm(hw);

   706 		break;

   707 	}

   708 

   709 	if (ret_val)

   710 		e1000_put_hw_semaphore_82571(hw);

   711 

   712 	return ret_val;

   713 }

   714 

   715 /**

   716  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM

   717  *  @hw: pointer to the HW structure

   718  *

   719  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.

   720  **/

   721 static void e1000_release_nvm_82571(struct e1000_hw *hw)

   722 {

   723 	e1000e_release_nvm(hw);

   724 	e1000_put_hw_semaphore_82571(hw);

   725 }

   726 

   727 /**

   728  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface

   729  *  @hw: pointer to the HW structure

   730  *  @offset: offset within the EEPROM to be written to

   731  *  @words: number of words to write

   732  *  @data: 16 bit word(s) to be written to the EEPROM

   733  *

   734  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.

   735  *

   736  *  If e1000e_update_nvm_checksum is not called after this function, the

   737  *  EEPROM will most likely contain an invalid checksum.

   738  **/

   739 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,

   740 				 u16 *data)

   741 {

   742 	s32 ret_val;

   743 

   744 	switch (hw->mac.type) {

   745 	case e1000_82573:

   746 	case e1000_82574:

   747 	case e1000_82583:

   748 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);

   749 		break;

   750 	case e1000_82571:

   751 	case e1000_82572:

   752 		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);

   753 		break;

   754 	default:

   755 		ret_val = -E1000_ERR_NVM;

   756 		break;

   757 	}

   758 

   759 	return ret_val;

   760 }

   761 

   762 /**

   763  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum

   764  *  @hw: pointer to the HW structure

   765  *

   766  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM

   767  *  up to the checksum.  Then calculates the EEPROM checksum and writes the

   768  *  value to the EEPROM.

   769  **/

   770 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)

   771 {

   772 	u32 eecd;

   773 	s32 ret_val;

   774 	u16 i;

   775 

   776 	ret_val = e1000e_update_nvm_checksum_generic(hw);

   777 	if (ret_val)

   778 		return ret_val;

   779 

   780 	/* If our nvm is an EEPROM, then we're done

   781 	 * otherwise, commit the checksum to the flash NVM.

   782 	 */

   783 	if (hw->nvm.type != e1000_nvm_flash_hw)

   784 		return 0;

   785 

   786 	/* Check for pending operations. */

   787 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   788 		usleep_range(1000, 2000);

   789 		if (!(er32(EECD) & E1000_EECD_FLUPD))

   790 			break;

   791 	}

   792 

   793 	if (i == E1000_FLASH_UPDATES)

   794 		return -E1000_ERR_NVM;

   795 

   796 	/* Reset the firmware if using STM opcode. */

   797 	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

   798 		/* The enabling of and the actual reset must be done

   799 		 * in two write cycles.

   800 		 */

   801 		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);

   802 		e1e_flush();

   803 		ew32(HICR, E1000_HICR_FW_RESET);

   804 	}

   805 

   806 	/* Commit the write to flash */

   807 	eecd = er32(EECD) | E1000_EECD_FLUPD;

   808 	ew32(EECD, eecd);

   809 

   810 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   811 		usleep_range(1000, 2000);

   812 		if (!(er32(EECD) & E1000_EECD_FLUPD))

   813 			break;

   814 	}

   815 

   816 	if (i == E1000_FLASH_UPDATES)

   817 		return -E1000_ERR_NVM;

   818 

   819 	return 0;

   820 }

   821 

   822 /**

   823  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum

   824  *  @hw: pointer to the HW structure

   825  *

   826  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM

   827  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.

   828  **/

   829 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)

   830 {

   831 	if (hw->nvm.type == e1000_nvm_flash_hw)

   832 		e1000_fix_nvm_checksum_82571(hw);

   833 

   834 	return e1000e_validate_nvm_checksum_generic(hw);

   835 }

   836 

   837 /**

   838  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon

   839  *  @hw: pointer to the HW structure

   840  *  @offset: offset within the EEPROM to be written to

   841  *  @words: number of words to write

   842  *  @data: 16 bit word(s) to be written to the EEPROM

   843  *

   844  *  After checking for invalid values, poll the EEPROM to ensure the previous

   845  *  command has completed before trying to write the next word.  After write

   846  *  poll for completion.

   847  *

   848  *  If e1000e_update_nvm_checksum is not called after this function, the

   849  *  EEPROM will most likely contain an invalid checksum.

   850  **/

   851 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

   852 				      u16 words, u16 *data)

   853 {

   854 	struct e1000_nvm_info *nvm = &hw->nvm;

   855 	u32 i, eewr = 0;

   856 	s32 ret_val = 0;

   857 

   858 	/* A check for invalid values:  offset too large, too many words,

   859 	 * and not enough words.

   860 	 */

   861 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

   862 	    (words == 0)) {

   863 		e_dbg("nvm parameter(s) out of bounds\n");

   864 		return -E1000_ERR_NVM;

   865 	}

   866 

   867 	for (i = 0; i < words; i++) {

   868 		eewr = (data[i] << E1000_NVM_RW_REG_DATA) |

   869 		       ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |

   870 		       E1000_NVM_RW_REG_START;

   871 

   872 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   873 		if (ret_val)

   874 			break;

   875 

   876 		ew32(EEWR, eewr);

   877 

   878 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   879 		if (ret_val)

   880 			break;

   881 	}

   882 

   883 	return ret_val;

   884 }

   885 

   886 /**

   887  *  e1000_get_cfg_done_82571 - Poll for configuration done

   888  *  @hw: pointer to the HW structure

   889  *

   890  *  Reads the management control register for the config done bit to be set.

   891  **/

   892 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)

   893 {

   894 	s32 timeout = PHY_CFG_TIMEOUT;

   895 

   896 	while (timeout) {

   897 		if (er32(EEMNGCTL) &

   898 		    E1000_NVM_CFG_DONE_PORT_0)

   899 			break;

   900 		usleep_range(1000, 2000);

   901 		timeout--;

   902 	}

   903 	if (!timeout) {

   904 		e_dbg("MNG configuration cycle has not completed.\n");

   905 		return -E1000_ERR_RESET;

   906 	}

   907 

   908 	return 0;

   909 }

   910 

   911 /**

   912  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state

   913  *  @hw: pointer to the HW structure

   914  *  @active: true to enable LPLU, false to disable

   915  *

   916  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU

   917  *  this function also disables smart speed and vice versa.  LPLU will not be

   918  *  activated unless the device autonegotiation advertisement meets standards

   919  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function

   920  *  pointer entry point only called by PHY setup routines.

   921  **/

   922 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)

   923 {

   924 	struct e1000_phy_info *phy = &hw->phy;

   925 	s32 ret_val;

   926 	u16 data;

   927 

   928 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);

   929 	if (ret_val)

   930 		return ret_val;

   931 

   932 	if (active) {

   933 		data |= IGP02E1000_PM_D0_LPLU;

   934 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   935 		if (ret_val)

   936 			return ret_val;

   937 

   938 		/* When LPLU is enabled, we should disable SmartSpeed */

   939 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);

   940 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   941 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);

   942 		if (ret_val)

   943 			return ret_val;

   944 	} else {

   945 		data &= ~IGP02E1000_PM_D0_LPLU;

   946 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   947 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used

   948 		 * during Dx states where the power conservation is most

   949 		 * important.  During driver activity we should enable

   950 		 * SmartSpeed, so performance is maintained.

   951 		 */

   952 		if (phy->smart_speed == e1000_smart_speed_on) {

   953 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   954 					   &data);

   955 			if (ret_val)

   956 				return ret_val;

   957 

   958 			data |= IGP01E1000_PSCFR_SMART_SPEED;

   959 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   960 					   data);

   961 			if (ret_val)

   962 				return ret_val;

   963 		} else if (phy->smart_speed == e1000_smart_speed_off) {

   964 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   965 					   &data);

   966 			if (ret_val)

   967 				return ret_val;

   968 

   969 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   970 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   971 					   data);

   972 			if (ret_val)

   973 				return ret_val;

   974 		}

   975 	}

   976 

   977 	return 0;

   978 }

   979 

   980 /**

   981  *  e1000_reset_hw_82571 - Reset hardware

   982  *  @hw: pointer to the HW structure

   983  *

   984  *  This resets the hardware into a known state.

   985  **/

   986 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)

   987 {

   988 	u32 ctrl, ctrl_ext, eecd, tctl;

   989 	s32 ret_val;

   990 

   991 	/* Prevent the PCI-E bus from sticking if there is no TLP connection

   992 	 * on the last TLP read/write transaction when MAC is reset.

   993 	 */

   994 	ret_val = e1000e_disable_pcie_master(hw);

   995 	if (ret_val)

   996 		e_dbg("PCI-E Master disable polling has failed.\n");

   997 

   998 	e_dbg("Masking off all interrupts\n");

   999 	ew32(IMC, 0xffffffff);

  1000 

  1001 	ew32(RCTL, 0);

  1002 	tctl = er32(TCTL);

  1003 	tctl &= ~E1000_TCTL_EN;

  1004 	ew32(TCTL, tctl);

  1005 	e1e_flush();

  1006 

  1007 	usleep_range(10000, 20000);

  1008 

  1009 	/* Must acquire the MDIO ownership before MAC reset.

  1010 	 * Ownership defaults to firmware after a reset.

  1011 	 */

  1012 	switch (hw->mac.type) {

  1013 	case e1000_82573:

  1014 		ret_val = e1000_get_hw_semaphore_82573(hw);

  1015 		break;

  1016 	case e1000_82574:

  1017 	case e1000_82583:

  1018 		ret_val = e1000_get_hw_semaphore_82574(hw);

  1019 		break;

  1020 	default:

  1021 		break;

  1022 	}

  1023 	if (ret_val)

  1024 		e_dbg("Cannot acquire MDIO ownership\n");

  1025 

  1026 	ctrl = er32(CTRL);

  1027 

  1028 	e_dbg("Issuing a global reset to MAC\n");

  1029 	ew32(CTRL, ctrl | E1000_CTRL_RST);

  1030 

  1031 	/* Must release MDIO ownership and mutex after MAC reset. */

  1032 	switch (hw->mac.type) {

  1033 	case e1000_82574:

  1034 	case e1000_82583:

  1035 		e1000_put_hw_semaphore_82574(hw);

  1036 		break;

  1037 	default:

  1038 		break;

  1039 	}

  1040 

  1041 	if (hw->nvm.type == e1000_nvm_flash_hw) {

  1042 		udelay(10);

  1043 		ctrl_ext = er32(CTRL_EXT);

  1044 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

  1045 		ew32(CTRL_EXT, ctrl_ext);

  1046 		e1e_flush();

  1047 	}

  1048 

  1049 	ret_val = e1000e_get_auto_rd_done(hw);

  1050 	if (ret_val)

  1051 		/* We don't want to continue accessing MAC registers. */

  1052 		return ret_val;

  1053 

  1054 	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.

  1055 	 * Need to wait for Phy configuration completion before accessing

  1056 	 * NVM and Phy.

  1057 	 */

  1058 

  1059 	switch (hw->mac.type) {

  1060 	case e1000_82571:

  1061 	case e1000_82572:

  1062 		/* REQ and GNT bits need to be cleared when using AUTO_RD

  1063 		 * to access the EEPROM.

  1064 		 */

  1065 		eecd = er32(EECD);

  1066 		eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);

  1067 		ew32(EECD, eecd);

  1068 		break;

  1069 	case e1000_82573:

  1070 	case e1000_82574:

  1071 	case e1000_82583:

  1072 		msleep(25);

  1073 		break;

  1074 	default:

  1075 		break;

  1076 	}

  1077 

  1078 	/* Clear any pending interrupt events. */

  1079 	ew32(IMC, 0xffffffff);

  1080 	er32(ICR);

  1081 

  1082 	if (hw->mac.type == e1000_82571) {

  1083 		/* Install any alternate MAC address into RAR0 */

  1084 		ret_val = e1000_check_alt_mac_addr_generic(hw);

  1085 		if (ret_val)

  1086 			return ret_val;

  1087 

  1088 		e1000e_set_laa_state_82571(hw, true);

  1089 	}

  1090 

  1091 	/* Reinitialize the 82571 serdes link state machine */

  1092 	if (hw->phy.media_type == e1000_media_type_internal_serdes)

  1093 		hw->mac.serdes_link_state = e1000_serdes_link_down;

  1094 

  1095 	return 0;

  1096 }

  1097 

  1098 /**

  1099  *  e1000_init_hw_82571 - Initialize hardware

  1100  *  @hw: pointer to the HW structure

  1101  *

  1102  *  This inits the hardware readying it for operation.

  1103  **/

  1104 static s32 e1000_init_hw_82571(struct e1000_hw *hw)

  1105 {

  1106 	struct e1000_mac_info *mac = &hw->mac;

  1107 	u32 reg_data;

  1108 	s32 ret_val;

  1109 	u16 i, rar_count = mac->rar_entry_count;

  1110 

  1111 	e1000_initialize_hw_bits_82571(hw);

  1112 

  1113 	/* Initialize identification LED */

  1114 	ret_val = mac->ops.id_led_init(hw);

  1115 	if (ret_val)

  1116 		e_dbg("Error initializing identification LED\n");

  1117 		/* This is not fatal and we should not stop init due to this */

  1118 

  1119 	/* Disabling VLAN filtering */

  1120 	e_dbg("Initializing the IEEE VLAN\n");

  1121 	mac->ops.clear_vfta(hw);

  1122 

  1123 	/* Setup the receive address.

  1124 	 * If, however, a locally administered address was assigned to the

  1125 	 * 82571, we must reserve a RAR for it to work around an issue where

  1126 	 * resetting one port will reload the MAC on the other port.

  1127 	 */

  1128 	if (e1000e_get_laa_state_82571(hw))

  1129 		rar_count--;

  1130 	e1000e_init_rx_addrs(hw, rar_count);

  1131 

  1132 	/* Zero out the Multicast HASH table */

  1133 	e_dbg("Zeroing the MTA\n");

  1134 	for (i = 0; i < mac->mta_reg_count; i++)

  1135 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

  1136