1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2012 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)

    30  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    31  */

    32 

    33 #include "e1000.h"

    34 

    35 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00

    36 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02

    37 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10

    38 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F

    39 

    40 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008

    41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800

    42 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010

    43 

    44 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

    45 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000

    46 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000

    47 

    48 #define E1000_KMRNCTRLSTA_OPMODE_MASK		 0x000C

    49 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	 0x0004

    50 

    51 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

    52 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000

    53 

    54 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8

    55 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9

    56 

    57 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */

    58 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */

    59 #define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060

    60 #define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */

    61 #define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */

    62 #define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */

    63 

    64 /* PHY Specific Control Register 2 (Page 0, Register 26) */

    65 #define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000

    66 						/* 1=Reverse Auto-Negotiation */

    67 

    68 /* MAC Specific Control Register (Page 2, Register 21) */

    69 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

    70 #define GG82563_MSCR_TX_CLK_MASK		 0x0007

    71 #define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004

    72 #define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005

    73 #define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007

    74 

    75 #define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */

    76 

    77 /* DSP Distance Register (Page 5, Register 26) */

    78 #define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M

    79 							   1 = 50-80M

    80 							   2 = 80-110M

    81 							   3 = 110-140M

    82 							   4 = >140M

    83 							*/

    84 

    85 /* Kumeran Mode Control Register (Page 193, Register 16) */

    86 #define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800

    87 

    88 /* Max number of times Kumeran read/write should be validated */

    89 #define GG82563_MAX_KMRN_RETRY  0x5

    90 

    91 /* Power Management Control Register (Page 193, Register 20) */

    92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001

    93 					   /* 1=Enable SERDES Electrical Idle */

    94 

    95 /* In-Band Control Register (Page 194, Register 18) */

    96 #define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */

    97 

    98 /* A table for the GG82563 cable length where the range is defined

    99  * with a lower bound at "index" and the upper bound at

   100  * "index + 5".

   101  */

   102 static const u16 e1000_gg82563_cable_length_table[] = {

   103 	 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };

   104 #define GG82563_CABLE_LENGTH_TABLE_SIZE \

   105 		ARRAY_SIZE(e1000_gg82563_cable_length_table)

   106 

   107 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

   108 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   109 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   110 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

   111 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

   112 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

   113 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

   114 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);

   115 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   116                                             u16 *data);

   117 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   118                                              u16 data);

   119 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);

   120 

   121 /**

   122  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

   123  *  @hw: pointer to the HW structure

   124  **/

   125 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

   126 {

   127 	struct e1000_phy_info *phy = &hw->phy;

   128 	s32 ret_val;

   129 

   130 	if (hw->phy.media_type != e1000_media_type_copper) {

   131 		phy->type	= e1000_phy_none;

   132 		return 0;

   133 	} else {

   134 		phy->ops.power_up = e1000_power_up_phy_copper;

   135 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

   136 	}

   137 

   138 	phy->addr		= 1;

   139 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

   140 	phy->reset_delay_us      = 100;

   141 	phy->type		= e1000_phy_gg82563;

   142 

   143 	/* This can only be done after all function pointers are setup. */

   144 	ret_val = e1000e_get_phy_id(hw);

   145 

   146 	/* Verify phy id */

   147 	if (phy->id != GG82563_E_PHY_ID)

   148 		return -E1000_ERR_PHY;

   149 

   150 	return ret_val;

   151 }

   152 

   153 /**

   154  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

   155  *  @hw: pointer to the HW structure

   156  **/

   157 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

   158 {

   159 	struct e1000_nvm_info *nvm = &hw->nvm;

   160 	u32 eecd = er32(EECD);

   161 	u16 size;

   162 

   163 	nvm->opcode_bits	= 8;

   164 	nvm->delay_usec	 = 1;

   165 	switch (nvm->override) {

   166 	case e1000_nvm_override_spi_large:

   167 		nvm->page_size    = 32;

   168 		nvm->address_bits = 16;

   169 		break;

   170 	case e1000_nvm_override_spi_small:

   171 		nvm->page_size    = 8;

   172 		nvm->address_bits = 8;

   173 		break;

   174 	default:

   175 		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   176 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   177 		break;

   178 	}

   179 

   180 	nvm->type = e1000_nvm_eeprom_spi;

   181 

   182 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   183 			  E1000_EECD_SIZE_EX_SHIFT);

   184 

   185 	/* Added to a constant, "size" becomes the left-shift value

   186 	 * for setting word_size.

   187 	 */

   188 	size += NVM_WORD_SIZE_BASE_SHIFT;

   189 

   190 	/* EEPROM access above 16k is unsupported */

   191 	if (size > 14)

   192 		size = 14;

   193 	nvm->word_size	= 1 << size;

   194 

   195 	return 0;

   196 }

   197 

   198 /**

   199  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   200  *  @hw: pointer to the HW structure

   201  **/

   202 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)

   203 {

   204 	struct e1000_mac_info *mac = &hw->mac;

   205 

   206 	/* Set media type and media-dependent function pointers */

   207 	switch (hw->adapter->pdev->device) {

   208 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   209 		hw->phy.media_type = e1000_media_type_internal_serdes;

   210 		mac->ops.check_for_link = e1000e_check_for_serdes_link;

   211 		mac->ops.setup_physical_interface =

   212 		    e1000e_setup_fiber_serdes_link;

   213 		break;

   214 	default:

   215 		hw->phy.media_type = e1000_media_type_copper;

   216 		mac->ops.check_for_link = e1000e_check_for_copper_link;

   217 		mac->ops.setup_physical_interface =

   218 		    e1000_setup_copper_link_80003es2lan;

   219 		break;

   220 	}

   221 

   222 	/* Set mta register count */

   223 	mac->mta_reg_count = 128;

   224 	/* Set rar entry count */

   225 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   226 	/* FWSM register */

   227 	mac->has_fwsm = true;

   228 	/* ARC supported; valid only if manageability features are enabled. */

   229 	mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);

   230 	/* Adaptive IFS not supported */

   231 	mac->adaptive_ifs = false;

   232 

   233 	/* set lan id for port to determine which phy lock to use */

   234 	hw->mac.ops.set_lan_id(hw);

   235 

   236 	return 0;

   237 }

   238 

   239 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   240 {

   241 	struct e1000_hw *hw = &adapter->hw;

   242 	s32 rc;

   243 

   244 	rc = e1000_init_mac_params_80003es2lan(hw);

   245 	if (rc)

   246 		return rc;

   247 

   248 	rc = e1000_init_nvm_params_80003es2lan(hw);

   249 	if (rc)

   250 		return rc;

   251 

   252 	rc = e1000_init_phy_params_80003es2lan(hw);

   253 	if (rc)

   254 		return rc;

   255 

   256 	return 0;

   257 }

   258 

   259 /**

   260  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   261  *  @hw: pointer to the HW structure

   262  *

   263  *  A wrapper to acquire access rights to the correct PHY.

   264  **/

   265 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   266 {

   267 	u16 mask;

   268 

   269 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   270 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   271 }

   272 

   273 /**

   274  *  e1000_release_phy_80003es2lan - Release rights to access PHY

   275  *  @hw: pointer to the HW structure

   276  *

   277  *  A wrapper to release access rights to the correct PHY.

   278  **/

   279 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   280 {

   281 	u16 mask;

   282 

   283 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   284 	e1000_release_swfw_sync_80003es2lan(hw, mask);

   285 }

   286 

   287 /**

   288  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register

   289  *  @hw: pointer to the HW structure

   290  *

   291  *  Acquire the semaphore to access the Kumeran interface.

   292  *

   293  **/

   294 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   295 {

   296 	u16 mask;

   297 

   298 	mask = E1000_SWFW_CSR_SM;

   299 

   300 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   301 }

   302 

   303 /**

   304  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register

   305  *  @hw: pointer to the HW structure

   306  *

   307  *  Release the semaphore used to access the Kumeran interface

   308  **/

   309 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   310 {

   311 	u16 mask;

   312 

   313 	mask = E1000_SWFW_CSR_SM;

   314 

   315 	e1000_release_swfw_sync_80003es2lan(hw, mask);

   316 }

   317 

   318 /**

   319  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   320  *  @hw: pointer to the HW structure

   321  *

   322  *  Acquire the semaphore to access the EEPROM.

   323  **/

   324 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   325 {

   326 	s32 ret_val;

   327 

   328 	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   329 	if (ret_val)

   330 		return ret_val;

   331 

   332 	ret_val = e1000e_acquire_nvm(hw);

   333 

   334 	if (ret_val)

   335 		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   336 

   337 	return ret_val;

   338 }

   339 

   340 /**

   341  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   342  *  @hw: pointer to the HW structure

   343  *

   344  *  Release the semaphore used to access the EEPROM.

   345  **/

   346 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   347 {

   348 	e1000e_release_nvm(hw);

   349 	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   350 }

   351 

   352 /**

   353  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   354  *  @hw: pointer to the HW structure

   355  *  @mask: specifies which semaphore to acquire

   356  *

   357  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   358  *  will also specify which port we're acquiring the lock for.

   359  **/

   360 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   361 {

   362 	u32 swfw_sync;

   363 	u32 swmask = mask;

   364 	u32 fwmask = mask << 16;

   365 	s32 i = 0;

   366 	s32 timeout = 50;

   367 

   368 	while (i < timeout) {

   369 		if (e1000e_get_hw_semaphore(hw))

   370 			return -E1000_ERR_SWFW_SYNC;

   371 

   372 		swfw_sync = er32(SW_FW_SYNC);

   373 		if (!(swfw_sync & (fwmask | swmask)))

   374 			break;

   375 

   376 		/* Firmware currently using resource (fwmask)

   377 		 * or other software thread using resource (swmask)

   378 		 */

   379 		e1000e_put_hw_semaphore(hw);

   380 		mdelay(5);

   381 		i++;

   382 	}

   383 

   384 	if (i == timeout) {

   385 		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");

   386 		return -E1000_ERR_SWFW_SYNC;

   387 	}

   388 

   389 	swfw_sync |= swmask;

   390 	ew32(SW_FW_SYNC, swfw_sync);

   391 

   392 	e1000e_put_hw_semaphore(hw);

   393 

   394 	return 0;

   395 }

   396 

   397 /**

   398  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   399  *  @hw: pointer to the HW structure

   400  *  @mask: specifies which semaphore to acquire

   401  *

   402  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   403  *  will also specify which port we're releasing the lock for.

   404  **/

   405 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   406 {

   407 	u32 swfw_sync;

   408 

   409 	while (e1000e_get_hw_semaphore(hw) != 0)

   410 		; /* Empty */

   411 

   412 	swfw_sync = er32(SW_FW_SYNC);

   413 	swfw_sync &= ~mask;

   414 	ew32(SW_FW_SYNC, swfw_sync);

   415 

   416 	e1000e_put_hw_semaphore(hw);

   417 }

   418 

   419 /**

   420  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   421  *  @hw: pointer to the HW structure

   422  *  @offset: offset of the register to read

   423  *  @data: pointer to the data returned from the operation

   424  *

   425  *  Read the GG82563 PHY register.

   426  **/

   427 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   428 						  u32 offset, u16 *data)

   429 {

   430 	s32 ret_val;

   431 	u32 page_select;

   432 	u16 temp;

   433 

   434 	ret_val = e1000_acquire_phy_80003es2lan(hw);

   435 	if (ret_val)

   436 		return ret_val;

   437 

   438 	/* Select Configuration Page */

   439 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   440 		page_select = GG82563_PHY_PAGE_SELECT;

   441 	} else {

   442 		/* Use Alternative Page Select register to access

   443 		 * registers 30 and 31

   444 		 */

   445 		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   446 	}

   447 

   448 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   449 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   450 	if (ret_val) {

   451 		e1000_release_phy_80003es2lan(hw);

   452 		return ret_val;

   453 	}

   454 

   455 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   456 		/* The "ready" bit in the MDIC register may be incorrectly set

   457 		 * before the device has completed the "Page Select" MDI

   458 		 * transaction.  So we wait 200us after each MDI command...

   459 		 */

   460 		udelay(200);

   461 

   462 		/* ...and verify the command was successful. */

   463 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   464 

   465 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   466 			e1000_release_phy_80003es2lan(hw);

   467 			return -E1000_ERR_PHY;

   468 		}

   469 

   470 		udelay(200);

   471 

   472 		ret_val = e1000e_read_phy_reg_mdic(hw,

   473 		                                  MAX_PHY_REG_ADDRESS & offset,

   474 		                                  data);

   475 

   476 		udelay(200);

   477 	} else {

   478 		ret_val = e1000e_read_phy_reg_mdic(hw,

   479 		                                  MAX_PHY_REG_ADDRESS & offset,

   480 		                                  data);

   481 	}

   482 

   483 	e1000_release_phy_80003es2lan(hw);

   484 

   485 	return ret_val;

   486 }

   487 

   488 /**

   489  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   490  *  @hw: pointer to the HW structure

   491  *  @offset: offset of the register to read

   492  *  @data: value to write to the register

   493  *

   494  *  Write to the GG82563 PHY register.

   495  **/

   496 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   497 						   u32 offset, u16 data)

   498 {

   499 	s32 ret_val;

   500 	u32 page_select;

   501 	u16 temp;

   502 

   503 	ret_val = e1000_acquire_phy_80003es2lan(hw);

   504 	if (ret_val)

   505 		return ret_val;

   506 

   507 	/* Select Configuration Page */

   508 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   509 		page_select = GG82563_PHY_PAGE_SELECT;

   510 	} else {

   511 		/* Use Alternative Page Select register to access

   512 		 * registers 30 and 31

   513 		 */

   514 		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   515 	}

   516 

   517 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   518 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   519 	if (ret_val) {

   520 		e1000_release_phy_80003es2lan(hw);

   521 		return ret_val;

   522 	}

   523 

   524 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   525 		/* The "ready" bit in the MDIC register may be incorrectly set

   526 		 * before the device has completed the "Page Select" MDI

   527 		 * transaction.  So we wait 200us after each MDI command...

   528 		 */

   529 		udelay(200);

   530 

   531 		/* ...and verify the command was successful. */

   532 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   533 

   534 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   535 			e1000_release_phy_80003es2lan(hw);

   536 			return -E1000_ERR_PHY;

   537 		}

   538 

   539 		udelay(200);

   540 

   541 		ret_val = e1000e_write_phy_reg_mdic(hw,

   542 		                                  MAX_PHY_REG_ADDRESS & offset,

   543 		                                  data);

   544 

   545 		udelay(200);

   546 	} else {

   547 		ret_val = e1000e_write_phy_reg_mdic(hw,

   548 		                                  MAX_PHY_REG_ADDRESS & offset,

   549 		                                  data);

   550 	}

   551 

   552 	e1000_release_phy_80003es2lan(hw);

   553 

   554 	return ret_val;

   555 }

   556 

   557 /**

   558  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM

   559  *  @hw: pointer to the HW structure

   560  *  @offset: offset of the register to read

   561  *  @words: number of words to write

   562  *  @data: buffer of data to write to the NVM

   563  *

   564  *  Write "words" of data to the ESB2 NVM.

   565  **/

   566 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,

   567 				       u16 words, u16 *data)

   568 {

   569 	return e1000e_write_nvm_spi(hw, offset, words, data);

   570 }

   571 

   572 /**

   573  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete

   574  *  @hw: pointer to the HW structure

   575  *

   576  *  Wait a specific amount of time for manageability processes to complete.

   577  *  This is a function pointer entry point called by the phy module.

   578  **/

   579 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)

   580 {

   581 	s32 timeout = PHY_CFG_TIMEOUT;

   582 	u32 mask = E1000_NVM_CFG_DONE_PORT_0;

   583 

   584 	if (hw->bus.func == 1)

   585 		mask = E1000_NVM_CFG_DONE_PORT_1;

   586 

   587 	while (timeout) {

   588 		if (er32(EEMNGCTL) & mask)

   589 			break;

   590 		usleep_range(1000, 2000);

   591 		timeout--;

   592 	}

   593 	if (!timeout) {

   594 		e_dbg("MNG configuration cycle has not completed.\n");

   595 		return -E1000_ERR_RESET;

   596 	}

   597 

   598 	return 0;

   599 }

   600 

   601 /**

   602  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex

   603  *  @hw: pointer to the HW structure

   604  *

   605  *  Force the speed and duplex settings onto the PHY.  This is a

   606  *  function pointer entry point called by the phy module.

   607  **/

   608 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)

   609 {

   610 	s32 ret_val;

   611 	u16 phy_data;

   612 	bool link;

   613 

   614 	/* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI

   615 	 * forced whenever speed and duplex are forced.

   616 	 */

   617 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

   618 	if (ret_val)

   619 		return ret_val;

   620 

   621 	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;

   622 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);

   623 	if (ret_val)

   624 		return ret_val;

   625 

   626 	e_dbg("GG82563 PSCR: %X\n", phy_data);

   627 

   628 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);

   629 	if (ret_val)

   630 		return ret_val;

   631 

   632 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);

   633 

   634 	/* Reset the phy to commit changes. */

   635 	phy_data |= MII_CR_RESET;

   636 

   637 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);

   638 	if (ret_val)

   639 		return ret_val;

   640 

   641 	udelay(1);

   642 

   643 	if (hw->phy.autoneg_wait_to_complete) {

   644 		e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");

   645 

   646 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,

   647 						     100000, &link);

   648 		if (ret_val)

   649 			return ret_val;

   650 

   651 		if (!link) {

   652 			/* We didn't get link.

   653 			 * Reset the DSP and cross our fingers.

   654 			 */

   655 			ret_val = e1000e_phy_reset_dsp(hw);

   656 			if (ret_val)

   657 				return ret_val;

   658 		}

   659 

   660 		/* Try once more */

   661 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,

   662 						     100000, &link);

   663 		if (ret_val)

   664 			return ret_val;

   665 	}

   666 

   667 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);

   668 	if (ret_val)

   669 		return ret_val;

   670 

   671 	/* Resetting the phy means we need to verify the TX_CLK corresponds

   672 	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.

   673 	 */

   674 	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;

   675 	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)

   676 		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;

   677 	else

   678 		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;

   679 

   680 	/* In addition, we must re-enable CRS on Tx for both half and full

   681 	 * duplex.

   682 	 */

   683 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;

   684 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);

   685 

   686 	return ret_val;

   687 }

   688 

   689 /**

   690  *  e1000_get_cable_length_80003es2lan - Set approximate cable length

   691  *  @hw: pointer to the HW structure

   692  *

   693  *  Find the approximate cable length as measured by the GG82563 PHY.

   694  *  This is a function pointer entry point called by the phy module.

   695  **/

   696 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)

   697 {

   698 	struct e1000_phy_info *phy = &hw->phy;

   699 	s32 ret_val = 0;

   700 	u16 phy_data, index;

   701 

   702 	ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);

   703 	if (ret_val)

   704 		return ret_val;

   705 

   706 	index = phy_data & GG82563_DSPD_CABLE_LENGTH;

   707 

   708 	if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)

   709 		return -E1000_ERR_PHY;

   710 

   711 	phy->min_cable_length = e1000_gg82563_cable_length_table[index];

   712 	phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];

   713 

   714 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;

   715 

   716 	return 0;

   717 }

   718 

   719 /**

   720  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex

   721  *  @hw: pointer to the HW structure

   722  *  @speed: pointer to speed buffer

   723  *  @duplex: pointer to duplex buffer

   724  *

   725  *  Retrieve the current speed and duplex configuration.

   726  **/

   727 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,

   728 					      u16 *duplex)

   729 {

   730 	s32 ret_val;

   731 

   732 	if (hw->phy.media_type == e1000_media_type_copper) {

   733 		ret_val = e1000e_get_speed_and_duplex_copper(hw,

   734 								    speed,

   735 								    duplex);

   736 		hw->phy.ops.cfg_on_link_up(hw);

   737 	} else {

   738 		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,

   739 								  speed,

   740 								  duplex);

   741 	}

   742 

   743 	return ret_val;

   744 }

   745 

   746 /**

   747  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller

   748  *  @hw: pointer to the HW structure

   749  *

   750  *  Perform a global reset to the ESB2 controller.

   751  **/

   752 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)

   753 {

   754 	u32 ctrl;

   755 	s32 ret_val;

   756 	u16 kum_reg_data;

   757 

   758 	/* Prevent the PCI-E bus from sticking if there is no TLP connection

   759 	 * on the last TLP read/write transaction when MAC is reset.

   760 	 */

   761 	ret_val = e1000e_disable_pcie_master(hw);

   762 	if (ret_val)

   763 		e_dbg("PCI-E Master disable polling has failed.\n");

   764 

   765 	e_dbg("Masking off all interrupts\n");

   766 	ew32(IMC, 0xffffffff);

   767 

   768 	ew32(RCTL, 0);

   769 	ew32(TCTL, E1000_TCTL_PSP);

   770 	e1e_flush();

   771 

   772 	usleep_range(10000, 20000);

   773 

   774 	ctrl = er32(CTRL);

   775 

   776 	ret_val = e1000_acquire_phy_80003es2lan(hw);

   777 	e_dbg("Issuing a global reset to MAC\n");

   778 	ew32(CTRL, ctrl | E1000_CTRL_RST);

   779 	e1000_release_phy_80003es2lan(hw);

   780 

   781 	/* Disable IBIST slave mode (far-end loopback) */

   782 	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

   783 					&kum_reg_data);

   784 	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;

   785 	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

   786 					 kum_reg_data);

   787 

   788 	ret_val = e1000e_get_auto_rd_done(hw);

   789 	if (ret_val)

   790 		/* We don't want to continue accessing MAC registers. */

   791 		return ret_val;

   792 

   793 	/* Clear any pending interrupt events. */

   794 	ew32(IMC, 0xffffffff);

   795 	er32(ICR);

   796 

   797 	return e1000_check_alt_mac_addr_generic(hw);

   798 }

   799 

   800 /**

   801  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller

   802  *  @hw: pointer to the HW structure

   803  *

   804  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.

   805  **/

   806 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)

   807 {

   808 	struct e1000_mac_info *mac = &hw->mac;

   809 	u32 reg_data;

   810 	s32 ret_val;

   811 	u16 kum_reg_data;

   812 	u16 i;

   813 

   814 	e1000_initialize_hw_bits_80003es2lan(hw);

   815 

   816 	/* Initialize identification LED */

   817 	ret_val = mac->ops.id_led_init(hw);

   818 	if (ret_val)

   819 		e_dbg("Error initializing identification LED\n");

   820 		/* This is not fatal and we should not stop init due to this */

   821 

   822 	/* Disabling VLAN filtering */

   823 	e_dbg("Initializing the IEEE VLAN\n");

   824 	mac->ops.clear_vfta(hw);

   825 

   826 	/* Setup the receive address. */

   827 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);

   828 

   829 	/* Zero out the Multicast HASH table */

   830 	e_dbg("Zeroing the MTA\n");

   831 	for (i = 0; i < mac->mta_reg_count; i++)

   832 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

   833 

   834 	/* Setup link and flow control */

   835 	ret_val = mac->ops.setup_link(hw);

   836 

   837 	/* Disable IBIST slave mode (far-end loopback) */

   838 	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

   839 					&kum_reg_data);

   840 	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;

   841 	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,

   842 					 kum_reg_data);

   843 

   844 	/* Set the transmit descriptor write-back policy */

   845 	reg_data = er32(TXDCTL(0));

   846 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

   847 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;

   848 	ew32(TXDCTL(0), reg_data);

   849 

   850 	/* ...for both queues. */

   851 	reg_data = er32(TXDCTL(1));

   852 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

   853 		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;

   854 	ew32(TXDCTL(1), reg_data);

   855 

   856 	/* Enable retransmit on late collisions */

   857 	reg_data = er32(TCTL);

   858 	reg_data |= E1000_TCTL_RTLC;

   859 	ew32(TCTL, reg_data);

   860 

   861 	/* Configure Gigabit Carry Extend Padding */

   862 	reg_data = er32(TCTL_EXT);

   863 	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;

   864 	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;

   865 	ew32(TCTL_EXT, reg_data);

   866 

   867 	/* Configure Transmit Inter-Packet Gap */

   868 	reg_data = er32(TIPG);

   869 	reg_data &= ~E1000_TIPG_IPGT_MASK;

   870 	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;

   871 	ew32(TIPG, reg_data);

   872 

   873 	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);

   874 	reg_data &= ~0x00100000;

   875 	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);

   876 

   877 	/* default to true to enable the MDIC W/A */

   878 	hw->dev_spec.e80003es2lan.mdic_wa_enable = true;

   879 

   880 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

   881 	                              E1000_KMRNCTRLSTA_OFFSET >>

   882 	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,

   883 	                              &i);

   884 	if (!ret_val) {

   885 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==

   886 		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)

   887 			hw->dev_spec.e80003es2lan.mdic_wa_enable = false;

   888 	}

   889 

   890 	/* Clear all of the statistics registers (clear on read).  It is

   891 	 * important that we do this after we have tried to establish link

   892 	 * because the symbol error count will increment wildly if there

   893 	 * is no link.

   894 	 */

   895 	e1000_clear_hw_cntrs_80003es2lan(hw);

   896 

   897 	return ret_val;

   898 }

   899 

   900 /**

   901  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2

   902  *  @hw: pointer to the HW structure

   903  *

   904  *  Initializes required hardware-dependent bits needed for normal operation.

   905  **/

   906 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)

   907 {

   908 	u32 reg;

   909 

   910 	/* Transmit Descriptor Control 0 */

   911 	reg = er32(TXDCTL(0));

   912 	reg |= (1 << 22);

   913 	ew32(TXDCTL(0), reg);

   914 

   915 	/* Transmit Descriptor Control 1 */

   916 	reg = er32(TXDCTL(1));

   917 	reg |= (1 << 22);

   918 	ew32(TXDCTL(1), reg);

   919 

   920 	/* Transmit Arbitration Control 0 */

   921 	reg = er32(TARC(0));

   922 	reg &= ~(0xF << 27); /* 30:27 */

   923 	if (hw->phy.media_type != e1000_media_type_copper)

   924 		reg &= ~(1 << 20);

   925 	ew32(TARC(0), reg);

   926 

   927 	/* Transmit Arbitration Control 1 */

   928 	reg = er32(TARC(1));

   929 	if (er32(TCTL) & E1000_TCTL_MULR)

   930 		reg &= ~(1 << 28);

   931 	else

   932 		reg |= (1 << 28);

   933 	ew32(TARC(1), reg);

   934 

   935 	/* Disable IPv6 extension header parsing because some malformed

   936 	 * IPv6 headers can hang the Rx.

   937 	 */

   938 	reg = er32(RFCTL);

   939 	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

   940 	ew32(RFCTL, reg);

   941 }

   942 

   943 /**

   944  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link

   945  *  @hw: pointer to the HW structure

   946  *

   947  *  Setup some GG82563 PHY registers for obtaining link

   948  **/

   949 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)

   950 {

   951 	struct e1000_phy_info *phy = &hw->phy;

   952 	s32 ret_val;

   953 	u32 ctrl_ext;

   954 	u16 data;

   955 

   956 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);

   957 	if (ret_val)

   958 		return ret_val;

   959 

   960 	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;

   961 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */

   962 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;

   963 

   964 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);

   965 	if (ret_val)

   966 		return ret_val;

   967 

   968 	/* Options:

   969 	 *   MDI/MDI-X = 0 (default)

   970 	 *   0 - Auto for all speeds

   971 	 *   1 - MDI mode

   972 	 *   2 - MDI-X mode

   973 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)

   974 	 */

   975 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);

   976 	if (ret_val)

   977 		return ret_val;

   978 

   979 	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;

   980 

   981 	switch (phy->mdix) {

   982 	case 1:

   983 		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;

   984 		break;

   985 	case 2:

   986 		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;

   987 		break;

   988 	case 0:

   989 	default:

   990 		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;

   991 		break;

   992 	}

   993 

   994 	/* Options:

   995 	 *   disable_polarity_correction = 0 (default)

   996 	 *       Automatic Correction for Reversed Cable Polarity

   997 	 *   0 - Disabled

   998 	 *   1 - Enabled

   999 	 */

  1000 	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;

  1001 	if (phy->disable_polarity_correction)

  1002 		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;

  1003 

  1004 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);

  1005 	if (ret_val)

  1006 		return ret_val;

  1007 

  1008 	/* SW Reset the PHY so all changes take effect */

  1009 	ret_val = e1000e_commit_phy(hw);

  1010 	if (ret_val) {

  1011 		e_dbg("Error Resetting the PHY\n");

  1012 		return ret_val;

  1013 	}

  1014 

  1015 	/* Bypass Rx and Tx FIFO's */

  1016 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

  1017 					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,

  1018 					E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |

  1019 					E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);

  1020 	if (ret_val)

  1021 		return ret_val;

  1022 

  1023 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

  1024 				       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,

  1025 				       &data);

  1026 	if (ret_val)

  1027 		return ret_val;

  1028 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;

  1029 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

  1030 					E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,

  1031 					data);

  1032 	if (ret_val)

  1033 		return ret_val;

  1034 

  1035 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);

  1036 	if (ret_val)

  1037 		return ret_val;

  1038 

  1039 	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;

  1040 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);

  1041 	if (ret_val)

  1042 		return ret_val;

  1043 

  1044 	ctrl_ext = er32(CTRL_EXT);

  1045 	ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);

  1046 	ew32(CTRL_EXT, ctrl_ext);

  1047 

  1048 	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);

  1049 	if (ret_val)

  1050 		return ret_val;

  1051 

  1052 	/* Do not init these registers when the HW is in IAMT mode, since the

  1053 	 * firmware will have already initialized them.  We only initialize

  1054 	 * them if the HW is not in IAMT mode.

  1055 	 */

  1056 	if (!hw->mac.ops.check_mng_mode(hw)) {

  1057 		/* Enable Electrical Idle on the PHY */

  1058 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;

  1059 		ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);

  1060 		if (ret_val)

  1061 			return ret_val;

  1062 

  1063 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);

  1064 		if (ret_val)

  1065 			return ret_val;

  1066 

  1067 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;

  1068 		ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);

  1069 		if (ret_val)

  1070 			return ret_val;

  1071 	}

  1072 

  1073 	/* Workaround: Disable padding in Kumeran interface in the MAC

  1074 	 * and in the PHY to avoid CRC errors.

  1075 	 */

  1076 	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);

  1077 	if (ret_val)

  1078 		return ret_val;

  1079 

  1080 	data |= GG82563_ICR_DIS_PADDING;

  1081 	ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);

  1082 	if (ret_val)

  1083 		return ret_val;

  1084 

  1085 	return 0;

  1086 }

  1087 

  1088 /**

  1089  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2

  1090  *  @hw: pointer to the HW structure

  1091  *

  1092  *  Essentially a wrapper for setting up all things "copper" related.

  1093  *  This is a function pointer entry point called by the mac module.

  1094  **/

  1095 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)

  1096 {

  1097 	u32 ctrl;

  1098 	s32 ret_val;

  1099 	u16 reg_data;

  1100 

  1101 	ctrl = er32(CTRL);

  1102 	ctrl |= E1000_CTRL_SLU;

  1103 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1104 	ew32(CTRL, ctrl);

  1105 

  1106 	/* Set the mac to wait the maximum time between each

  1107 	 * iteration and increase the max iterations when

  1108 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.

  1109 	 */

  1110 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),

  1111 	                                           0xFFFF);

  1112 	if (ret_val)

  1113 		return ret_val;

  1114 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),

  1115 	                                          &reg_data);

  1116 	if (ret_val)

  1117 		return ret_val;

  1118 	reg_data |= 0x3F;

  1119 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),

  1120 	                                           reg_data);

  1121 	if (ret_val)

  1122 		return ret_val;

  1123 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

  1124 				      E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,

  1125 				      &reg_data);

  1126 	if (ret_val)

  1127 		return ret_val;

  1128 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;

  1129 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

  1130 					E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,

  1131 					reg_data);

  1132 	if (ret_val)

  1133 		return ret_val;

  1134 

  1135 	ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);

  1136 	if (ret_val)