1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27  */

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000-3.8-ethercat.h"

    34 

    35 static s32 e1000_check_downshift(struct e1000_hw *hw);

    36 static s32 e1000_check_polarity(struct e1000_hw *hw,

    37 				e1000_rev_polarity *polarity);

    38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39 static void e1000_clear_vfta(struct e1000_hw *hw);

    40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41 					      bool link_up);

    42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46 				  u16 *max_length);

    47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48 static s32 e1000_id_led_init(struct e1000_hw *hw);

    49 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51 				  struct e1000_phy_info *phy_info);

    52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53 				  struct e1000_phy_info *phy_info);

    54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58 static void e1000_phy_init_script(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70 				  u16 words, u16 *data);

    71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72 					u16 words, u16 *data);

    73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78 				  u16 phy_data);

    79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80 				 u16 *phy_data);

    81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83 static void e1000_release_eeprom(struct e1000_hw *hw);

    84 static void e1000_standby_eeprom(struct e1000_hw *hw);

    85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89 				u16 *data);

    90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91 				 u16 *data);

    92 

    93 /* IGP cable length table */

    94 static const

    95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102 	    100,

   103 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104 	    110, 110,

   105 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106 	    120, 120

   107 };

   108 

   109 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110 static DEFINE_SPINLOCK(e1000_phy_lock);

   111 

   112 /**

   113  * e1000_set_phy_type - Set the phy type member in the hw struct.

   114  * @hw: Struct containing variables accessed by shared code

   115  */

   116 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   117 {

   118 	e_dbg("e1000_set_phy_type");

   119 

   120 	if (hw->mac_type == e1000_undefined)

   121 		return -E1000_ERR_PHY_TYPE;

   122 

   123 	switch (hw->phy_id) {

   124 	case M88E1000_E_PHY_ID:

   125 	case M88E1000_I_PHY_ID:

   126 	case M88E1011_I_PHY_ID:

   127 	case M88E1111_I_PHY_ID:

   128 	case M88E1118_E_PHY_ID:

   129 		hw->phy_type = e1000_phy_m88;

   130 		break;

   131 	case IGP01E1000_I_PHY_ID:

   132 		if (hw->mac_type == e1000_82541 ||

   133 		    hw->mac_type == e1000_82541_rev_2 ||

   134 		    hw->mac_type == e1000_82547 ||

   135 		    hw->mac_type == e1000_82547_rev_2)

   136 			hw->phy_type = e1000_phy_igp;

   137 		break;

   138 	case RTL8211B_PHY_ID:

   139 		hw->phy_type = e1000_phy_8211;

   140 		break;

   141 	case RTL8201N_PHY_ID:

   142 		hw->phy_type = e1000_phy_8201;

   143 		break;

   144 	default:

   145 		/* Should never have loaded on this device */

   146 		hw->phy_type = e1000_phy_undefined;

   147 		return -E1000_ERR_PHY_TYPE;

   148 	}

   149 

   150 	return E1000_SUCCESS;

   151 }

   152 

   153 /**

   154  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   155  * @hw: Struct containing variables accessed by shared code

   156  */

   157 static void e1000_phy_init_script(struct e1000_hw *hw)

   158 {

   159 	u32 ret_val __attribute__ ((unused));

   160 	u16 phy_saved_data;

   161 

   162 	e_dbg("e1000_phy_init_script");

   163 

   164 	if (hw->phy_init_script) {

   165 		msleep(20);

   166 

   167 		/* Save off the current value of register 0x2F5B to be restored at

   168 		 * the end of this routine. */

   169 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   170 

   171 		/* Disabled the PHY transmitter */

   172 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   173 		msleep(20);

   174 

   175 		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   176 		msleep(5);

   177 

   178 		switch (hw->mac_type) {

   179 		case e1000_82541:

   180 		case e1000_82547:

   181 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   182 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   183 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   184 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   185 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   186 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   187 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   188 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   189 			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   190 			break;

   191 

   192 		case e1000_82541_rev_2:

   193 		case e1000_82547_rev_2:

   194 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   195 			break;

   196 		default:

   197 			break;

   198 		}

   199 

   200 		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   201 		msleep(20);

   202 

   203 		/* Now enable the transmitter */

   204 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   205 

   206 		if (hw->mac_type == e1000_82547) {

   207 			u16 fused, fine, coarse;

   208 

   209 			/* Move to analog registers page */

   210 			e1000_read_phy_reg(hw,

   211 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   212 					   &fused);

   213 

   214 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   215 				e1000_read_phy_reg(hw,

   216 						   IGP01E1000_ANALOG_FUSE_STATUS,

   217 						   &fused);

   218 

   219 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   220 				coarse =

   221 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   222 

   223 				if (coarse >

   224 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   225 					coarse -=

   226 					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   227 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   228 				} else if (coarse ==

   229 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   230 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   231 

   232 				fused =

   233 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   234 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   235 				    (coarse &

   236 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   237 

   238 				e1000_write_phy_reg(hw,

   239 						    IGP01E1000_ANALOG_FUSE_CONTROL,

   240 						    fused);

   241 				e1000_write_phy_reg(hw,

   242 						    IGP01E1000_ANALOG_FUSE_BYPASS,

   243 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   244 			}

   245 		}

   246 	}

   247 }

   248 

   249 /**

   250  * e1000_set_mac_type - Set the mac type member in the hw struct.

   251  * @hw: Struct containing variables accessed by shared code

   252  */

   253 s32 e1000_set_mac_type(struct e1000_hw *hw)

   254 {

   255 	e_dbg("e1000_set_mac_type");

   256 

   257 	switch (hw->device_id) {

   258 	case E1000_DEV_ID_82542:

   259 		switch (hw->revision_id) {

   260 		case E1000_82542_2_0_REV_ID:

   261 			hw->mac_type = e1000_82542_rev2_0;

   262 			break;

   263 		case E1000_82542_2_1_REV_ID:

   264 			hw->mac_type = e1000_82542_rev2_1;

   265 			break;

   266 		default:

   267 			/* Invalid 82542 revision ID */

   268 			return -E1000_ERR_MAC_TYPE;

   269 		}

   270 		break;

   271 	case E1000_DEV_ID_82543GC_FIBER:

   272 	case E1000_DEV_ID_82543GC_COPPER:

   273 		hw->mac_type = e1000_82543;

   274 		break;

   275 	case E1000_DEV_ID_82544EI_COPPER:

   276 	case E1000_DEV_ID_82544EI_FIBER:

   277 	case E1000_DEV_ID_82544GC_COPPER:

   278 	case E1000_DEV_ID_82544GC_LOM:

   279 		hw->mac_type = e1000_82544;

   280 		break;

   281 	case E1000_DEV_ID_82540EM:

   282 	case E1000_DEV_ID_82540EM_LOM:

   283 	case E1000_DEV_ID_82540EP:

   284 	case E1000_DEV_ID_82540EP_LOM:

   285 	case E1000_DEV_ID_82540EP_LP:

   286 		hw->mac_type = e1000_82540;

   287 		break;

   288 	case E1000_DEV_ID_82545EM_COPPER:

   289 	case E1000_DEV_ID_82545EM_FIBER:

   290 		hw->mac_type = e1000_82545;

   291 		break;

   292 	case E1000_DEV_ID_82545GM_COPPER:

   293 	case E1000_DEV_ID_82545GM_FIBER:

   294 	case E1000_DEV_ID_82545GM_SERDES:

   295 		hw->mac_type = e1000_82545_rev_3;

   296 		break;

   297 	case E1000_DEV_ID_82546EB_COPPER:

   298 	case E1000_DEV_ID_82546EB_FIBER:

   299 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   300 		hw->mac_type = e1000_82546;

   301 		break;

   302 	case E1000_DEV_ID_82546GB_COPPER:

   303 	case E1000_DEV_ID_82546GB_FIBER:

   304 	case E1000_DEV_ID_82546GB_SERDES:

   305 	case E1000_DEV_ID_82546GB_PCIE:

   306 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   307 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   308 		hw->mac_type = e1000_82546_rev_3;

   309 		break;

   310 	case E1000_DEV_ID_82541EI:

   311 	case E1000_DEV_ID_82541EI_MOBILE:

   312 	case E1000_DEV_ID_82541ER_LOM:

   313 		hw->mac_type = e1000_82541;

   314 		break;

   315 	case E1000_DEV_ID_82541ER:

   316 	case E1000_DEV_ID_82541GI:

   317 	case E1000_DEV_ID_82541GI_LF:

   318 	case E1000_DEV_ID_82541GI_MOBILE:

   319 		hw->mac_type = e1000_82541_rev_2;

   320 		break;

   321 	case E1000_DEV_ID_82547EI:

   322 	case E1000_DEV_ID_82547EI_MOBILE:

   323 		hw->mac_type = e1000_82547;

   324 		break;

   325 	case E1000_DEV_ID_82547GI:

   326 		hw->mac_type = e1000_82547_rev_2;

   327 		break;

   328 	case E1000_DEV_ID_INTEL_CE4100_GBE:

   329 		hw->mac_type = e1000_ce4100;

   330 		break;

   331 	default:

   332 		/* Should never have loaded on this device */

   333 		return -E1000_ERR_MAC_TYPE;

   334 	}

   335 

   336 	switch (hw->mac_type) {

   337 	case e1000_82541:

   338 	case e1000_82547:

   339 	case e1000_82541_rev_2:

   340 	case e1000_82547_rev_2:

   341 		hw->asf_firmware_present = true;

   342 		break;

   343 	default:

   344 		break;

   345 	}

   346 

   347 	/* The 82543 chip does not count tx_carrier_errors properly in

   348 	 * FD mode

   349 	 */

   350 	if (hw->mac_type == e1000_82543)

   351 		hw->bad_tx_carr_stats_fd = true;

   352 

   353 	if (hw->mac_type > e1000_82544)

   354 		hw->has_smbus = true;

   355 

   356 	return E1000_SUCCESS;

   357 }

   358 

   359 /**

   360  * e1000_set_media_type - Set media type and TBI compatibility.

   361  * @hw: Struct containing variables accessed by shared code

   362  */

   363 void e1000_set_media_type(struct e1000_hw *hw)

   364 {

   365 	u32 status;

   366 

   367 	e_dbg("e1000_set_media_type");

   368 

   369 	if (hw->mac_type != e1000_82543) {

   370 		/* tbi_compatibility is only valid on 82543 */

   371 		hw->tbi_compatibility_en = false;

   372 	}

   373 

   374 	switch (hw->device_id) {

   375 	case E1000_DEV_ID_82545GM_SERDES:

   376 	case E1000_DEV_ID_82546GB_SERDES:

   377 		hw->media_type = e1000_media_type_internal_serdes;

   378 		break;

   379 	default:

   380 		switch (hw->mac_type) {

   381 		case e1000_82542_rev2_0:

   382 		case e1000_82542_rev2_1:

   383 			hw->media_type = e1000_media_type_fiber;

   384 			break;

   385 		case e1000_ce4100:

   386 			hw->media_type = e1000_media_type_copper;

   387 			break;

   388 		default:

   389 			status = er32(STATUS);

   390 			if (status & E1000_STATUS_TBIMODE) {

   391 				hw->media_type = e1000_media_type_fiber;

   392 				/* tbi_compatibility not valid on fiber */

   393 				hw->tbi_compatibility_en = false;

   394 			} else {

   395 				hw->media_type = e1000_media_type_copper;

   396 			}

   397 			break;

   398 		}

   399 	}

   400 }

   401 

   402 /**

   403  * e1000_reset_hw - reset the hardware completely

   404  * @hw: Struct containing variables accessed by shared code

   405  *

   406  * Reset the transmit and receive units; mask and clear all interrupts.

   407  */

   408 s32 e1000_reset_hw(struct e1000_hw *hw)

   409 {

   410 	u32 ctrl;

   411 	u32 ctrl_ext;

   412 	u32 icr __attribute__ ((unused));

   413 	u32 manc;

   414 	u32 led_ctrl;

   415 	s32 ret_val;

   416 

   417 	e_dbg("e1000_reset_hw");

   418 

   419 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   420 	if (hw->mac_type == e1000_82542_rev2_0) {

   421 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   422 		e1000_pci_clear_mwi(hw);

   423 	}

   424 

   425 	/* Clear interrupt mask to stop board from generating interrupts */

   426 	e_dbg("Masking off all interrupts\n");

   427 	ew32(IMC, 0xffffffff);

   428 

   429 	/* Disable the Transmit and Receive units.  Then delay to allow

   430 	 * any pending transactions to complete before we hit the MAC with

   431 	 * the global reset.

   432 	 */

   433 	ew32(RCTL, 0);

   434 	ew32(TCTL, E1000_TCTL_PSP);

   435 	E1000_WRITE_FLUSH();

   436 

   437 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   438 	hw->tbi_compatibility_on = false;

   439 

   440 	/* Delay to allow any outstanding PCI transactions to complete before

   441 	 * resetting the device

   442 	 */

   443 	msleep(10);

   444 

   445 	ctrl = er32(CTRL);

   446 

   447 	/* Must reset the PHY before resetting the MAC */

   448 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   449 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   450 		E1000_WRITE_FLUSH();

   451 		msleep(5);

   452 	}

   453 

   454 	/* Issue a global reset to the MAC.  This will reset the chip's

   455 	 * transmit, receive, DMA, and link units.  It will not effect

   456 	 * the current PCI configuration.  The global reset bit is self-

   457 	 * clearing, and should clear within a microsecond.

   458 	 */

   459 	e_dbg("Issuing a global reset to MAC\n");

   460 

   461 	switch (hw->mac_type) {

   462 	case e1000_82544:

   463 	case e1000_82540:

   464 	case e1000_82545:

   465 	case e1000_82546:

   466 	case e1000_82541:

   467 	case e1000_82541_rev_2:

   468 		/* These controllers can't ack the 64-bit write when issuing the

   469 		 * reset, so use IO-mapping as a workaround to issue the reset */

   470 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   471 		break;

   472 	case e1000_82545_rev_3:

   473 	case e1000_82546_rev_3:

   474 		/* Reset is performed on a shadow of the control register */

   475 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   476 		break;

   477 	case e1000_ce4100:

   478 	default:

   479 		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   480 		break;

   481 	}

   482 

   483 	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   484 	 * device.  Later controllers reload the EEPROM automatically, so just wait

   485 	 * for reload to complete.

   486 	 */

   487 	switch (hw->mac_type) {

   488 	case e1000_82542_rev2_0:

   489 	case e1000_82542_rev2_1:

   490 	case e1000_82543:

   491 	case e1000_82544:

   492 		/* Wait for reset to complete */

   493 		udelay(10);

   494 		ctrl_ext = er32(CTRL_EXT);

   495 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   496 		ew32(CTRL_EXT, ctrl_ext);

   497 		E1000_WRITE_FLUSH();

   498 		/* Wait for EEPROM reload */

   499 		msleep(2);

   500 		break;

   501 	case e1000_82541:

   502 	case e1000_82541_rev_2:

   503 	case e1000_82547:

   504 	case e1000_82547_rev_2:

   505 		/* Wait for EEPROM reload */

   506 		msleep(20);

   507 		break;

   508 	default:

   509 		/* Auto read done will delay 5ms or poll based on mac type */

   510 		ret_val = e1000_get_auto_rd_done(hw);

   511 		if (ret_val)

   512 			return ret_val;

   513 		break;

   514 	}

   515 

   516 	/* Disable HW ARPs on ASF enabled adapters */

   517 	if (hw->mac_type >= e1000_82540) {

   518 		manc = er32(MANC);

   519 		manc &= ~(E1000_MANC_ARP_EN);

   520 		ew32(MANC, manc);

   521 	}

   522 

   523 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   524 		e1000_phy_init_script(hw);

   525 

   526 		/* Configure activity LED after PHY reset */

   527 		led_ctrl = er32(LEDCTL);

   528 		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   529 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   530 		ew32(LEDCTL, led_ctrl);

   531 	}

   532 

   533 	/* Clear interrupt mask to stop board from generating interrupts */

   534 	e_dbg("Masking off all interrupts\n");

   535 	ew32(IMC, 0xffffffff);

   536 

   537 	/* Clear any pending interrupt events. */

   538 	icr = er32(ICR);

   539 

   540 	/* If MWI was previously enabled, reenable it. */

   541 	if (hw->mac_type == e1000_82542_rev2_0) {

   542 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   543 			e1000_pci_set_mwi(hw);

   544 	}

   545 

   546 	return E1000_SUCCESS;

   547 }

   548 

   549 /**

   550  * e1000_init_hw - Performs basic configuration of the adapter.

   551  * @hw: Struct containing variables accessed by shared code

   552  *

   553  * Assumes that the controller has previously been reset and is in a

   554  * post-reset uninitialized state. Initializes the receive address registers,

   555  * multicast table, and VLAN filter table. Calls routines to setup link

   556  * configuration and flow control settings. Clears all on-chip counters. Leaves

   557  * the transmit and receive units disabled and uninitialized.

   558  */

   559 s32 e1000_init_hw(struct e1000_hw *hw)

   560 {

   561 	u32 ctrl;

   562 	u32 i;

   563 	s32 ret_val;

   564 	u32 mta_size;

   565 	u32 ctrl_ext;

   566 

   567 	e_dbg("e1000_init_hw");

   568 

   569 	/* Initialize Identification LED */

   570 	ret_val = e1000_id_led_init(hw);

   571 	if (ret_val) {

   572 		e_dbg("Error Initializing Identification LED\n");

   573 		return ret_val;

   574 	}

   575 

   576 	/* Set the media type and TBI compatibility */

   577 	e1000_set_media_type(hw);

   578 

   579 	/* Disabling VLAN filtering. */

   580 	e_dbg("Initializing the IEEE VLAN\n");

   581 	if (hw->mac_type < e1000_82545_rev_3)

   582 		ew32(VET, 0);

   583 	e1000_clear_vfta(hw);

   584 

   585 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   586 	if (hw->mac_type == e1000_82542_rev2_0) {

   587 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   588 		e1000_pci_clear_mwi(hw);

   589 		ew32(RCTL, E1000_RCTL_RST);

   590 		E1000_WRITE_FLUSH();

   591 		msleep(5);

   592 	}

   593 

   594 	/* Setup the receive address. This involves initializing all of the Receive

   595 	 * Address Registers (RARs 0 - 15).

   596 	 */

   597 	e1000_init_rx_addrs(hw);

   598 

   599 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   600 	if (hw->mac_type == e1000_82542_rev2_0) {

   601 		ew32(RCTL, 0);

   602 		E1000_WRITE_FLUSH();

   603 		msleep(1);

   604 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   605 			e1000_pci_set_mwi(hw);

   606 	}

   607 

   608 	/* Zero out the Multicast HASH table */

   609 	e_dbg("Zeroing the MTA\n");

   610 	mta_size = E1000_MC_TBL_SIZE;

   611 	for (i = 0; i < mta_size; i++) {

   612 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   613 		/* use write flush to prevent Memory Write Block (MWB) from

   614 		 * occurring when accessing our register space */

   615 		E1000_WRITE_FLUSH();

   616 	}

   617 

   618 	/* Set the PCI priority bit correctly in the CTRL register.  This

   619 	 * determines if the adapter gives priority to receives, or if it

   620 	 * gives equal priority to transmits and receives.  Valid only on

   621 	 * 82542 and 82543 silicon.

   622 	 */

   623 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   624 		ctrl = er32(CTRL);

   625 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   626 	}

   627 

   628 	switch (hw->mac_type) {

   629 	case e1000_82545_rev_3:

   630 	case e1000_82546_rev_3:

   631 		break;

   632 	default:

   633 		/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   634 		if (hw->bus_type == e1000_bus_type_pcix

   635 		    && e1000_pcix_get_mmrbc(hw) > 2048)

   636 			e1000_pcix_set_mmrbc(hw, 2048);

   637 		break;

   638 	}

   639 

   640 	/* Call a subroutine to configure the link and setup flow control. */

   641 	ret_val = e1000_setup_link(hw);

   642 

   643 	/* Set the transmit descriptor write-back policy */

   644 	if (hw->mac_type > e1000_82544) {

   645 		ctrl = er32(TXDCTL);

   646 		ctrl =

   647 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |

   648 		    E1000_TXDCTL_FULL_TX_DESC_WB;

   649 		ew32(TXDCTL, ctrl);

   650 	}

   651 

   652 	/* Clear all of the statistics registers (clear on read).  It is

   653 	 * important that we do this after we have tried to establish link

   654 	 * because the symbol error count will increment wildly if there

   655 	 * is no link.

   656 	 */

   657 	e1000_clear_hw_cntrs(hw);

   658 

   659 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   660 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   661 		ctrl_ext = er32(CTRL_EXT);

   662 		/* Relaxed ordering must be disabled to avoid a parity

   663 		 * error crash in a PCI slot. */

   664 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   665 		ew32(CTRL_EXT, ctrl_ext);

   666 	}

   667 

   668 	return ret_val;

   669 }

   670 

   671 /**

   672  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.

   673  * @hw: Struct containing variables accessed by shared code.

   674  */

   675 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   676 {

   677 	u16 eeprom_data;

   678 	s32 ret_val;

   679 

   680 	e_dbg("e1000_adjust_serdes_amplitude");

   681 

   682 	if (hw->media_type != e1000_media_type_internal_serdes)

   683 		return E1000_SUCCESS;

   684 

   685 	switch (hw->mac_type) {

   686 	case e1000_82545_rev_3:

   687 	case e1000_82546_rev_3:

   688 		break;

   689 	default:

   690 		return E1000_SUCCESS;

   691 	}

   692 

   693 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,

   694 	                            &eeprom_data);

   695 	if (ret_val) {

   696 		return ret_val;

   697 	}

   698 

   699 	if (eeprom_data != EEPROM_RESERVED_WORD) {

   700 		/* Adjust SERDES output amplitude only. */

   701 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   702 		ret_val =

   703 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   704 		if (ret_val)

   705 			return ret_val;

   706 	}

   707 

   708 	return E1000_SUCCESS;

   709 }

   710 

   711 /**

   712  * e1000_setup_link - Configures flow control and link settings.

   713  * @hw: Struct containing variables accessed by shared code

   714  *

   715  * Determines which flow control settings to use. Calls the appropriate media-

   716  * specific link configuration function. Configures the flow control settings.

   717  * Assuming the adapter has a valid link partner, a valid link should be

   718  * established. Assumes the hardware has previously been reset and the

   719  * transmitter and receiver are not enabled.

   720  */

   721 s32 e1000_setup_link(struct e1000_hw *hw)

   722 {

   723 	u32 ctrl_ext;

   724 	s32 ret_val;

   725 	u16 eeprom_data;

   726 

   727 	e_dbg("e1000_setup_link");

   728 

   729 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   730 	 * that determine the hardware's default PAUSE (flow control) mode,

   731 	 * a bit that determines whether the HW defaults to enabling or

   732 	 * disabling auto-negotiation, and the direction of the

   733 	 * SW defined pins. If there is no SW over-ride of the flow

   734 	 * control setting, then the variable hw->fc will

   735 	 * be initialized based on a value in the EEPROM.

   736 	 */

   737 	if (hw->fc == E1000_FC_DEFAULT) {

   738 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   739 					    1, &eeprom_data);

   740 		if (ret_val) {

   741 			e_dbg("EEPROM Read Error\n");

   742 			return -E1000_ERR_EEPROM;

   743 		}

   744 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   745 			hw->fc = E1000_FC_NONE;

   746 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   747 			 EEPROM_WORD0F_ASM_DIR)

   748 			hw->fc = E1000_FC_TX_PAUSE;

   749 		else

   750 			hw->fc = E1000_FC_FULL;

   751 	}

   752 

   753 	/* We want to save off the original Flow Control configuration just

   754 	 * in case we get disconnected and then reconnected into a different

   755 	 * hub or switch with different Flow Control capabilities.

   756 	 */

   757 	if (hw->mac_type == e1000_82542_rev2_0)

   758 		hw->fc &= (~E1000_FC_TX_PAUSE);

   759 

   760 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   761 		hw->fc &= (~E1000_FC_RX_PAUSE);

   762 

   763 	hw->original_fc = hw->fc;

   764 

   765 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);

   766 

   767 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial

   768 	 * polarity value for the SW controlled pins, and setup the

   769 	 * Extended Device Control reg with that info.

   770 	 * This is needed because one of the SW controlled pins is used for

   771 	 * signal detection.  So this should be done before e1000_setup_pcs_link()

   772 	 * or e1000_phy_setup() is called.

   773 	 */

   774 	if (hw->mac_type == e1000_82543) {

   775 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   776 					    1, &eeprom_data);

   777 		if (ret_val) {

   778 			e_dbg("EEPROM Read Error\n");

   779 			return -E1000_ERR_EEPROM;

   780 		}

   781 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   782 			    SWDPIO__EXT_SHIFT);

   783 		ew32(CTRL_EXT, ctrl_ext);

   784 	}

   785 

   786 	/* Call the necessary subroutine to configure the link. */

   787 	ret_val = (hw->media_type == e1000_media_type_copper) ?

   788 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);

   789 

   790 	/* Initialize the flow control address, type, and PAUSE timer

   791 	 * registers to their default values.  This is done even if flow

   792 	 * control is disabled, because it does not hurt anything to

   793 	 * initialize these registers.

   794 	 */

   795 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   796 

   797 	ew32(FCT, FLOW_CONTROL_TYPE);

   798 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   799 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   800 

   801 	ew32(FCTTV, hw->fc_pause_time);

   802 

   803 	/* Set the flow control receive threshold registers.  Normally,

   804 	 * these registers will be set to a default threshold that may be

   805 	 * adjusted later by the driver's runtime code.  However, if the

   806 	 * ability to transmit pause frames in not enabled, then these

   807 	 * registers will be set to 0.

   808 	 */

   809 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {

   810 		ew32(FCRTL, 0);

   811 		ew32(FCRTH, 0);

   812 	} else {

   813 		/* We need to set up the Receive Threshold high and low water marks

   814 		 * as well as (optionally) enabling the transmission of XON frames.

   815 		 */

   816 		if (hw->fc_send_xon) {

   817 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   818 			ew32(FCRTH, hw->fc_high_water);

   819 		} else {

   820 			ew32(FCRTL, hw->fc_low_water);

   821 			ew32(FCRTH, hw->fc_high_water);

   822 		}

   823 	}

   824 	return ret_val;

   825 }

   826 

   827 /**

   828  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link

   829  * @hw: Struct containing variables accessed by shared code

   830  *

   831  * Manipulates Physical Coding Sublayer functions in order to configure

   832  * link. Assumes the hardware has been previously reset and the transmitter

   833  * and receiver are not enabled.

   834  */

   835 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   836 {

   837 	u32 ctrl;

   838 	u32 status;

   839 	u32 txcw = 0;

   840 	u32 i;

   841 	u32 signal = 0;

   842 	s32 ret_val;

   843 

   844 	e_dbg("e1000_setup_fiber_serdes_link");

   845 

   846 	/* On adapters with a MAC newer than 82544, SWDP 1 will be

   847 	 * set when the optics detect a signal. On older adapters, it will be

   848 	 * cleared when there is a signal.  This applies to fiber media only.

   849 	 * If we're on serdes media, adjust the output amplitude to value

   850 	 * set in the EEPROM.

   851 	 */

   852 	ctrl = er32(CTRL);

   853 	if (hw->media_type == e1000_media_type_fiber)

   854 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   855 

   856 	ret_val = e1000_adjust_serdes_amplitude(hw);

   857 	if (ret_val)

   858 		return ret_val;

   859 

   860 	/* Take the link out of reset */

   861 	ctrl &= ~(E1000_CTRL_LRST);

   862 

   863 	/* Adjust VCO speed to improve BER performance */

   864 	ret_val = e1000_set_vco_speed(hw);

   865 	if (ret_val)

   866 		return ret_val;

   867 

   868 	e1000_config_collision_dist(hw);

   869 

   870 	/* Check for a software override of the flow control settings, and setup

   871 	 * the device accordingly.  If auto-negotiation is enabled, then software

   872 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit

   873 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if

   874 	 * auto-negotiation is disabled, then software will have to manually

   875 	 * configure the two flow control enable bits in the CTRL register.

   876 	 *

   877 	 * The possible values of the "fc" parameter are:

   878 	 *      0:  Flow control is completely disabled

   879 	 *      1:  Rx flow control is enabled (we can receive pause frames, but

   880 	 *          not send pause frames).

   881 	 *      2:  Tx flow control is enabled (we can send pause frames but we do

   882 	 *          not support receiving pause frames).

   883 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.

   884 	 */

   885 	switch (hw->fc) {

   886 	case E1000_FC_NONE:

   887 		/* Flow control is completely disabled by a software over-ride. */

   888 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   889 		break;

   890 	case E1000_FC_RX_PAUSE:

   891 		/* RX Flow control is enabled and TX Flow control is disabled by a

   892 		 * software over-ride. Since there really isn't a way to advertise

   893 		 * that we are capable of RX Pause ONLY, we will advertise that we

   894 		 * support both symmetric and asymmetric RX PAUSE. Later, we will

   895 		 *  disable the adapter's ability to send PAUSE frames.

   896 		 */

   897 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   898 		break;

   899 	case E1000_FC_TX_PAUSE:

   900 		/* TX Flow control is enabled, and RX Flow control is disabled, by a

   901 		 * software over-ride.

   902 		 */

   903 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   904 		break;

   905 	case E1000_FC_FULL:

   906 		/* Flow control (both RX and TX) is enabled by a software over-ride. */

   907 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   908 		break;

   909 	default:

   910 		e_dbg("Flow control param set incorrectly\n");

   911 		return -E1000_ERR_CONFIG;

   912 		break;

   913 	}

   914 

   915 	/* Since auto-negotiation is enabled, take the link out of reset (the link

   916 	 * will be in reset, because we previously reset the chip). This will

   917 	 * restart auto-negotiation.  If auto-negotiation is successful then the

   918 	 * link-up status bit will be set and the flow control enable bits (RFCE

   919 	 * and TFCE) will be set according to their negotiated value.

   920 	 */

   921 	e_dbg("Auto-negotiation enabled\n");

   922 

   923 	ew32(TXCW, txcw);

   924 	ew32(CTRL, ctrl);

   925 	E1000_WRITE_FLUSH();

   926 

   927 	hw->txcw = txcw;

   928 	msleep(1);

   929 

   930 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"

   931 	 * indication in the Device Status Register.  Time-out if a link isn't

   932 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in

   933 	 * less than 500 milliseconds even if the other end is doing it in SW).

   934 	 * For internal serdes, we just assume a signal is present, then poll.

   935 	 */

   936 	if (hw->media_type == e1000_media_type_internal_serdes ||

   937 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   938 		e_dbg("Looking for Link\n");

   939 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   940 			msleep(10);

   941 			status = er32(STATUS);

   942 			if (status & E1000_STATUS_LU)

   943 				break;

   944 		}

   945 		if (i == (LINK_UP_TIMEOUT / 10)) {

   946 			e_dbg("Never got a valid link from auto-neg!!!\n");

   947 			hw->autoneg_failed = 1;

   948 			/* AutoNeg failed to achieve a link, so we'll call

   949 			 * e1000_check_for_link. This routine will force the link up if

   950 			 * we detect a signal. This will allow us to communicate with

   951 			 * non-autonegotiating link partners.

   952 			 */

   953 			ret_val = e1000_check_for_link(hw);

   954 			if (ret_val) {

   955 				e_dbg("Error while checking for link\n");

   956 				return ret_val;

   957 			}

   958 			hw->autoneg_failed = 0;

   959 		} else {

   960 			hw->autoneg_failed = 0;

   961 			e_dbg("Valid Link Found\n");

   962 		}

   963 	} else {

   964 		e_dbg("No Signal Detected\n");

   965 	}

   966 	return E1000_SUCCESS;

   967 }

   968 

   969 /**

   970  * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.

   971  * @hw: Struct containing variables accessed by shared code

   972  *

   973  * Commits changes to PHY configuration by calling e1000_phy_reset().

   974  */

   975 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)

   976 {

   977 	s32 ret_val;

   978 

   979 	/* SW reset the PHY so all changes take effect */

   980 	ret_val = e1000_phy_reset(hw);

   981 	if (ret_val) {

   982 		e_dbg("Error Resetting the PHY\n");

   983 		return ret_val;

   984 	}

   985 

   986 	return E1000_SUCCESS;

   987 }

   988 

   989 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)

   990 {

   991 	s32 ret_val;

   992 	u32 ctrl_aux;

   993 

   994 	switch (hw->phy_type) {

   995 	case e1000_phy_8211:

   996 		ret_val = e1000_copper_link_rtl_setup(hw);

   997 		if (ret_val) {

   998 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

   999 			return ret_val;

  1000 		}

  1001 		break;

  1002 	case e1000_phy_8201:

  1003 		/* Set RMII mode */

  1004 		ctrl_aux = er32(CTL_AUX);

  1005 		ctrl_aux |= E1000_CTL_AUX_RMII;

  1006 		ew32(CTL_AUX, ctrl_aux);

  1007 		E1000_WRITE_FLUSH();

  1008 

  1009 		/* Disable the J/K bits required for receive */

  1010 		ctrl_aux = er32(CTL_AUX);

  1011 		ctrl_aux |= 0x4;

  1012 		ctrl_aux &= ~0x2;

  1013 		ew32(CTL_AUX, ctrl_aux);

  1014 		E1000_WRITE_FLUSH();

  1015 		ret_val = e1000_copper_link_rtl_setup(hw);

  1016 

  1017 		if (ret_val) {

  1018 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

  1019 			return ret_val;

  1020 		}

  1021 		break;

  1022 	default:

  1023 		e_dbg("Error Resetting the PHY\n");

  1024 		return E1000_ERR_PHY_TYPE;

  1025 	}

  1026 

  1027 	return E1000_SUCCESS;

  1028 }

  1029 

  1030 /**

  1031  * e1000_copper_link_preconfig - early configuration for copper

  1032  * @hw: Struct containing variables accessed by shared code

  1033  *

  1034  * Make sure we have a valid PHY and change PHY mode before link setup.

  1035  */

  1036 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)

  1037 {

  1038 	u32 ctrl;

  1039 	s32 ret_val;

  1040 	u16 phy_data;

  1041 

  1042 	e_dbg("e1000_copper_link_preconfig");

  1043 

  1044 	ctrl = er32(CTRL);

  1045 	/* With 82543, we need to force speed and duplex on the MAC equal to what

  1046 	 * the PHY speed and duplex configuration is. In addition, we need to

  1047 	 * perform a hardware reset on the PHY to take it out of reset.

  1048 	 */

  1049 	if (hw->mac_type > e1000_82543) {

  1050 		ctrl |= E1000_CTRL_SLU;

  1051 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1052 		ew32(CTRL, ctrl);

  1053 	} else {

  1054 		ctrl |=

  1055 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

  1056 		ew32(CTRL, ctrl);

  1057 		ret_val = e1000_phy_hw_reset(hw);

  1058 		if (ret_val)

  1059 			return ret_val;

  1060 	}

  1061 

  1062 	/* Make sure we have a valid PHY */

  1063 	ret_val = e1000_detect_gig_phy(hw);

  1064 	if (ret_val) {

  1065 		e_dbg("Error, did not detect valid phy.\n");

  1066 		return ret_val;

  1067 	}

  1068 	e_dbg("Phy ID = %x\n", hw->phy_id);

  1069 

  1070 	/* Set PHY to class A mode (if necessary) */

  1071 	ret_val = e1000_set_phy_mode(hw);

  1072 	if (ret_val)

  1073 		return ret_val;

  1074 

  1075 	if ((hw->mac_type == e1000_82545_rev_3) ||

  1076 	    (hw->mac_type == e1000_82546_rev_3)) {

  1077 		ret_val =

  1078 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1079 		phy_data |= 0x00000008;

  1080 		ret_val =

  1081 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1082 	}

  1083 

  1084 	if (hw->mac_type <= e1000_82543 ||

  1085 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1086 	    hw->mac_type == e1000_82541_rev_2

  1087 	    || hw->mac_type == e1000_82547_rev_2)

  1088 		hw->phy_reset_disable = false;

  1089 

  1090 	return E1000_SUCCESS;

  1091 }

  1092 

  1093 /**

  1094  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.

  1095  * @hw: Struct containing variables accessed by shared code

  1096  */

  1097 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1098 {

  1099 	u32 led_ctrl;

  1100 	s32 ret_val;

  1101 	u16 phy_data;

  1102 

  1103 	e_dbg("e1000_copper_link_igp_setup");

  1104 

  1105 	if (hw->phy_reset_disable)

  1106 		return E1000_SUCCESS;

  1107 

  1108 	ret_val = e1000_phy_reset(hw);

  1109 	if (ret_val) {

  1110 		e_dbg("Error Resetting the PHY\n");

  1111 		return ret_val;

  1112 	}

  1113 

  1114 	/* Wait 15ms for MAC to configure PHY from eeprom settings */

  1115 	msleep(15);

  1116 	/* Configure activity LED after PHY reset */

  1117 	led_ctrl = er32(LEDCTL);

  1118 	led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1119 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1120 	ew32(LEDCTL, led_ctrl);

  1121 

  1122 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */

  1123 	if (hw->phy_type == e1000_phy_igp) {

  1124 		/* disable lplu d3 during driver init */

  1125 		ret_val = e1000_set_d3_lplu_state(hw, false);

  1126 		if (ret_val) {

  1127 			e_dbg("Error Disabling LPLU D3\n");

  1128 			return ret_val;

  1129 		}

  1130 	}

  1131 

  1132 	/* Configure mdi-mdix settings */

  1133 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

  1134 	if (ret_val)

  1135 		return ret_val;

  1136