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1 /****************************************************************************** |
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2 * |
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3 * $Id$ |
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4 * |
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5 * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH |
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6 * |
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7 * This file is part of the IgH EtherCAT Master. |
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8 * |
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9 * The IgH EtherCAT Master is free software; you can redistribute it and/or |
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10 * modify it under the terms of the GNU General Public License version 2, as |
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11 * published by the Free Software Foundation. |
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12 * |
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13 * The IgH EtherCAT Master is distributed in the hope that it will be useful, |
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General |
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16 * Public License for more details. |
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17 * |
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18 * You should have received a copy of the GNU General Public License along |
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19 * with the IgH EtherCAT Master; if not, write to the Free Software |
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20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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21 * |
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22 * --- |
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23 * |
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24 * The license mentioned above concerns the source code only. Using the |
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25 * EtherCAT technology and brand is only permitted in compliance with the |
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26 * industrial property and similar rights of Beckhoff Automation GmbH. |
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27 * |
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28 * vim: noexpandtab |
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29 * |
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30 *****************************************************************************/ |
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31 |
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32 /** |
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33 \file |
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34 EtherCAT driver for RTL8139-compatible NICs. |
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35 */ |
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36 |
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37 /*****************************************************************************/ |
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38 |
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39 /* |
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40 Former documentation: |
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41 |
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42 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. |
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43 |
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44 Maintained by Jeff Garzik <jgarzik@pobox.com> |
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45 Copyright 2000-2002 Jeff Garzik |
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46 |
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47 Much code comes from Donald Becker's rtl8139.c driver, |
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48 versions 1.13 and older. This driver was originally based |
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49 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: |
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50 |
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51 -----<snip>----- |
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52 |
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53 Written 1997-2001 by Donald Becker. |
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54 This software may be used and distributed according to the |
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55 terms of the GNU General Public License (GPL), incorporated |
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56 herein by reference. Drivers based on or derived from this |
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57 code fall under the GPL and must retain the authorship, |
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58 copyright and license notice. This file is not a complete |
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59 program and may only be used when the entire operating |
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60 system is licensed under the GPL. |
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61 |
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62 This driver is for boards based on the RTL8129 and RTL8139 |
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63 PCI ethernet chips. |
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64 |
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65 The author may be reached as becker@scyld.com, or C/O Scyld |
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66 Computing Corporation 410 Severn Ave., Suite 210 Annapolis |
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67 MD 21403 |
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68 |
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69 Support and updates available at |
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70 http://www.scyld.com/network/rtl8139.html |
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71 |
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72 Twister-tuning table provided by Kinston |
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73 <shangh@realtek.com.tw>. |
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74 |
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75 -----<snip>----- |
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76 |
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77 This software may be used and distributed according to the terms |
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78 of the GNU General Public License, incorporated herein by reference. |
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79 |
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80 Contributors: |
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81 |
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82 Donald Becker - he wrote the original driver, kudos to him! |
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83 (but please don't e-mail him for support, this isn't his driver) |
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84 |
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85 Tigran Aivazian - bug fixes, skbuff free cleanup |
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86 |
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87 Martin Mares - suggestions for PCI cleanup |
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88 |
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89 David S. Miller - PCI DMA and softnet updates |
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90 |
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91 Ernst Gill - fixes ported from BSD driver |
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92 |
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93 Daniel Kobras - identified specific locations of |
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94 posted MMIO write bugginess |
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95 |
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96 Gerard Sharp - bug fix, testing and feedback |
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97 |
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98 David Ford - Rx ring wrap fix |
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99 |
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100 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me |
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101 to find and fix a crucial bug on older chipsets. |
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102 |
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103 Donald Becker/Chris Butterworth/Marcus Westergren - |
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104 Noticed various Rx packet size-related buglets. |
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105 |
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106 Santiago Garcia Mantinan - testing and feedback |
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107 |
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108 Jens David - 2.2.x kernel backports |
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109 |
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110 Martin Dennett - incredibly helpful insight on undocumented |
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111 features of the 8139 chips |
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112 |
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113 Jean-Jacques Michel - bug fix |
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114 |
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115 Tobias Ringström - Rx interrupt status checking suggestion |
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116 |
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117 Andrew Morton - Clear blocked signals, avoid |
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118 buffer overrun setting current->comm. |
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119 |
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120 Kalle Olavi Niemitalo - Wake-on-LAN ioctls |
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121 |
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122 Robert Kuebel - Save kernel thread from dying on any signal. |
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123 |
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124 Submitting bug reports: |
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125 |
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126 "rtl8139-diag -mmmaaavvveefN" output |
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127 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log |
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128 |
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129 */ |
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130 |
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131 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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132 |
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133 #define DRV_NAME "ec_8139too" |
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134 #define DRV_VERSION "0.9.28" |
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135 |
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136 |
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137 #include <linux/module.h> |
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138 #include <linux/kernel.h> |
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139 #include <linux/compiler.h> |
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140 #include <linux/pci.h> |
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141 #include <linux/init.h> |
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142 #include <linux/interrupt.h> |
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143 #include <linux/netdevice.h> |
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144 #include <linux/etherdevice.h> |
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145 #include <linux/rtnetlink.h> |
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146 #include <linux/delay.h> |
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147 #include <linux/ethtool.h> |
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148 #include <linux/mii.h> |
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149 #include <linux/completion.h> |
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150 #include <linux/crc32.h> |
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151 #include <linux/io.h> |
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152 #include <linux/uaccess.h> |
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153 #include <linux/gfp.h> |
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154 #include <asm/irq.h> |
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155 |
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156 #include "../globals.h" |
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157 #include "ecdev.h" |
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158 |
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159 #define RTL8139_DRIVER_NAME DRV_NAME \ |
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160 " EtherCAT-capable Fast Ethernet driver " \ |
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161 DRV_VERSION ", master " EC_MASTER_VERSION |
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162 |
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163 #define PFX DRV_NAME ": " |
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164 |
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165 /* Default Message level */ |
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166 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
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167 NETIF_MSG_PROBE | \ |
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168 NETIF_MSG_LINK) |
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169 |
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170 |
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171 /* define to 1, 2 or 3 to enable copious debugging info */ |
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172 #define RTL8139_DEBUG 0 |
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173 |
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174 /* define to 1 to disable lightweight runtime debugging checks */ |
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175 #undef RTL8139_NDEBUG |
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176 |
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177 |
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178 #ifdef RTL8139_NDEBUG |
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179 # define assert(expr) do {} while (0) |
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180 #else |
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181 # define assert(expr) \ |
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182 if (unlikely(!(expr))) { \ |
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183 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ |
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184 #expr, __FILE__, __func__, __LINE__); \ |
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185 } |
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186 #endif |
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187 |
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188 |
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189 /* A few user-configurable values. */ |
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190 /* media options */ |
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191 #define MAX_UNITS 8 |
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192 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; |
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193 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; |
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194 |
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195 /* Whether to use MMIO or PIO. Default to MMIO. */ |
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196 #ifdef CONFIG_8139TOO_PIO |
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197 static bool use_io = true; |
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198 #else |
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199 static bool use_io = false; |
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200 #endif |
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201 |
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202 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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203 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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204 static int multicast_filter_limit = 32; |
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205 |
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206 /* bitmapped message enable number */ |
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207 static int debug = -1; |
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208 |
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209 /* |
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210 * Receive ring size |
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211 * Warning: 64K ring has hardware issues and may lock up. |
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212 */ |
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213 #if defined(CONFIG_SH_DREAMCAST) |
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214 #define RX_BUF_IDX 0 /* 8K ring */ |
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215 #else |
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216 #define RX_BUF_IDX 2 /* 32K ring */ |
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217 #endif |
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218 #define RX_BUF_LEN (8192 << RX_BUF_IDX) |
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219 #define RX_BUF_PAD 16 |
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220 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ |
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221 |
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222 #if RX_BUF_LEN == 65536 |
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223 #define RX_BUF_TOT_LEN RX_BUF_LEN |
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224 #else |
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225 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) |
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226 #endif |
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227 |
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228 /* Number of Tx descriptor registers. */ |
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229 #define NUM_TX_DESC 4 |
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230 |
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231 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/ |
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232 #define MAX_ETH_FRAME_SIZE 1536 |
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233 |
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234 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ |
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235 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE |
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236 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) |
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237 |
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238 /* PCI Tuning Parameters |
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239 Threshold is bytes transferred to chip before transmission starts. */ |
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240 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ |
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241 |
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242 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ |
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243 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ |
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244 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ |
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245 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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246 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ |
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247 |
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248 /* Operational parameters that usually are not changed. */ |
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249 /* Time in jiffies before concluding the transmitter is hung. */ |
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250 #define TX_TIMEOUT (6*HZ) |
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251 |
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252 |
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253 enum { |
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254 HAS_MII_XCVR = 0x010000, |
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255 HAS_CHIP_XCVR = 0x020000, |
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256 HAS_LNK_CHNG = 0x040000, |
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257 }; |
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258 |
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259 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ |
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260 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ |
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261 #define RTL_MIN_IO_SIZE 0x80 |
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262 #define RTL8139B_IO_SIZE 256 |
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263 |
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264 #define RTL8129_CAPS HAS_MII_XCVR |
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265 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) |
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266 |
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267 typedef enum { |
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268 RTL8139 = 0, |
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269 RTL8129, |
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270 } board_t; |
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271 |
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272 |
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273 /* indexed by board_t, above */ |
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274 static const struct { |
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275 const char *name; |
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276 u32 hw_flags; |
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277 } board_info[] = { |
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278 { "RealTek RTL8139", RTL8139_CAPS }, |
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279 { "RealTek RTL8129", RTL8129_CAPS }, |
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280 }; |
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281 |
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282 |
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283 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = { |
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284 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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285 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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286 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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287 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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288 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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289 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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290 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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291 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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292 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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293 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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294 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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295 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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296 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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297 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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298 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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299 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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300 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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301 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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302 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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303 |
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304 #ifdef CONFIG_SH_SECUREEDGE5410 |
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305 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ |
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306 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, |
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307 #endif |
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308 #ifdef CONFIG_8139TOO_8129 |
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309 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, |
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310 #endif |
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311 |
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312 /* some crazy cards report invalid vendor ids like |
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313 * 0x0001 here. The other ids are valid and constant, |
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314 * so we simply don't match on the main vendor id. |
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315 */ |
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316 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, |
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317 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, |
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318 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, |
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319 |
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320 {0,} |
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321 }; |
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322 |
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323 /* prevent driver from being loaded automatically */ |
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324 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); |
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325 |
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326 static struct { |
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327 const char str[ETH_GSTRING_LEN]; |
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328 } ethtool_stats_keys[] = { |
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329 { "early_rx" }, |
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330 { "tx_buf_mapped" }, |
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331 { "tx_timeouts" }, |
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332 { "rx_lost_in_ring" }, |
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333 }; |
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334 |
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335 /* The rest of these values should never change. */ |
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336 |
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337 /* Symbolic offsets to registers. */ |
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338 enum RTL8139_registers { |
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339 MAC0 = 0, /* Ethernet hardware address. */ |
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340 MAR0 = 8, /* Multicast filter. */ |
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341 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ |
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342 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
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343 RxBuf = 0x30, |
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344 ChipCmd = 0x37, |
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345 RxBufPtr = 0x38, |
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346 RxBufAddr = 0x3A, |
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347 IntrMask = 0x3C, |
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348 IntrStatus = 0x3E, |
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349 TxConfig = 0x40, |
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350 RxConfig = 0x44, |
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351 Timer = 0x48, /* A general-purpose counter. */ |
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352 RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
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353 Cfg9346 = 0x50, |
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354 Config0 = 0x51, |
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355 Config1 = 0x52, |
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356 TimerInt = 0x54, |
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357 MediaStatus = 0x58, |
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358 Config3 = 0x59, |
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359 Config4 = 0x5A, /* absent on RTL-8139A */ |
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360 HltClk = 0x5B, |
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361 MultiIntr = 0x5C, |
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362 TxSummary = 0x60, |
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363 BasicModeCtrl = 0x62, |
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364 BasicModeStatus = 0x64, |
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365 NWayAdvert = 0x66, |
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366 NWayLPAR = 0x68, |
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367 NWayExpansion = 0x6A, |
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368 /* Undocumented registers, but required for proper operation. */ |
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369 FIFOTMS = 0x70, /* FIFO Control and test. */ |
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370 CSCR = 0x74, /* Chip Status and Configuration Register. */ |
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371 PARA78 = 0x78, |
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372 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ |
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373 PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
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374 Config5 = 0xD8, /* absent on RTL-8139A */ |
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375 }; |
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376 |
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377 enum ClearBitMasks { |
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378 MultiIntrClear = 0xF000, |
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379 ChipCmdClear = 0xE2, |
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380 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
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381 }; |
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382 |
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383 enum ChipCmdBits { |
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384 CmdReset = 0x10, |
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385 CmdRxEnb = 0x08, |
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386 CmdTxEnb = 0x04, |
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387 RxBufEmpty = 0x01, |
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388 }; |
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389 |
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390 /* Interrupt register bits, using my own meaningful names. */ |
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391 enum IntrStatusBits { |
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392 PCIErr = 0x8000, |
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393 PCSTimeout = 0x4000, |
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394 RxFIFOOver = 0x40, |
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395 RxUnderrun = 0x20, |
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396 RxOverflow = 0x10, |
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397 TxErr = 0x08, |
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398 TxOK = 0x04, |
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399 RxErr = 0x02, |
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400 RxOK = 0x01, |
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401 |
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402 RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
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403 }; |
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404 |
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405 enum TxStatusBits { |
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406 TxHostOwns = 0x2000, |
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407 TxUnderrun = 0x4000, |
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408 TxStatOK = 0x8000, |
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409 TxOutOfWindow = 0x20000000, |
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410 TxAborted = 0x40000000, |
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411 TxCarrierLost = 0x80000000, |
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412 }; |
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413 enum RxStatusBits { |
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414 RxMulticast = 0x8000, |
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415 RxPhysical = 0x4000, |
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416 RxBroadcast = 0x2000, |
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417 RxBadSymbol = 0x0020, |
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418 RxRunt = 0x0010, |
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419 RxTooLong = 0x0008, |
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420 RxCRCErr = 0x0004, |
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421 RxBadAlign = 0x0002, |
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422 RxStatusOK = 0x0001, |
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423 }; |
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424 |
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425 /* Bits in RxConfig. */ |
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426 enum rx_mode_bits { |
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427 AcceptErr = 0x20, |
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428 AcceptRunt = 0x10, |
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429 AcceptBroadcast = 0x08, |
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430 AcceptMulticast = 0x04, |
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431 AcceptMyPhys = 0x02, |
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432 AcceptAllPhys = 0x01, |
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433 }; |
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434 |
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435 /* Bits in TxConfig. */ |
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436 enum tx_config_bits { |
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437 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ |
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438 TxIFGShift = 24, |
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439 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
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440 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
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441 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
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442 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
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443 |
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444 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
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445 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ |
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446 TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
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447 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ |
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448 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ |
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449 |
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450 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
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451 }; |
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452 |
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453 /* Bits in Config1 */ |
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454 enum Config1Bits { |
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455 Cfg1_PM_Enable = 0x01, |
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456 Cfg1_VPD_Enable = 0x02, |
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457 Cfg1_PIO = 0x04, |
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458 Cfg1_MMIO = 0x08, |
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459 LWAKE = 0x10, /* not on 8139, 8139A */ |
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460 Cfg1_Driver_Load = 0x20, |
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461 Cfg1_LED0 = 0x40, |
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462 Cfg1_LED1 = 0x80, |
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463 SLEEP = (1 << 1), /* only on 8139, 8139A */ |
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464 PWRDN = (1 << 0), /* only on 8139, 8139A */ |
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465 }; |
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466 |
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467 /* Bits in Config3 */ |
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468 enum Config3Bits { |
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469 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
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470 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
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471 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
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472 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
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473 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
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474 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
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475 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
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476 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
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477 }; |
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478 |
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479 /* Bits in Config4 */ |
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480 enum Config4Bits { |
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481 LWPTN = (1 << 2), /* not on 8139, 8139A */ |
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482 }; |
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483 |
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484 /* Bits in Config5 */ |
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485 enum Config5Bits { |
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486 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
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487 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
|
488 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
|
489 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ |
|
490 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
|
491 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
|
492 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
|
493 }; |
|
494 |
|
495 enum RxConfigBits { |
|
496 /* rx fifo threshold */ |
|
497 RxCfgFIFOShift = 13, |
|
498 RxCfgFIFONone = (7 << RxCfgFIFOShift), |
|
499 |
|
500 /* Max DMA burst */ |
|
501 RxCfgDMAShift = 8, |
|
502 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), |
|
503 |
|
504 /* rx ring buffer length */ |
|
505 RxCfgRcv8K = 0, |
|
506 RxCfgRcv16K = (1 << 11), |
|
507 RxCfgRcv32K = (1 << 12), |
|
508 RxCfgRcv64K = (1 << 11) | (1 << 12), |
|
509 |
|
510 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ |
|
511 RxNoWrap = (1 << 7), |
|
512 }; |
|
513 |
|
514 /* Twister tuning parameters from RealTek. |
|
515 Completely undocumented, but required to tune bad links on some boards. */ |
|
516 enum CSCRBits { |
|
517 CSCR_LinkOKBit = 0x0400, |
|
518 CSCR_LinkChangeBit = 0x0800, |
|
519 CSCR_LinkStatusBits = 0x0f000, |
|
520 CSCR_LinkDownOffCmd = 0x003c0, |
|
521 CSCR_LinkDownCmd = 0x0f3c0, |
|
522 }; |
|
523 |
|
524 enum Cfg9346Bits { |
|
525 Cfg9346_Lock = 0x00, |
|
526 Cfg9346_Unlock = 0xC0, |
|
527 }; |
|
528 |
|
529 typedef enum { |
|
530 CH_8139 = 0, |
|
531 CH_8139_K, |
|
532 CH_8139A, |
|
533 CH_8139A_G, |
|
534 CH_8139B, |
|
535 CH_8130, |
|
536 CH_8139C, |
|
537 CH_8100, |
|
538 CH_8100B_8139D, |
|
539 CH_8101, |
|
540 } chip_t; |
|
541 |
|
542 enum chip_flags { |
|
543 HasHltClk = (1 << 0), |
|
544 HasLWake = (1 << 1), |
|
545 }; |
|
546 |
|
547 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ |
|
548 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
|
549 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
|
550 |
|
551 /* directly indexed by chip_t, above */ |
|
552 static const struct { |
|
553 const char *name; |
|
554 u32 version; /* from RTL8139C/RTL8139D docs */ |
|
555 u32 flags; |
|
556 } rtl_chip_info[] = { |
|
557 { "RTL-8139", |
|
558 HW_REVID(1, 0, 0, 0, 0, 0, 0), |
|
559 HasHltClk, |
|
560 }, |
|
561 |
|
562 { "RTL-8139 rev K", |
|
563 HW_REVID(1, 1, 0, 0, 0, 0, 0), |
|
564 HasHltClk, |
|
565 }, |
|
566 |
|
567 { "RTL-8139A", |
|
568 HW_REVID(1, 1, 1, 0, 0, 0, 0), |
|
569 HasHltClk, /* XXX undocumented? */ |
|
570 }, |
|
571 |
|
572 { "RTL-8139A rev G", |
|
573 HW_REVID(1, 1, 1, 0, 0, 1, 0), |
|
574 HasHltClk, /* XXX undocumented? */ |
|
575 }, |
|
576 |
|
577 { "RTL-8139B", |
|
578 HW_REVID(1, 1, 1, 1, 0, 0, 0), |
|
579 HasLWake, |
|
580 }, |
|
581 |
|
582 { "RTL-8130", |
|
583 HW_REVID(1, 1, 1, 1, 1, 0, 0), |
|
584 HasLWake, |
|
585 }, |
|
586 |
|
587 { "RTL-8139C", |
|
588 HW_REVID(1, 1, 1, 0, 1, 0, 0), |
|
589 HasLWake, |
|
590 }, |
|
591 |
|
592 { "RTL-8100", |
|
593 HW_REVID(1, 1, 1, 1, 0, 1, 0), |
|
594 HasLWake, |
|
595 }, |
|
596 |
|
597 { "RTL-8100B/8139D", |
|
598 HW_REVID(1, 1, 1, 0, 1, 0, 1), |
|
599 HasHltClk /* XXX undocumented? */ |
|
600 | HasLWake, |
|
601 }, |
|
602 |
|
603 { "RTL-8101", |
|
604 HW_REVID(1, 1, 1, 0, 1, 1, 1), |
|
605 HasLWake, |
|
606 }, |
|
607 }; |
|
608 |
|
609 struct rtl_extra_stats { |
|
610 unsigned long early_rx; |
|
611 unsigned long tx_buf_mapped; |
|
612 unsigned long tx_timeouts; |
|
613 unsigned long rx_lost_in_ring; |
|
614 }; |
|
615 |
|
616 struct rtl8139_stats { |
|
617 u64 packets; |
|
618 u64 bytes; |
|
619 struct u64_stats_sync syncp; |
|
620 }; |
|
621 |
|
622 struct rtl8139_private { |
|
623 void __iomem *mmio_addr; |
|
624 int drv_flags; |
|
625 struct pci_dev *pci_dev; |
|
626 u32 msg_enable; |
|
627 struct napi_struct napi; |
|
628 struct net_device *dev; |
|
629 |
|
630 unsigned char *rx_ring; |
|
631 unsigned int cur_rx; /* RX buf index of next pkt */ |
|
632 struct rtl8139_stats rx_stats; |
|
633 dma_addr_t rx_ring_dma; |
|
634 |
|
635 unsigned int tx_flag; |
|
636 unsigned long cur_tx; |
|
637 unsigned long dirty_tx; |
|
638 struct rtl8139_stats tx_stats; |
|
639 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ |
|
640 unsigned char *tx_bufs; /* Tx bounce buffer region. */ |
|
641 dma_addr_t tx_bufs_dma; |
|
642 |
|
643 signed char phys[4]; /* MII device addresses. */ |
|
644 |
|
645 /* Twister tune state. */ |
|
646 char twistie, twist_row, twist_col; |
|
647 |
|
648 unsigned int watchdog_fired : 1; |
|
649 unsigned int default_port : 4; /* Last dev->if_port value. */ |
|
650 unsigned int have_thread : 1; |
|
651 |
|
652 spinlock_t lock; |
|
653 spinlock_t rx_lock; |
|
654 |
|
655 chip_t chipset; |
|
656 u32 rx_config; |
|
657 struct rtl_extra_stats xstats; |
|
658 |
|
659 struct delayed_work thread; |
|
660 |
|
661 struct mii_if_info mii; |
|
662 unsigned int regs_len; |
|
663 unsigned long fifo_copy_timeout; |
|
664 |
|
665 ec_device_t *ecdev; |
|
666 }; |
|
667 |
|
668 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>"); |
|
669 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver"); |
|
670 MODULE_LICENSE("GPL"); |
|
671 MODULE_VERSION(EC_MASTER_VERSION); |
|
672 |
|
673 module_param(use_io, bool, 0); |
|
674 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); |
|
675 module_param(multicast_filter_limit, int, 0); |
|
676 module_param_array(media, int, NULL, 0); |
|
677 module_param_array(full_duplex, int, NULL, 0); |
|
678 module_param(debug, int, 0); |
|
679 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); |
|
680 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); |
|
681 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); |
|
682 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); |
|
683 |
|
684 void ec_poll(struct net_device *); |
|
685 |
|
686 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); |
|
687 static int rtl8139_open (struct net_device *dev); |
|
688 static int mdio_read (struct net_device *dev, int phy_id, int location); |
|
689 static void mdio_write (struct net_device *dev, int phy_id, int location, |
|
690 int val); |
|
691 static void rtl8139_start_thread(struct rtl8139_private *tp); |
|
692 static void rtl8139_tx_timeout (struct net_device *dev); |
|
693 static void rtl8139_init_ring (struct net_device *dev); |
|
694 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, |
|
695 struct net_device *dev); |
|
696 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
697 static void rtl8139_poll_controller(struct net_device *dev); |
|
698 #endif |
|
699 static int rtl8139_set_mac_address(struct net_device *dev, void *p); |
|
700 static int rtl8139_poll(struct napi_struct *napi, int budget); |
|
701 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); |
|
702 static int rtl8139_close (struct net_device *dev); |
|
703 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); |
|
704 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev, |
|
705 struct rtnl_link_stats64 |
|
706 *stats); |
|
707 static void rtl8139_set_rx_mode (struct net_device *dev); |
|
708 static void __set_rx_mode (struct net_device *dev); |
|
709 static void rtl8139_hw_start (struct net_device *dev); |
|
710 static void rtl8139_thread (struct work_struct *work); |
|
711 static void rtl8139_tx_timeout_task(struct work_struct *work); |
|
712 static const struct ethtool_ops rtl8139_ethtool_ops; |
|
713 |
|
714 /* write MMIO register, with flush */ |
|
715 /* Flush avoids rtl8139 bug w/ posted MMIO writes */ |
|
716 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) |
|
717 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) |
|
718 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) |
|
719 |
|
720 /* write MMIO register */ |
|
721 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) |
|
722 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) |
|
723 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) |
|
724 |
|
725 /* read MMIO register */ |
|
726 #define RTL_R8(reg) ioread8 (ioaddr + (reg)) |
|
727 #define RTL_R16(reg) ioread16 (ioaddr + (reg)) |
|
728 #define RTL_R32(reg) ioread32 (ioaddr + (reg)) |
|
729 |
|
730 |
|
731 static const u16 rtl8139_intr_mask = |
|
732 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | |
|
733 TxErr | TxOK | RxErr | RxOK; |
|
734 |
|
735 static const u16 rtl8139_norx_intr_mask = |
|
736 PCIErr | PCSTimeout | RxUnderrun | |
|
737 TxErr | TxOK | RxErr ; |
|
738 |
|
739 #if RX_BUF_IDX == 0 |
|
740 static const unsigned int rtl8139_rx_config = |
|
741 RxCfgRcv8K | RxNoWrap | |
|
742 (RX_FIFO_THRESH << RxCfgFIFOShift) | |
|
743 (RX_DMA_BURST << RxCfgDMAShift); |
|
744 #elif RX_BUF_IDX == 1 |
|
745 static const unsigned int rtl8139_rx_config = |
|
746 RxCfgRcv16K | RxNoWrap | |
|
747 (RX_FIFO_THRESH << RxCfgFIFOShift) | |
|
748 (RX_DMA_BURST << RxCfgDMAShift); |
|
749 #elif RX_BUF_IDX == 2 |
|
750 static const unsigned int rtl8139_rx_config = |
|
751 RxCfgRcv32K | RxNoWrap | |
|
752 (RX_FIFO_THRESH << RxCfgFIFOShift) | |
|
753 (RX_DMA_BURST << RxCfgDMAShift); |
|
754 #elif RX_BUF_IDX == 3 |
|
755 static const unsigned int rtl8139_rx_config = |
|
756 RxCfgRcv64K | |
|
757 (RX_FIFO_THRESH << RxCfgFIFOShift) | |
|
758 (RX_DMA_BURST << RxCfgDMAShift); |
|
759 #else |
|
760 #error "Invalid configuration for 8139_RXBUF_IDX" |
|
761 #endif |
|
762 |
|
763 static const unsigned int rtl8139_tx_config = |
|
764 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); |
|
765 |
|
766 static void __rtl8139_cleanup_dev (struct net_device *dev) |
|
767 { |
|
768 struct rtl8139_private *tp = netdev_priv(dev); |
|
769 struct pci_dev *pdev; |
|
770 |
|
771 assert (dev != NULL); |
|
772 assert (tp->pci_dev != NULL); |
|
773 pdev = tp->pci_dev; |
|
774 |
|
775 if (tp->mmio_addr) |
|
776 pci_iounmap (pdev, tp->mmio_addr); |
|
777 |
|
778 /* it's ok to call this even if we have no regions to free */ |
|
779 pci_release_regions (pdev); |
|
780 |
|
781 free_netdev(dev); |
|
782 pci_set_drvdata (pdev, NULL); |
|
783 } |
|
784 |
|
785 |
|
786 static void rtl8139_chip_reset (void __iomem *ioaddr) |
|
787 { |
|
788 int i; |
|
789 |
|
790 /* Soft reset the chip. */ |
|
791 RTL_W8 (ChipCmd, CmdReset); |
|
792 |
|
793 /* Check that the chip has finished the reset. */ |
|
794 for (i = 1000; i > 0; i--) { |
|
795 barrier(); |
|
796 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) |
|
797 break; |
|
798 udelay (10); |
|
799 } |
|
800 } |
|
801 |
|
802 |
|
803 static struct net_device *rtl8139_init_board(struct pci_dev *pdev) |
|
804 { |
|
805 struct device *d = &pdev->dev; |
|
806 void __iomem *ioaddr; |
|
807 struct net_device *dev; |
|
808 struct rtl8139_private *tp; |
|
809 u8 tmp8; |
|
810 int rc, disable_dev_on_err = 0; |
|
811 unsigned int i, bar; |
|
812 unsigned long io_len; |
|
813 u32 version; |
|
814 static const struct { |
|
815 unsigned long mask; |
|
816 char *type; |
|
817 } res[] = { |
|
818 { IORESOURCE_IO, "PIO" }, |
|
819 { IORESOURCE_MEM, "MMIO" } |
|
820 }; |
|
821 |
|
822 assert (pdev != NULL); |
|
823 |
|
824 /* dev and priv zeroed in alloc_etherdev */ |
|
825 dev = alloc_etherdev (sizeof (*tp)); |
|
826 if (dev == NULL) |
|
827 return ERR_PTR(-ENOMEM); |
|
828 |
|
829 SET_NETDEV_DEV(dev, &pdev->dev); |
|
830 |
|
831 tp = netdev_priv(dev); |
|
832 tp->pci_dev = pdev; |
|
833 |
|
834 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
835 rc = pci_enable_device (pdev); |
|
836 if (rc) |
|
837 goto err_out; |
|
838 |
|
839 rc = pci_request_regions (pdev, DRV_NAME); |
|
840 if (rc) |
|
841 goto err_out; |
|
842 disable_dev_on_err = 1; |
|
843 |
|
844 pci_set_master (pdev); |
|
845 |
|
846 retry: |
|
847 /* PIO bar register comes first. */ |
|
848 bar = !use_io; |
|
849 |
|
850 io_len = pci_resource_len(pdev, bar); |
|
851 |
|
852 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len); |
|
853 |
|
854 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { |
|
855 dev_err(d, "region #%d not a %s resource, aborting\n", bar, |
|
856 res[bar].type); |
|
857 rc = -ENODEV; |
|
858 goto err_out; |
|
859 } |
|
860 if (io_len < RTL_MIN_IO_SIZE) { |
|
861 dev_err(d, "Invalid PCI %s region size(s), aborting\n", |
|
862 res[bar].type); |
|
863 rc = -ENODEV; |
|
864 goto err_out; |
|
865 } |
|
866 |
|
867 ioaddr = pci_iomap(pdev, bar, 0); |
|
868 if (!ioaddr) { |
|
869 dev_err(d, "cannot map %s\n", res[bar].type); |
|
870 if (!use_io) { |
|
871 use_io = true; |
|
872 goto retry; |
|
873 } |
|
874 rc = -ENODEV; |
|
875 goto err_out; |
|
876 } |
|
877 tp->regs_len = io_len; |
|
878 tp->mmio_addr = ioaddr; |
|
879 |
|
880 /* Bring old chips out of low-power mode. */ |
|
881 RTL_W8 (HltClk, 'R'); |
|
882 |
|
883 /* check for missing/broken hardware */ |
|
884 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { |
|
885 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); |
|
886 rc = -EIO; |
|
887 goto err_out; |
|
888 } |
|
889 |
|
890 /* identify chip attached to board */ |
|
891 version = RTL_R32 (TxConfig) & HW_REVID_MASK; |
|
892 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) |
|
893 if (version == rtl_chip_info[i].version) { |
|
894 tp->chipset = i; |
|
895 goto match; |
|
896 } |
|
897 |
|
898 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ |
|
899 i = 0; |
|
900 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); |
|
901 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); |
|
902 tp->chipset = 0; |
|
903 |
|
904 match: |
|
905 pr_debug("chipset id (%d) == index %d, '%s'\n", |
|
906 version, i, rtl_chip_info[i].name); |
|
907 |
|
908 if (tp->chipset >= CH_8139B) { |
|
909 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); |
|
910 pr_debug("PCI PM wakeup\n"); |
|
911 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && |
|
912 (tmp8 & LWAKE)) |
|
913 new_tmp8 &= ~LWAKE; |
|
914 new_tmp8 |= Cfg1_PM_Enable; |
|
915 if (new_tmp8 != tmp8) { |
|
916 RTL_W8 (Cfg9346, Cfg9346_Unlock); |
|
917 RTL_W8 (Config1, tmp8); |
|
918 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
919 } |
|
920 if (rtl_chip_info[tp->chipset].flags & HasLWake) { |
|
921 tmp8 = RTL_R8 (Config4); |
|
922 if (tmp8 & LWPTN) { |
|
923 RTL_W8 (Cfg9346, Cfg9346_Unlock); |
|
924 RTL_W8 (Config4, tmp8 & ~LWPTN); |
|
925 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
926 } |
|
927 } |
|
928 } else { |
|
929 pr_debug("Old chip wakeup\n"); |
|
930 tmp8 = RTL_R8 (Config1); |
|
931 tmp8 &= ~(SLEEP | PWRDN); |
|
932 RTL_W8 (Config1, tmp8); |
|
933 } |
|
934 |
|
935 rtl8139_chip_reset (ioaddr); |
|
936 |
|
937 return dev; |
|
938 |
|
939 err_out: |
|
940 __rtl8139_cleanup_dev (dev); |
|
941 if (disable_dev_on_err) |
|
942 pci_disable_device (pdev); |
|
943 return ERR_PTR(rc); |
|
944 } |
|
945 |
|
946 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) |
|
947 { |
|
948 struct rtl8139_private *tp = netdev_priv(dev); |
|
949 unsigned long flags; |
|
950 netdev_features_t changed = features ^ dev->features; |
|
951 void __iomem *ioaddr = tp->mmio_addr; |
|
952 |
|
953 if (!(changed & (NETIF_F_RXALL))) |
|
954 return 0; |
|
955 |
|
956 spin_lock_irqsave(&tp->lock, flags); |
|
957 |
|
958 if (changed & NETIF_F_RXALL) { |
|
959 int rx_mode = tp->rx_config; |
|
960 if (features & NETIF_F_RXALL) |
|
961 rx_mode |= (AcceptErr | AcceptRunt); |
|
962 else |
|
963 rx_mode &= ~(AcceptErr | AcceptRunt); |
|
964 tp->rx_config = rtl8139_rx_config | rx_mode; |
|
965 RTL_W32_F(RxConfig, tp->rx_config); |
|
966 } |
|
967 |
|
968 spin_unlock_irqrestore(&tp->lock, flags); |
|
969 |
|
970 return 0; |
|
971 } |
|
972 |
|
973 static const struct net_device_ops rtl8139_netdev_ops = { |
|
974 .ndo_open = rtl8139_open, |
|
975 .ndo_stop = rtl8139_close, |
|
976 .ndo_get_stats64 = rtl8139_get_stats64, |
|
977 .ndo_change_mtu = eth_change_mtu, |
|
978 .ndo_validate_addr = eth_validate_addr, |
|
979 .ndo_set_mac_address = rtl8139_set_mac_address, |
|
980 .ndo_start_xmit = rtl8139_start_xmit, |
|
981 .ndo_set_rx_mode = rtl8139_set_rx_mode, |
|
982 .ndo_do_ioctl = netdev_ioctl, |
|
983 .ndo_tx_timeout = rtl8139_tx_timeout, |
|
984 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
985 .ndo_poll_controller = rtl8139_poll_controller, |
|
986 #endif |
|
987 .ndo_set_features = rtl8139_set_features, |
|
988 }; |
|
989 |
|
990 static int rtl8139_init_one(struct pci_dev *pdev, |
|
991 const struct pci_device_id *ent) |
|
992 { |
|
993 struct net_device *dev = NULL; |
|
994 struct rtl8139_private *tp; |
|
995 int i, addr_len, option; |
|
996 void __iomem *ioaddr; |
|
997 static int board_idx = -1; |
|
998 |
|
999 assert (pdev != NULL); |
|
1000 assert (ent != NULL); |
|
1001 |
|
1002 board_idx++; |
|
1003 |
|
1004 /* when we're built into the kernel, the driver version message |
|
1005 * is only printed if at least one 8139 board has been found |
|
1006 */ |
|
1007 #ifndef MODULE |
|
1008 { |
|
1009 static int printed_version; |
|
1010 if (!printed_version++) |
|
1011 pr_info(RTL8139_DRIVER_NAME "\n"); |
|
1012 } |
|
1013 #endif |
|
1014 |
|
1015 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && |
|
1016 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { |
|
1017 dev_info(&pdev->dev, |
|
1018 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", |
|
1019 pdev->vendor, pdev->device, pdev->revision); |
|
1020 return -ENODEV; |
|
1021 } |
|
1022 |
|
1023 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && |
|
1024 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && |
|
1025 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && |
|
1026 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { |
|
1027 pr_info("OQO Model 2 detected. Forcing PIO\n"); |
|
1028 use_io = 1; |
|
1029 } |
|
1030 |
|
1031 dev = rtl8139_init_board (pdev); |
|
1032 if (IS_ERR(dev)) |
|
1033 return PTR_ERR(dev); |
|
1034 |
|
1035 assert (dev != NULL); |
|
1036 tp = netdev_priv(dev); |
|
1037 tp->dev = dev; |
|
1038 |
|
1039 ioaddr = tp->mmio_addr; |
|
1040 assert (ioaddr != NULL); |
|
1041 |
|
1042 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; |
|
1043 for (i = 0; i < 3; i++) |
|
1044 ((__le16 *) (dev->dev_addr))[i] = |
|
1045 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); |
|
1046 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
1047 |
|
1048 /* The Rtl8139-specific entries in the device structure. */ |
|
1049 dev->netdev_ops = &rtl8139_netdev_ops; |
|
1050 dev->ethtool_ops = &rtl8139_ethtool_ops; |
|
1051 dev->watchdog_timeo = TX_TIMEOUT; |
|
1052 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64); |
|
1053 |
|
1054 /* note: the hardware is not capable of sg/csum/highdma, however |
|
1055 * through the use of skb_copy_and_csum_dev we enable these |
|
1056 * features |
|
1057 */ |
|
1058 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; |
|
1059 dev->vlan_features = dev->features; |
|
1060 |
|
1061 dev->hw_features |= NETIF_F_RXALL; |
|
1062 dev->hw_features |= NETIF_F_RXFCS; |
|
1063 |
|
1064 /* tp zeroed and aligned in alloc_etherdev */ |
|
1065 tp = netdev_priv(dev); |
|
1066 |
|
1067 /* note: tp->chipset set in rtl8139_init_board */ |
|
1068 tp->drv_flags = board_info[ent->driver_data].hw_flags; |
|
1069 tp->mmio_addr = ioaddr; |
|
1070 tp->msg_enable = |
|
1071 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); |
|
1072 spin_lock_init (&tp->lock); |
|
1073 spin_lock_init (&tp->rx_lock); |
|
1074 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); |
|
1075 tp->mii.dev = dev; |
|
1076 tp->mii.mdio_read = mdio_read; |
|
1077 tp->mii.mdio_write = mdio_write; |
|
1078 tp->mii.phy_id_mask = 0x3f; |
|
1079 tp->mii.reg_num_mask = 0x1f; |
|
1080 |
|
1081 /* dev is fully set up and ready to use now */ |
|
1082 |
|
1083 // offer device to EtherCAT master module |
|
1084 tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); |
|
1085 |
|
1086 if (!tp->ecdev) { |
|
1087 pr_debug("about to register device named %s (%p)...\n", |
|
1088 dev->name, dev); |
|
1089 i = register_netdev (dev); |
|
1090 if (i) goto err_out; |
|
1091 } |
|
1092 |
|
1093 pci_set_drvdata (pdev, dev); |
|
1094 |
|
1095 pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n", |
|
1096 dev->name, |
|
1097 board_info[ent->driver_data].name, |
|
1098 dev->base_addr, |
|
1099 dev->dev_addr, |
|
1100 dev->irq); |
|
1101 |
|
1102 pr_debug("%s: Identified 8139 chip type '%s'\n", |
|
1103 dev->name, rtl_chip_info[tp->chipset].name); |
|
1104 |
|
1105 /* Find the connected MII xcvrs. |
|
1106 Doing this in open() would allow detecting external xcvrs later, but |
|
1107 takes too much time. */ |
|
1108 #ifdef CONFIG_8139TOO_8129 |
|
1109 if (tp->drv_flags & HAS_MII_XCVR) { |
|
1110 int phy, phy_idx = 0; |
|
1111 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { |
|
1112 int mii_status = mdio_read(dev, phy, 1); |
|
1113 if (mii_status != 0xffff && mii_status != 0x0000) { |
|
1114 u16 advertising = mdio_read(dev, phy, 4); |
|
1115 tp->phys[phy_idx++] = phy; |
|
1116 pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n", |
|
1117 dev->name, phy, mii_status, advertising); |
|
1118 } |
|
1119 } |
|
1120 if (phy_idx == 0) { |
|
1121 pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n", |
|
1122 dev->name); |
|
1123 tp->phys[0] = 32; |
|
1124 } |
|
1125 } else |
|
1126 #endif |
|
1127 tp->phys[0] = 32; |
|
1128 tp->mii.phy_id = tp->phys[0]; |
|
1129 |
|
1130 /* The lower four bits are the media type. */ |
|
1131 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; |
|
1132 if (option > 0) { |
|
1133 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; |
|
1134 tp->default_port = option & 0xFF; |
|
1135 if (tp->default_port) |
|
1136 tp->mii.force_media = 1; |
|
1137 } |
|
1138 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) |
|
1139 tp->mii.full_duplex = full_duplex[board_idx]; |
|
1140 if (tp->mii.full_duplex) { |
|
1141 pr_info("%s: Media type forced to Full Duplex.\n", dev->name); |
|
1142 /* Changing the MII-advertised media because might prevent |
|
1143 re-connection. */ |
|
1144 tp->mii.force_media = 1; |
|
1145 } |
|
1146 if (tp->default_port) { |
|
1147 pr_info(" Forcing %dMbps %s-duplex operation.\n", |
|
1148 (option & 0x20 ? 100 : 10), |
|
1149 (option & 0x10 ? "full" : "half")); |
|
1150 mdio_write(dev, tp->phys[0], 0, |
|
1151 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ |
|
1152 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ |
|
1153 } |
|
1154 |
|
1155 /* Put the chip into low-power mode. */ |
|
1156 if (rtl_chip_info[tp->chipset].flags & HasHltClk) |
|
1157 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ |
|
1158 |
|
1159 if (tp->ecdev) { |
|
1160 i = ecdev_open(tp->ecdev); |
|
1161 if (i) { |
|
1162 ecdev_withdraw(tp->ecdev); |
|
1163 goto err_out; |
|
1164 } |
|
1165 } |
|
1166 |
|
1167 return 0; |
|
1168 |
|
1169 err_out: |
|
1170 __rtl8139_cleanup_dev (dev); |
|
1171 pci_disable_device (pdev); |
|
1172 return i; |
|
1173 } |
|
1174 |
|
1175 |
|
1176 static void rtl8139_remove_one(struct pci_dev *pdev) |
|
1177 { |
|
1178 struct net_device *dev = pci_get_drvdata (pdev); |
|
1179 struct rtl8139_private *tp = netdev_priv(dev); |
|
1180 |
|
1181 assert (dev != NULL); |
|
1182 |
|
1183 if (tp->ecdev) { |
|
1184 ecdev_close(tp->ecdev); |
|
1185 ecdev_withdraw(tp->ecdev); |
|
1186 } |
|
1187 else { |
|
1188 cancel_delayed_work_sync(&tp->thread); |
|
1189 |
|
1190 unregister_netdev (dev); |
|
1191 } |
|
1192 |
|
1193 __rtl8139_cleanup_dev (dev); |
|
1194 pci_disable_device (pdev); |
|
1195 } |
|
1196 |
|
1197 |
|
1198 /* Serial EEPROM section. */ |
|
1199 |
|
1200 /* EEPROM_Ctrl bits. */ |
|
1201 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ |
|
1202 #define EE_CS 0x08 /* EEPROM chip select. */ |
|
1203 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ |
|
1204 #define EE_WRITE_0 0x00 |
|
1205 #define EE_WRITE_1 0x02 |
|
1206 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ |
|
1207 #define EE_ENB (0x80 | EE_CS) |
|
1208 |
|
1209 /* Delay between EEPROM clock transitions. |
|
1210 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. |
|
1211 */ |
|
1212 |
|
1213 #define eeprom_delay() (void)RTL_R8(Cfg9346) |
|
1214 |
|
1215 /* The EEPROM commands include the alway-set leading bit. */ |
|
1216 #define EE_WRITE_CMD (5) |
|
1217 #define EE_READ_CMD (6) |
|
1218 #define EE_ERASE_CMD (7) |
|
1219 |
|
1220 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len) |
|
1221 { |
|
1222 int i; |
|
1223 unsigned retval = 0; |
|
1224 int read_cmd = location | (EE_READ_CMD << addr_len); |
|
1225 |
|
1226 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); |
|
1227 RTL_W8 (Cfg9346, EE_ENB); |
|
1228 eeprom_delay (); |
|
1229 |
|
1230 /* Shift the read command bits out. */ |
|
1231 for (i = 4 + addr_len; i >= 0; i--) { |
|
1232 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; |
|
1233 RTL_W8 (Cfg9346, EE_ENB | dataval); |
|
1234 eeprom_delay (); |
|
1235 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); |
|
1236 eeprom_delay (); |
|
1237 } |
|
1238 RTL_W8 (Cfg9346, EE_ENB); |
|
1239 eeprom_delay (); |
|
1240 |
|
1241 for (i = 16; i > 0; i--) { |
|
1242 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); |
|
1243 eeprom_delay (); |
|
1244 retval = |
|
1245 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : |
|
1246 0); |
|
1247 RTL_W8 (Cfg9346, EE_ENB); |
|
1248 eeprom_delay (); |
|
1249 } |
|
1250 |
|
1251 /* Terminate the EEPROM access. */ |
|
1252 RTL_W8(Cfg9346, 0); |
|
1253 eeprom_delay (); |
|
1254 |
|
1255 return retval; |
|
1256 } |
|
1257 |
|
1258 /* MII serial management: mostly bogus for now. */ |
|
1259 /* Read and write the MII management registers using software-generated |
|
1260 serial MDIO protocol. |
|
1261 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually |
|
1262 met by back-to-back PCI I/O cycles, but we insert a delay to avoid |
|
1263 "overclocking" issues. */ |
|
1264 #define MDIO_DIR 0x80 |
|
1265 #define MDIO_DATA_OUT 0x04 |
|
1266 #define MDIO_DATA_IN 0x02 |
|
1267 #define MDIO_CLK 0x01 |
|
1268 #define MDIO_WRITE0 (MDIO_DIR) |
|
1269 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) |
|
1270 |
|
1271 #define mdio_delay() RTL_R8(Config4) |
|
1272 |
|
1273 |
|
1274 static const char mii_2_8139_map[8] = { |
|
1275 BasicModeCtrl, |
|
1276 BasicModeStatus, |
|
1277 0, |
|
1278 0, |
|
1279 NWayAdvert, |
|
1280 NWayLPAR, |
|
1281 NWayExpansion, |
|
1282 0 |
|
1283 }; |
|
1284 |
|
1285 |
|
1286 #ifdef CONFIG_8139TOO_8129 |
|
1287 /* Syncronize the MII management interface by shifting 32 one bits out. */ |
|
1288 static void mdio_sync (void __iomem *ioaddr) |
|
1289 { |
|
1290 int i; |
|
1291 |
|
1292 for (i = 32; i >= 0; i--) { |
|
1293 RTL_W8 (Config4, MDIO_WRITE1); |
|
1294 mdio_delay (); |
|
1295 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); |
|
1296 mdio_delay (); |
|
1297 } |
|
1298 } |
|
1299 #endif |
|
1300 |
|
1301 static int mdio_read (struct net_device *dev, int phy_id, int location) |
|
1302 { |
|
1303 struct rtl8139_private *tp = netdev_priv(dev); |
|
1304 int retval = 0; |
|
1305 #ifdef CONFIG_8139TOO_8129 |
|
1306 void __iomem *ioaddr = tp->mmio_addr; |
|
1307 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; |
|
1308 int i; |
|
1309 #endif |
|
1310 |
|
1311 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ |
|
1312 void __iomem *ioaddr = tp->mmio_addr; |
|
1313 return location < 8 && mii_2_8139_map[location] ? |
|
1314 RTL_R16 (mii_2_8139_map[location]) : 0; |
|
1315 } |
|
1316 |
|
1317 #ifdef CONFIG_8139TOO_8129 |
|
1318 mdio_sync (ioaddr); |
|
1319 /* Shift the read command bits out. */ |
|
1320 for (i = 15; i >= 0; i--) { |
|
1321 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; |
|
1322 |
|
1323 RTL_W8 (Config4, MDIO_DIR | dataval); |
|
1324 mdio_delay (); |
|
1325 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); |
|
1326 mdio_delay (); |
|
1327 } |
|
1328 |
|
1329 /* Read the two transition, 16 data, and wire-idle bits. */ |
|
1330 for (i = 19; i > 0; i--) { |
|
1331 RTL_W8 (Config4, 0); |
|
1332 mdio_delay (); |
|
1333 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); |
|
1334 RTL_W8 (Config4, MDIO_CLK); |
|
1335 mdio_delay (); |
|
1336 } |
|
1337 #endif |
|
1338 |
|
1339 return (retval >> 1) & 0xffff; |
|
1340 } |
|
1341 |
|
1342 |
|
1343 static void mdio_write (struct net_device *dev, int phy_id, int location, |
|
1344 int value) |
|
1345 { |
|
1346 struct rtl8139_private *tp = netdev_priv(dev); |
|
1347 #ifdef CONFIG_8139TOO_8129 |
|
1348 void __iomem *ioaddr = tp->mmio_addr; |
|
1349 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; |
|
1350 int i; |
|
1351 #endif |
|
1352 |
|
1353 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ |
|
1354 void __iomem *ioaddr = tp->mmio_addr; |
|
1355 if (location == 0) { |
|
1356 RTL_W8 (Cfg9346, Cfg9346_Unlock); |
|
1357 RTL_W16 (BasicModeCtrl, value); |
|
1358 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
1359 } else if (location < 8 && mii_2_8139_map[location]) |
|
1360 RTL_W16 (mii_2_8139_map[location], value); |
|
1361 return; |
|
1362 } |
|
1363 |
|
1364 #ifdef CONFIG_8139TOO_8129 |
|
1365 mdio_sync (ioaddr); |
|
1366 |
|
1367 /* Shift the command bits out. */ |
|
1368 for (i = 31; i >= 0; i--) { |
|
1369 int dataval = |
|
1370 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; |
|
1371 RTL_W8 (Config4, dataval); |
|
1372 mdio_delay (); |
|
1373 RTL_W8 (Config4, dataval | MDIO_CLK); |
|
1374 mdio_delay (); |
|
1375 } |
|
1376 /* Clear out extra bits. */ |
|
1377 for (i = 2; i > 0; i--) { |
|
1378 RTL_W8 (Config4, 0); |
|
1379 mdio_delay (); |
|
1380 RTL_W8 (Config4, MDIO_CLK); |
|
1381 mdio_delay (); |
|
1382 } |
|
1383 #endif |
|
1384 } |
|
1385 |
|
1386 |
|
1387 static int rtl8139_open (struct net_device *dev) |
|
1388 { |
|
1389 struct rtl8139_private *tp = netdev_priv(dev); |
|
1390 void __iomem *ioaddr = tp->mmio_addr; |
|
1391 const int irq = tp->pci_dev->irq; |
|
1392 int retval; |
|
1393 |
|
1394 if (!tp->ecdev) { |
|
1395 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); |
|
1396 if (retval) |
|
1397 return retval; |
|
1398 } |
|
1399 |
|
1400 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, |
|
1401 &tp->tx_bufs_dma, GFP_KERNEL); |
|
1402 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, |
|
1403 &tp->rx_ring_dma, GFP_KERNEL); |
|
1404 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { |
|
1405 if (!tp->ecdev) { |
|
1406 free_irq(irq, dev); |
|
1407 } |
|
1408 |
|
1409 if (tp->tx_bufs) |
|
1410 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, |
|
1411 tp->tx_bufs, tp->tx_bufs_dma); |
|
1412 if (tp->rx_ring) |
|
1413 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, |
|
1414 tp->rx_ring, tp->rx_ring_dma); |
|
1415 |
|
1416 return -ENOMEM; |
|
1417 |
|
1418 } |
|
1419 |
|
1420 napi_enable(&tp->napi); |
|
1421 |
|
1422 tp->mii.full_duplex = tp->mii.force_media; |
|
1423 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; |
|
1424 |
|
1425 rtl8139_init_ring (dev); |
|
1426 rtl8139_hw_start (dev); |
|
1427 if (!tp->ecdev) { |
|
1428 netif_start_queue (dev); |
|
1429 } |
|
1430 |
|
1431 netif_dbg(tp, ifup, dev, |
|
1432 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", |
|
1433 __func__, |
|
1434 (unsigned long long)pci_resource_start (tp->pci_dev, 1), |
|
1435 irq, RTL_R8 (MediaStatus), |
|
1436 tp->mii.full_duplex ? "full" : "half"); |
|
1437 |
|
1438 if (!tp->ecdev) { |
|
1439 rtl8139_start_thread(tp); |
|
1440 } |
|
1441 |
|
1442 return 0; |
|
1443 } |
|
1444 |
|
1445 |
|
1446 static void rtl_check_media (struct net_device *dev, unsigned int init_media) |
|
1447 { |
|
1448 struct rtl8139_private *tp = netdev_priv(dev); |
|
1449 |
|
1450 if (tp->ecdev) { |
|
1451 void __iomem *ioaddr = tp->mmio_addr; |
|
1452 u16 state = RTL_R16(BasicModeStatus) & BMSR_LSTATUS; |
|
1453 ecdev_set_link(tp->ecdev, state ? 1 : 0); |
|
1454 } |
|
1455 else { |
|
1456 if (tp->phys[0] >= 0) { |
|
1457 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); |
|
1458 } |
|
1459 } |
|
1460 } |
|
1461 |
|
1462 /* Start the hardware at open or resume. */ |
|
1463 static void rtl8139_hw_start (struct net_device *dev) |
|
1464 { |
|
1465 struct rtl8139_private *tp = netdev_priv(dev); |
|
1466 void __iomem *ioaddr = tp->mmio_addr; |
|
1467 u32 i; |
|
1468 u8 tmp; |
|
1469 |
|
1470 /* Bring old chips out of low-power mode. */ |
|
1471 if (rtl_chip_info[tp->chipset].flags & HasHltClk) |
|
1472 RTL_W8 (HltClk, 'R'); |
|
1473 |
|
1474 rtl8139_chip_reset (ioaddr); |
|
1475 |
|
1476 /* unlock Config[01234] and BMCR register writes */ |
|
1477 RTL_W8_F (Cfg9346, Cfg9346_Unlock); |
|
1478 /* Restore our idea of the MAC address. */ |
|
1479 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); |
|
1480 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); |
|
1481 |
|
1482 tp->cur_rx = 0; |
|
1483 |
|
1484 /* init Rx ring buffer DMA address */ |
|
1485 RTL_W32_F (RxBuf, tp->rx_ring_dma); |
|
1486 |
|
1487 /* Must enable Tx/Rx before setting transfer thresholds! */ |
|
1488 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); |
|
1489 |
|
1490 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; |
|
1491 RTL_W32 (RxConfig, tp->rx_config); |
|
1492 RTL_W32 (TxConfig, rtl8139_tx_config); |
|
1493 |
|
1494 rtl_check_media (dev, 1); |
|
1495 |
|
1496 if (tp->chipset >= CH_8139B) { |
|
1497 /* Disable magic packet scanning, which is enabled |
|
1498 * when PM is enabled in Config1. It can be reenabled |
|
1499 * via ETHTOOL_SWOL if desired. */ |
|
1500 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); |
|
1501 } |
|
1502 |
|
1503 netdev_dbg(dev, "init buffer addresses\n"); |
|
1504 |
|
1505 /* Lock Config[01234] and BMCR register writes */ |
|
1506 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
1507 |
|
1508 /* init Tx buffer DMA addresses */ |
|
1509 for (i = 0; i < NUM_TX_DESC; i++) |
|
1510 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); |
|
1511 |
|
1512 RTL_W32 (RxMissed, 0); |
|
1513 |
|
1514 rtl8139_set_rx_mode (dev); |
|
1515 |
|
1516 /* no early-rx interrupts */ |
|
1517 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); |
|
1518 |
|
1519 /* make sure RxTx has started */ |
|
1520 tmp = RTL_R8 (ChipCmd); |
|
1521 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) |
|
1522 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); |
|
1523 |
|
1524 if (!tp->ecdev) { |
|
1525 /* Enable all known interrupts by setting the interrupt mask. */ |
|
1526 RTL_W16 (IntrMask, rtl8139_intr_mask); |
|
1527 } |
|
1528 } |
|
1529 |
|
1530 |
|
1531 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ |
|
1532 static void rtl8139_init_ring (struct net_device *dev) |
|
1533 { |
|
1534 struct rtl8139_private *tp = netdev_priv(dev); |
|
1535 int i; |
|
1536 |
|
1537 tp->cur_rx = 0; |
|
1538 tp->cur_tx = 0; |
|
1539 tp->dirty_tx = 0; |
|
1540 |
|
1541 for (i = 0; i < NUM_TX_DESC; i++) |
|
1542 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; |
|
1543 } |
|
1544 |
|
1545 |
|
1546 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ |
|
1547 static int next_tick = 3 * HZ; |
|
1548 |
|
1549 #ifndef CONFIG_8139TOO_TUNE_TWISTER |
|
1550 static inline void rtl8139_tune_twister (struct net_device *dev, |
|
1551 struct rtl8139_private *tp) {} |
|
1552 #else |
|
1553 enum TwisterParamVals { |
|
1554 PARA78_default = 0x78fa8388, |
|
1555 PARA7c_default = 0xcb38de43, /* param[0][3] */ |
|
1556 PARA7c_xxx = 0xcb38de43, |
|
1557 }; |
|
1558 |
|
1559 static const unsigned long param[4][4] = { |
|
1560 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, |
|
1561 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, |
|
1562 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, |
|
1563 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} |
|
1564 }; |
|
1565 |
|
1566 static void rtl8139_tune_twister (struct net_device *dev, |
|
1567 struct rtl8139_private *tp) |
|
1568 { |
|
1569 int linkcase; |
|
1570 void __iomem *ioaddr = tp->mmio_addr; |
|
1571 |
|
1572 /* This is a complicated state machine to configure the "twister" for |
|
1573 impedance/echos based on the cable length. |
|
1574 All of this is magic and undocumented. |
|
1575 */ |
|
1576 switch (tp->twistie) { |
|
1577 case 1: |
|
1578 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { |
|
1579 /* We have link beat, let us tune the twister. */ |
|
1580 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); |
|
1581 tp->twistie = 2; /* Change to state 2. */ |
|
1582 next_tick = HZ / 10; |
|
1583 } else { |
|
1584 /* Just put in some reasonable defaults for when beat returns. */ |
|
1585 RTL_W16 (CSCR, CSCR_LinkDownCmd); |
|
1586 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ |
|
1587 RTL_W32 (PARA78, PARA78_default); |
|
1588 RTL_W32 (PARA7c, PARA7c_default); |
|
1589 tp->twistie = 0; /* Bail from future actions. */ |
|
1590 } |
|
1591 break; |
|
1592 case 2: |
|
1593 /* Read how long it took to hear the echo. */ |
|
1594 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; |
|
1595 if (linkcase == 0x7000) |
|
1596 tp->twist_row = 3; |
|
1597 else if (linkcase == 0x3000) |
|
1598 tp->twist_row = 2; |
|
1599 else if (linkcase == 0x1000) |
|
1600 tp->twist_row = 1; |
|
1601 else |
|
1602 tp->twist_row = 0; |
|
1603 tp->twist_col = 0; |
|
1604 tp->twistie = 3; /* Change to state 2. */ |
|
1605 next_tick = HZ / 10; |
|
1606 break; |
|
1607 case 3: |
|
1608 /* Put out four tuning parameters, one per 100msec. */ |
|
1609 if (tp->twist_col == 0) |
|
1610 RTL_W16 (FIFOTMS, 0); |
|
1611 RTL_W32 (PARA7c, param[(int) tp->twist_row] |
|
1612 [(int) tp->twist_col]); |
|
1613 next_tick = HZ / 10; |
|
1614 if (++tp->twist_col >= 4) { |
|
1615 /* For short cables we are done. |
|
1616 For long cables (row == 3) check for mistune. */ |
|
1617 tp->twistie = |
|
1618 (tp->twist_row == 3) ? 4 : 0; |
|
1619 } |
|
1620 break; |
|
1621 case 4: |
|
1622 /* Special case for long cables: check for mistune. */ |
|
1623 if ((RTL_R16 (CSCR) & |
|
1624 CSCR_LinkStatusBits) == 0x7000) { |
|
1625 tp->twistie = 0; |
|
1626 break; |
|
1627 } else { |
|
1628 RTL_W32 (PARA7c, 0xfb38de03); |
|
1629 tp->twistie = 5; |
|
1630 next_tick = HZ / 10; |
|
1631 } |
|
1632 break; |
|
1633 case 5: |
|
1634 /* Retune for shorter cable (column 2). */ |
|
1635 RTL_W32 (FIFOTMS, 0x20); |
|
1636 RTL_W32 (PARA78, PARA78_default); |
|
1637 RTL_W32 (PARA7c, PARA7c_default); |
|
1638 RTL_W32 (FIFOTMS, 0x00); |
|
1639 tp->twist_row = 2; |
|
1640 tp->twist_col = 0; |
|
1641 tp->twistie = 3; |
|
1642 next_tick = HZ / 10; |
|
1643 break; |
|
1644 |
|
1645 default: |
|
1646 /* do nothing */ |
|
1647 break; |
|
1648 } |
|
1649 } |
|
1650 #endif /* CONFIG_8139TOO_TUNE_TWISTER */ |
|
1651 |
|
1652 static inline void rtl8139_thread_iter (struct net_device *dev, |
|
1653 struct rtl8139_private *tp, |
|
1654 void __iomem *ioaddr) |
|
1655 { |
|
1656 int mii_lpa; |
|
1657 |
|
1658 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); |
|
1659 |
|
1660 if (!tp->mii.force_media && mii_lpa != 0xffff) { |
|
1661 int duplex = ((mii_lpa & LPA_100FULL) || |
|
1662 (mii_lpa & 0x01C0) == 0x0040); |
|
1663 if (tp->mii.full_duplex != duplex) { |
|
1664 tp->mii.full_duplex = duplex; |
|
1665 |
|
1666 if (mii_lpa) { |
|
1667 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", |
|
1668 tp->mii.full_duplex ? "full" : "half", |
|
1669 tp->phys[0], mii_lpa); |
|
1670 } else { |
|
1671 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); |
|
1672 } |
|
1673 #if 0 |
|
1674 RTL_W8 (Cfg9346, Cfg9346_Unlock); |
|
1675 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); |
|
1676 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
1677 #endif |
|
1678 } |
|
1679 } |
|
1680 |
|
1681 next_tick = HZ * 60; |
|
1682 |
|
1683 rtl8139_tune_twister (dev, tp); |
|
1684 |
|
1685 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", |
|
1686 RTL_R16(NWayLPAR)); |
|
1687 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", |
|
1688 RTL_R16(IntrMask), RTL_R16(IntrStatus)); |
|
1689 netdev_dbg(dev, "Chip config %02x %02x\n", |
|
1690 RTL_R8(Config0), RTL_R8(Config1)); |
|
1691 } |
|
1692 |
|
1693 static void rtl8139_thread (struct work_struct *work) |
|
1694 { |
|
1695 struct rtl8139_private *tp = |
|
1696 container_of(work, struct rtl8139_private, thread.work); |
|
1697 struct net_device *dev = tp->mii.dev; |
|
1698 unsigned long thr_delay = next_tick; |
|
1699 |
|
1700 rtnl_lock(); |
|
1701 |
|
1702 if (!netif_running(dev)) |
|
1703 goto out_unlock; |
|
1704 |
|
1705 if (tp->watchdog_fired) { |
|
1706 tp->watchdog_fired = 0; |
|
1707 rtl8139_tx_timeout_task(work); |
|
1708 } else |
|
1709 rtl8139_thread_iter(dev, tp, tp->mmio_addr); |
|
1710 |
|
1711 if (tp->have_thread) |
|
1712 schedule_delayed_work(&tp->thread, thr_delay); |
|
1713 out_unlock: |
|
1714 rtnl_unlock (); |
|
1715 } |
|
1716 |
|
1717 static void rtl8139_start_thread(struct rtl8139_private *tp) |
|
1718 { |
|
1719 tp->twistie = 0; |
|
1720 if (tp->chipset == CH_8139_K) |
|
1721 tp->twistie = 1; |
|
1722 else if (tp->drv_flags & HAS_LNK_CHNG) |
|
1723 return; |
|
1724 |
|
1725 tp->have_thread = 1; |
|
1726 tp->watchdog_fired = 0; |
|
1727 |
|
1728 schedule_delayed_work(&tp->thread, next_tick); |
|
1729 } |
|
1730 |
|
1731 static inline void rtl8139_tx_clear (struct rtl8139_private *tp) |
|
1732 { |
|
1733 tp->cur_tx = 0; |
|
1734 tp->dirty_tx = 0; |
|
1735 |
|
1736 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ |
|
1737 } |
|
1738 |
|
1739 static void rtl8139_tx_timeout_task (struct work_struct *work) |
|
1740 { |
|
1741 struct rtl8139_private *tp = |
|
1742 container_of(work, struct rtl8139_private, thread.work); |
|
1743 struct net_device *dev = tp->mii.dev; |
|
1744 void __iomem *ioaddr = tp->mmio_addr; |
|
1745 int i; |
|
1746 u8 tmp8; |
|
1747 |
|
1748 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", |
|
1749 RTL_R8(ChipCmd), RTL_R16(IntrStatus), |
|
1750 RTL_R16(IntrMask), RTL_R8(MediaStatus)); |
|
1751 /* Emit info to figure out what went wrong. */ |
|
1752 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", |
|
1753 tp->cur_tx, tp->dirty_tx); |
|
1754 for (i = 0; i < NUM_TX_DESC; i++) |
|
1755 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", |
|
1756 i, RTL_R32(TxStatus0 + (i * 4)), |
|
1757 i == tp->dirty_tx % NUM_TX_DESC ? |
|
1758 " (queue head)" : ""); |
|
1759 |
|
1760 tp->xstats.tx_timeouts++; |
|
1761 |
|
1762 /* disable Tx ASAP, if not already */ |
|
1763 tmp8 = RTL_R8 (ChipCmd); |
|
1764 if (tmp8 & CmdTxEnb) |
|
1765 RTL_W8 (ChipCmd, CmdRxEnb); |
|
1766 |
|
1767 if (tp->ecdev) { |
|
1768 rtl8139_tx_clear (tp); |
|
1769 rtl8139_hw_start (dev); |
|
1770 } |
|
1771 else { |
|
1772 spin_lock_bh(&tp->rx_lock); |
|
1773 |
|
1774 /* Disable interrupts by clearing the interrupt mask. */ |
|
1775 RTL_W16 (IntrMask, 0x0000); |
|
1776 |
|
1777 /* Stop a shared interrupt from scavenging while we are. */ |
|
1778 spin_lock_irq(&tp->lock); |
|
1779 rtl8139_tx_clear (tp); |
|
1780 spin_unlock_irq(&tp->lock); |
|
1781 |
|
1782 /* ...and finally, reset everything */ |
|
1783 if (netif_running(dev)) { |
|
1784 rtl8139_hw_start (dev); |
|
1785 netif_wake_queue (dev); |
|
1786 } |
|
1787 |
|
1788 spin_unlock_bh(&tp->rx_lock); |
|
1789 } |
|
1790 } |
|
1791 |
|
1792 static void rtl8139_tx_timeout (struct net_device *dev) |
|
1793 { |
|
1794 struct rtl8139_private *tp = netdev_priv(dev); |
|
1795 |
|
1796 tp->watchdog_fired = 1; |
|
1797 if (!tp->ecdev && !tp->have_thread) { |
|
1798 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); |
|
1799 schedule_delayed_work(&tp->thread, next_tick); |
|
1800 } |
|
1801 } |
|
1802 |
|
1803 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, |
|
1804 struct net_device *dev) |
|
1805 { |
|
1806 struct rtl8139_private *tp = netdev_priv(dev); |
|
1807 void __iomem *ioaddr = tp->mmio_addr; |
|
1808 unsigned int entry; |
|
1809 unsigned int len = skb->len; |
|
1810 unsigned long flags = 0; |
|
1811 |
|
1812 /* Calculate the next Tx descriptor entry. */ |
|
1813 entry = tp->cur_tx % NUM_TX_DESC; |
|
1814 |
|
1815 /* Note: the chip doesn't have auto-pad! */ |
|
1816 if (likely(len < TX_BUF_SIZE)) { |
|
1817 if (len < ETH_ZLEN) |
|
1818 memset(tp->tx_buf[entry], 0, ETH_ZLEN); |
|
1819 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); |
|
1820 if (!tp->ecdev) { |
|
1821 dev_kfree_skb(skb); |
|
1822 } |
|
1823 } else { |
|
1824 if (!tp->ecdev) { |
|
1825 dev_kfree_skb(skb); |
|
1826 } |
|
1827 dev->stats.tx_dropped++; |
|
1828 return NETDEV_TX_OK; |
|
1829 } |
|
1830 |
|
1831 if (!tp->ecdev) { |
|
1832 spin_lock_irqsave(&tp->lock, flags); |
|
1833 } |
|
1834 /* |
|
1835 * Writing to TxStatus triggers a DMA transfer of the data |
|
1836 * copied to tp->tx_buf[entry] above. Use a memory barrier |
|
1837 * to make sure that the device sees the updated data. |
|
1838 */ |
|
1839 wmb(); |
|
1840 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), |
|
1841 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); |
|
1842 |
|
1843 tp->cur_tx++; |
|
1844 |
|
1845 if (!tp->ecdev) { |
|
1846 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) |
|
1847 netif_stop_queue (dev); |
|
1848 spin_unlock_irqrestore(&tp->lock, flags); |
|
1849 } |
|
1850 |
|
1851 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", |
|
1852 len, entry); |
|
1853 |
|
1854 return NETDEV_TX_OK; |
|
1855 } |
|
1856 |
|
1857 |
|
1858 static void rtl8139_tx_interrupt (struct net_device *dev, |
|
1859 struct rtl8139_private *tp, |
|
1860 void __iomem *ioaddr) |
|
1861 { |
|
1862 unsigned long dirty_tx, tx_left; |
|
1863 |
|
1864 assert (dev != NULL); |
|
1865 assert (ioaddr != NULL); |
|
1866 |
|
1867 dirty_tx = tp->dirty_tx; |
|
1868 tx_left = tp->cur_tx - dirty_tx; |
|
1869 while (tx_left > 0) { |
|
1870 int entry = dirty_tx % NUM_TX_DESC; |
|
1871 int txstatus; |
|
1872 |
|
1873 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); |
|
1874 |
|
1875 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) |
|
1876 break; /* It still hasn't been Txed */ |
|
1877 |
|
1878 /* Note: TxCarrierLost is always asserted at 100mbps. */ |
|
1879 if (txstatus & (TxOutOfWindow | TxAborted)) { |
|
1880 /* There was an major error, log it. */ |
|
1881 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", |
|
1882 txstatus); |
|
1883 dev->stats.tx_errors++; |
|
1884 if (txstatus & TxAborted) { |
|
1885 dev->stats.tx_aborted_errors++; |
|
1886 RTL_W32 (TxConfig, TxClearAbt); |
|
1887 RTL_W16 (IntrStatus, TxErr); |
|
1888 wmb(); |
|
1889 } |
|
1890 if (txstatus & TxCarrierLost) |
|
1891 dev->stats.tx_carrier_errors++; |
|
1892 if (txstatus & TxOutOfWindow) |
|
1893 dev->stats.tx_window_errors++; |
|
1894 } else { |
|
1895 if (txstatus & TxUnderrun) { |
|
1896 /* Add 64 to the Tx FIFO threshold. */ |
|
1897 if (tp->tx_flag < 0x00300000) |
|
1898 tp->tx_flag += 0x00020000; |
|
1899 dev->stats.tx_fifo_errors++; |
|
1900 } |
|
1901 dev->stats.collisions += (txstatus >> 24) & 15; |
|
1902 u64_stats_update_begin(&tp->tx_stats.syncp); |
|
1903 tp->tx_stats.packets++; |
|
1904 tp->tx_stats.bytes += txstatus & 0x7ff; |
|
1905 u64_stats_update_end(&tp->tx_stats.syncp); |
|
1906 } |
|
1907 |
|
1908 dirty_tx++; |
|
1909 tx_left--; |
|
1910 } |
|
1911 |
|
1912 #ifndef RTL8139_NDEBUG |
|
1913 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { |
|
1914 pr_err("%s: Out-of-sync dirty pointer, %ld vs. %ld.\n", |
|
1915 dev->name, dirty_tx, tp->cur_tx); |
|
1916 dirty_tx += NUM_TX_DESC; |
|
1917 } |
|
1918 #endif /* RTL8139_NDEBUG */ |
|
1919 |
|
1920 /* only wake the queue if we did work, and the queue is stopped */ |
|
1921 if (tp->dirty_tx != dirty_tx) { |
|
1922 tp->dirty_tx = dirty_tx; |
|
1923 mb(); |
|
1924 if (!tp->ecdev) { |
|
1925 netif_wake_queue (dev); |
|
1926 } |
|
1927 } |
|
1928 } |
|
1929 |
|
1930 |
|
1931 /* TODO: clean this up! Rx reset need not be this intensive */ |
|
1932 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, |
|
1933 struct rtl8139_private *tp, void __iomem *ioaddr) |
|
1934 { |
|
1935 u8 tmp8; |
|
1936 #ifdef CONFIG_8139_OLD_RX_RESET |
|
1937 int tmp_work; |
|
1938 #endif |
|
1939 |
|
1940 if (netif_msg_rx_err (tp)) |
|
1941 pr_debug("%s: Ethernet frame had errors, status %8.8x.\n", |
|
1942 dev->name, rx_status); |
|
1943 dev->stats.rx_errors++; |
|
1944 if (!(rx_status & RxStatusOK)) { |
|
1945 if (rx_status & RxTooLong) { |
|
1946 pr_debug("%s: Oversized Ethernet frame, status %4.4x!\n", |
|
1947 dev->name, rx_status); |
|
1948 /* A.C.: The chip hangs here. */ |
|
1949 } |
|
1950 if (rx_status & (RxBadSymbol | RxBadAlign)) |
|
1951 dev->stats.rx_frame_errors++; |
|
1952 if (rx_status & (RxRunt | RxTooLong)) |
|
1953 dev->stats.rx_length_errors++; |
|
1954 if (rx_status & RxCRCErr) |
|
1955 dev->stats.rx_crc_errors++; |
|
1956 } else { |
|
1957 tp->xstats.rx_lost_in_ring++; |
|
1958 } |
|
1959 |
|
1960 #ifndef CONFIG_8139_OLD_RX_RESET |
|
1961 tmp8 = RTL_R8 (ChipCmd); |
|
1962 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); |
|
1963 RTL_W8 (ChipCmd, tmp8); |
|
1964 RTL_W32 (RxConfig, tp->rx_config); |
|
1965 tp->cur_rx = 0; |
|
1966 #else |
|
1967 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ |
|
1968 |
|
1969 /* disable receive */ |
|
1970 RTL_W8_F (ChipCmd, CmdTxEnb); |
|
1971 tmp_work = 200; |
|
1972 while (--tmp_work > 0) { |
|
1973 udelay(1); |
|
1974 tmp8 = RTL_R8 (ChipCmd); |
|
1975 if (!(tmp8 & CmdRxEnb)) |
|
1976 break; |
|
1977 } |
|
1978 if (tmp_work <= 0) |
|
1979 pr_warning(PFX "rx stop wait too long\n"); |
|
1980 /* restart receive */ |
|
1981 tmp_work = 200; |
|
1982 while (--tmp_work > 0) { |
|
1983 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); |
|
1984 udelay(1); |
|
1985 tmp8 = RTL_R8 (ChipCmd); |
|
1986 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) |
|
1987 break; |
|
1988 } |
|
1989 if (tmp_work <= 0) |
|
1990 pr_warning(PFX "tx/rx enable wait too long\n"); |
|
1991 |
|
1992 /* and reinitialize all rx related registers */ |
|
1993 RTL_W8_F (Cfg9346, Cfg9346_Unlock); |
|
1994 /* Must enable Tx/Rx before setting transfer thresholds! */ |
|
1995 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); |
|
1996 |
|
1997 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; |
|
1998 RTL_W32 (RxConfig, tp->rx_config); |
|
1999 tp->cur_rx = 0; |
|
2000 |
|
2001 pr_debug("init buffer addresses\n"); |
|
2002 |
|
2003 /* Lock Config[01234] and BMCR register writes */ |
|
2004 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
2005 |
|
2006 /* init Rx ring buffer DMA address */ |
|
2007 RTL_W32_F (RxBuf, tp->rx_ring_dma); |
|
2008 |
|
2009 /* A.C.: Reset the multicast list. */ |
|
2010 __set_rx_mode (dev); |
|
2011 #endif |
|
2012 } |
|
2013 |
|
2014 #if RX_BUF_IDX == 3 |
|
2015 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, |
|
2016 u32 offset, unsigned int size) |
|
2017 { |
|
2018 u32 left = RX_BUF_LEN - offset; |
|
2019 |
|
2020 if (size > left) { |
|
2021 skb_copy_to_linear_data(skb, ring + offset, left); |
|
2022 skb_copy_to_linear_data_offset(skb, left, ring, size - left); |
|
2023 } else |
|
2024 skb_copy_to_linear_data(skb, ring + offset, size); |
|
2025 } |
|
2026 #endif |
|
2027 |
|
2028 static void rtl8139_isr_ack(struct rtl8139_private *tp) |
|
2029 { |
|
2030 void __iomem *ioaddr = tp->mmio_addr; |
|
2031 u16 status; |
|
2032 |
|
2033 status = RTL_R16 (IntrStatus) & RxAckBits; |
|
2034 |
|
2035 /* Clear out errors and receive interrupts */ |
|
2036 if (likely(status != 0)) { |
|
2037 if (unlikely(status & (RxFIFOOver | RxOverflow))) { |
|
2038 tp->dev->stats.rx_errors++; |
|
2039 if (status & RxFIFOOver) |
|
2040 tp->dev->stats.rx_fifo_errors++; |
|
2041 } |
|
2042 RTL_W16_F (IntrStatus, RxAckBits); |
|
2043 } |
|
2044 } |
|
2045 |
|
2046 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, |
|
2047 int budget) |
|
2048 { |
|
2049 void __iomem *ioaddr = tp->mmio_addr; |
|
2050 int received = 0; |
|
2051 unsigned char *rx_ring = tp->rx_ring; |
|
2052 unsigned int cur_rx = tp->cur_rx; |
|
2053 unsigned int rx_size = 0; |
|
2054 |
|
2055 pr_debug("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x," |
|
2056 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx, |
|
2057 RTL_R16 (RxBufAddr), |
|
2058 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd)); |
|
2059 |
|
2060 while ((tp->ecdev || netif_running(dev)) |
|
2061 && received < budget |
|
2062 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { |
|
2063 u32 ring_offset = cur_rx % RX_BUF_LEN; |
|
2064 u32 rx_status; |
|
2065 unsigned int pkt_size; |
|
2066 struct sk_buff *skb; |
|
2067 |
|
2068 rmb(); |
|
2069 |
|
2070 /* read size+status of next frame from DMA ring buffer */ |
|
2071 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); |
|
2072 rx_size = rx_status >> 16; |
|
2073 if (likely(!(dev->features & NETIF_F_RXFCS))) |
|
2074 pkt_size = rx_size - 4; |
|
2075 else |
|
2076 pkt_size = rx_size; |
|
2077 |
|
2078 if (!tp->ecdev) { |
|
2079 if (netif_msg_rx_status(tp)) |
|
2080 pr_debug("%s: rtl8139_rx() status %4.4x, size %4.4x," |
|
2081 " cur %4.4x.\n", dev->name, rx_status, |
|
2082 rx_size, cur_rx); |
|
2083 } |
|
2084 #if RTL8139_DEBUG > 2 |
|
2085 { |
|
2086 int i; |
|
2087 pr_debug("%s: Frame contents ", dev->name); |
|
2088 for (i = 0; i < 70; i++) |
|
2089 pr_cont(" %2.2x", |
|
2090 rx_ring[ring_offset + i]); |
|
2091 pr_cont(".\n"); |
|
2092 } |
|
2093 #endif |
|
2094 |
|
2095 /* Packet copy from FIFO still in progress. |
|
2096 * Theoretically, this should never happen |
|
2097 * since EarlyRx is disabled. |
|
2098 */ |
|
2099 if (unlikely(rx_size == 0xfff0)) { |
|
2100 if (!tp->fifo_copy_timeout) |
|
2101 tp->fifo_copy_timeout = jiffies + 2; |
|
2102 else if (time_after(jiffies, tp->fifo_copy_timeout)) { |
|
2103 pr_debug("%s: hung FIFO. Reset.", dev->name); |
|
2104 rx_size = 0; |
|
2105 goto no_early_rx; |
|
2106 } |
|
2107 if (netif_msg_intr(tp)) { |
|
2108 pr_debug("%s: fifo copy in progress.", |
|
2109 dev->name); |
|
2110 } |
|
2111 tp->xstats.early_rx++; |
|
2112 break; |
|
2113 } |
|
2114 |
|
2115 no_early_rx: |
|
2116 tp->fifo_copy_timeout = 0; |
|
2117 |
|
2118 /* If Rx err or invalid rx_size/rx_status received |
|
2119 * (which happens if we get lost in the ring), |
|
2120 * Rx process gets reset, so we abort any further |
|
2121 * Rx processing. |
|
2122 */ |
|
2123 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || |
|
2124 (rx_size < 8) || |
|
2125 (!(rx_status & RxStatusOK)))) { |
|
2126 if ((dev->features & NETIF_F_RXALL) && |
|
2127 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && |
|
2128 (rx_size >= 8) && |
|
2129 (!(rx_status & RxStatusOK))) { |
|
2130 /* Length is at least mostly OK, but pkt has |
|
2131 * error. I'm hoping we can handle some of these |
|
2132 * errors without resetting the chip. --Ben |
|
2133 */ |
|
2134 dev->stats.rx_errors++; |
|
2135 if (rx_status & RxCRCErr) { |
|
2136 dev->stats.rx_crc_errors++; |
|
2137 goto keep_pkt; |
|
2138 } |
|
2139 if (rx_status & RxRunt) { |
|
2140 dev->stats.rx_length_errors++; |
|
2141 goto keep_pkt; |
|
2142 } |
|
2143 } |
|
2144 rtl8139_rx_err (rx_status, dev, tp, ioaddr); |
|
2145 received = -1; |
|
2146 goto out; |
|
2147 } |
|
2148 |
|
2149 keep_pkt: |
|
2150 if (tp->ecdev) { |
|
2151 ecdev_receive(tp->ecdev, |
|
2152 &rx_ring[ring_offset + 4], pkt_size); |
|
2153 dev->last_rx = jiffies; |
|
2154 dev->stats.rx_bytes += pkt_size; |
|
2155 dev->stats.rx_packets++; |
|
2156 } else { |
|
2157 /* Malloc up new buffer, compatible with net-2e. */ |
|
2158 /* Omit the four octet CRC from the length. */ |
|
2159 |
|
2160 skb = netdev_alloc_skb_ip_align(dev, pkt_size); |
|
2161 if (likely(skb)) { |
|
2162 #if RX_BUF_IDX == 3 |
|
2163 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); |
|
2164 #else |
|
2165 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], |
|
2166 pkt_size); |
|
2167 #endif |
|
2168 skb_put (skb, pkt_size); |
|
2169 |
|
2170 skb->protocol = eth_type_trans (skb, dev); |
|
2171 |
|
2172 u64_stats_update_begin(&tp->rx_stats.syncp); |
|
2173 tp->rx_stats.packets++; |
|
2174 tp->rx_stats.bytes += pkt_size; |
|
2175 u64_stats_update_end(&tp->rx_stats.syncp); |
|
2176 |
|
2177 netif_receive_skb (skb); |
|
2178 } else { |
|
2179 if (net_ratelimit()) |
|
2180 netdev_warn(dev, "Memory squeeze, dropping packet\n"); |
|
2181 dev->stats.rx_dropped++; |
|
2182 } |
|
2183 } |
|
2184 received++; |
|
2185 |
|
2186 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; |
|
2187 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); |
|
2188 |
|
2189 rtl8139_isr_ack(tp); |
|
2190 } |
|
2191 |
|
2192 if (unlikely(!received || rx_size == 0xfff0)) |
|
2193 rtl8139_isr_ack(tp); |
|
2194 |
|
2195 pr_debug("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x," |
|
2196 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx, |
|
2197 RTL_R16 (RxBufAddr), |
|
2198 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd)); |
|
2199 |
|
2200 tp->cur_rx = cur_rx; |
|
2201 |
|
2202 /* |
|
2203 * The receive buffer should be mostly empty. |
|
2204 * Tell NAPI to reenable the Rx irq. |
|
2205 */ |
|
2206 if (tp->fifo_copy_timeout) |
|
2207 received = budget; |
|
2208 |
|
2209 out: |
|
2210 return received; |
|
2211 } |
|
2212 |
|
2213 |
|
2214 static void rtl8139_weird_interrupt (struct net_device *dev, |
|
2215 struct rtl8139_private *tp, |
|
2216 void __iomem *ioaddr, |
|
2217 int status, int link_changed) |
|
2218 { |
|
2219 pr_debug("%s: Abnormal interrupt, status %8.8x.\n", |
|
2220 dev->name, status); |
|
2221 |
|
2222 assert (dev != NULL); |
|
2223 assert (tp != NULL); |
|
2224 assert (ioaddr != NULL); |
|
2225 |
|
2226 /* Update the error count. */ |
|
2227 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); |
|
2228 RTL_W32 (RxMissed, 0); |
|
2229 |
|
2230 if ((status & RxUnderrun) && link_changed && |
|
2231 (tp->drv_flags & HAS_LNK_CHNG)) { |
|
2232 rtl_check_media(dev, 0); |
|
2233 status &= ~RxUnderrun; |
|
2234 } |
|
2235 |
|
2236 if (status & (RxUnderrun | RxErr)) |
|
2237 dev->stats.rx_errors++; |
|
2238 |
|
2239 if (status & PCSTimeout) |
|
2240 dev->stats.rx_length_errors++; |
|
2241 if (status & RxUnderrun) |
|
2242 dev->stats.rx_fifo_errors++; |
|
2243 if (status & PCIErr) { |
|
2244 u16 pci_cmd_status; |
|
2245 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); |
|
2246 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); |
|
2247 |
|
2248 pr_err("%s: PCI Bus error %4.4x.\n", |
|
2249 dev->name, pci_cmd_status); |
|
2250 } |
|
2251 } |
|
2252 |
|
2253 static int rtl8139_poll(struct napi_struct *napi, int budget) |
|
2254 { |
|
2255 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); |
|
2256 struct net_device *dev = tp->dev; |
|
2257 void __iomem *ioaddr = tp->mmio_addr; |
|
2258 int work_done; |
|
2259 |
|
2260 spin_lock(&tp->rx_lock); |
|
2261 work_done = 0; |
|
2262 if (likely(RTL_R16(IntrStatus) & RxAckBits)) |
|
2263 work_done += rtl8139_rx(dev, tp, budget); |
|
2264 |
|
2265 if (work_done < budget) { |
|
2266 unsigned long flags; |
|
2267 /* |
|
2268 * Order is important since data can get interrupted |
|
2269 * again when we think we are done. |
|
2270 */ |
|
2271 spin_lock_irqsave(&tp->lock, flags); |
|
2272 __napi_complete(napi); |
|
2273 RTL_W16_F(IntrMask, rtl8139_intr_mask); |
|
2274 spin_unlock_irqrestore(&tp->lock, flags); |
|
2275 } |
|
2276 spin_unlock(&tp->rx_lock); |
|
2277 |
|
2278 return work_done; |
|
2279 } |
|
2280 |
|
2281 void ec_poll(struct net_device *dev) |
|
2282 { |
|
2283 rtl8139_interrupt(0, dev); |
|
2284 } |
|
2285 |
|
2286 /* The interrupt handler does all of the Rx thread work and cleans up |
|
2287 after the Tx thread. */ |
|
2288 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) |
|
2289 { |
|
2290 struct net_device *dev = (struct net_device *) dev_instance; |
|
2291 struct rtl8139_private *tp = netdev_priv(dev); |
|
2292 void __iomem *ioaddr = tp->mmio_addr; |
|
2293 u16 status, ackstat; |
|
2294 int link_changed = 0; /* avoid bogus "uninit" warning */ |
|
2295 int handled = 0; |
|
2296 |
|
2297 if (tp->ecdev) { |
|
2298 status = RTL_R16 (IntrStatus); |
|
2299 } |
|
2300 else { |
|
2301 spin_lock (&tp->lock); |
|
2302 status = RTL_R16 (IntrStatus); |
|
2303 |
|
2304 /* shared irq? */ |
|
2305 if (unlikely((status & rtl8139_intr_mask) == 0)) |
|
2306 goto out; |
|
2307 } |
|
2308 |
|
2309 handled = 1; |
|
2310 |
|
2311 /* h/w no longer present (hotplug?) or major error, bail */ |
|
2312 if (unlikely(status == 0xFFFF)) |
|
2313 goto out; |
|
2314 |
|
2315 if (!tp->ecdev) { |
|
2316 /* close possible race's with dev_close */ |
|
2317 if (unlikely(!netif_running(dev))) { |
|
2318 RTL_W16 (IntrMask, 0); |
|
2319 goto out; |
|
2320 } |
|
2321 } |
|
2322 |
|
2323 /* Acknowledge all of the current interrupt sources ASAP, but |
|
2324 an first get an additional status bit from CSCR. */ |
|
2325 if (unlikely(status & RxUnderrun)) |
|
2326 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; |
|
2327 |
|
2328 ackstat = status & ~(RxAckBits | TxErr); |
|
2329 if (ackstat) |
|
2330 RTL_W16 (IntrStatus, ackstat); |
|
2331 |
|
2332 /* Receive packets are processed by poll routine. |
|
2333 If not running start it now. */ |
|
2334 if (status & RxAckBits){ |
|
2335 if (tp->ecdev) { |
|
2336 /* EtherCAT device: Just receive all frames */ |
|
2337 rtl8139_rx(dev, tp, 100); // FIXME |
|
2338 } else { |
|
2339 /* Mark for polling */ |
|
2340 if (napi_schedule_prep(&tp->napi)) { |
|
2341 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); |
|
2342 __napi_schedule(&tp->napi); |
|
2343 } |
|
2344 } |
|
2345 } |
|
2346 |
|
2347 /* Check uncommon events with one test. */ |
|
2348 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) |
|
2349 rtl8139_weird_interrupt (dev, tp, ioaddr, |
|
2350 status, link_changed); |
|
2351 |
|
2352 if (status & (TxOK | TxErr)) { |
|
2353 rtl8139_tx_interrupt (dev, tp, ioaddr); |
|
2354 if (status & TxErr) |
|
2355 RTL_W16 (IntrStatus, TxErr); |
|
2356 } |
|
2357 out: |
|
2358 if (!tp->ecdev) { |
|
2359 spin_unlock (&tp->lock); |
|
2360 } |
|
2361 |
|
2362 pr_debug("%s: exiting interrupt, intr_status=%#4.4x.\n", |
|
2363 dev->name, RTL_R16 (IntrStatus)); |
|
2364 return IRQ_RETVAL(handled); |
|
2365 } |
|
2366 |
|
2367 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2368 /* |
|
2369 * Polling receive - used by netconsole and other diagnostic tools |
|
2370 * to allow network i/o with interrupts disabled. |
|
2371 */ |
|
2372 static void rtl8139_poll_controller(struct net_device *dev) |
|
2373 { |
|
2374 struct rtl8139_private *tp = netdev_priv(dev); |
|
2375 const int irq = tp->pci_dev->irq; |
|
2376 |
|
2377 disable_irq(irq); |
|
2378 rtl8139_interrupt(irq, dev); |
|
2379 enable_irq(irq); |
|
2380 } |
|
2381 #endif |
|
2382 |
|
2383 static int rtl8139_set_mac_address(struct net_device *dev, void *p) |
|
2384 { |
|
2385 struct rtl8139_private *tp = netdev_priv(dev); |
|
2386 void __iomem *ioaddr = tp->mmio_addr; |
|
2387 struct sockaddr *addr = p; |
|
2388 |
|
2389 if (!is_valid_ether_addr(addr->sa_data)) |
|
2390 return -EADDRNOTAVAIL; |
|
2391 |
|
2392 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
2393 |
|
2394 spin_lock_irq(&tp->lock); |
|
2395 |
|
2396 RTL_W8_F(Cfg9346, Cfg9346_Unlock); |
|
2397 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); |
|
2398 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); |
|
2399 RTL_W8_F(Cfg9346, Cfg9346_Lock); |
|
2400 |
|
2401 spin_unlock_irq(&tp->lock); |
|
2402 |
|
2403 return 0; |
|
2404 } |
|
2405 |
|
2406 static int rtl8139_close (struct net_device *dev) |
|
2407 { |
|
2408 struct rtl8139_private *tp = netdev_priv(dev); |
|
2409 void __iomem *ioaddr = tp->mmio_addr; |
|
2410 unsigned long flags = 0; |
|
2411 |
|
2412 if (!tp->ecdev) { |
|
2413 netif_stop_queue(dev); |
|
2414 napi_disable(&tp->napi); |
|
2415 |
|
2416 netif_dbg(tp, ifdown, dev, |
|
2417 "Shutting down ethercard, status was 0x%04x\n", |
|
2418 RTL_R16(IntrStatus)); |
|
2419 |
|
2420 spin_lock_irqsave (&tp->lock, flags); |
|
2421 } |
|
2422 |
|
2423 /* Stop the chip's Tx and Rx DMA processes. */ |
|
2424 RTL_W8 (ChipCmd, 0); |
|
2425 |
|
2426 /* Disable interrupts by clearing the interrupt mask. */ |
|
2427 RTL_W16 (IntrMask, 0); |
|
2428 |
|
2429 /* Update the error counts. */ |
|
2430 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); |
|
2431 RTL_W32 (RxMissed, 0); |
|
2432 |
|
2433 if (!tp->ecdev) { |
|
2434 spin_unlock_irqrestore (&tp->lock, flags); |
|
2435 |
|
2436 free_irq(tp->pci_dev->irq, dev); |
|
2437 } |
|
2438 |
|
2439 rtl8139_tx_clear (tp); |
|
2440 |
|
2441 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, |
|
2442 tp->rx_ring, tp->rx_ring_dma); |
|
2443 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, |
|
2444 tp->tx_bufs, tp->tx_bufs_dma); |
|
2445 tp->rx_ring = NULL; |
|
2446 tp->tx_bufs = NULL; |
|
2447 |
|
2448 /* Green! Put the chip in low-power mode. */ |
|
2449 RTL_W8 (Cfg9346, Cfg9346_Unlock); |
|
2450 |
|
2451 if (rtl_chip_info[tp->chipset].flags & HasHltClk) |
|
2452 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ |
|
2453 |
|
2454 return 0; |
|
2455 } |
|
2456 |
|
2457 |
|
2458 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to |
|
2459 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and |
|
2460 other threads or interrupts aren't messing with the 8139. */ |
|
2461 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
2462 { |
|
2463 struct rtl8139_private *tp = netdev_priv(dev); |
|
2464 void __iomem *ioaddr = tp->mmio_addr; |
|
2465 |
|
2466 spin_lock_irq(&tp->lock); |
|
2467 if (rtl_chip_info[tp->chipset].flags & HasLWake) { |
|
2468 u8 cfg3 = RTL_R8 (Config3); |
|
2469 u8 cfg5 = RTL_R8 (Config5); |
|
2470 |
|
2471 wol->supported = WAKE_PHY | WAKE_MAGIC |
|
2472 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; |
|
2473 |
|
2474 wol->wolopts = 0; |
|
2475 if (cfg3 & Cfg3_LinkUp) |
|
2476 wol->wolopts |= WAKE_PHY; |
|
2477 if (cfg3 & Cfg3_Magic) |
|
2478 wol->wolopts |= WAKE_MAGIC; |
|
2479 /* (KON)FIXME: See how netdev_set_wol() handles the |
|
2480 following constants. */ |
|
2481 if (cfg5 & Cfg5_UWF) |
|
2482 wol->wolopts |= WAKE_UCAST; |
|
2483 if (cfg5 & Cfg5_MWF) |
|
2484 wol->wolopts |= WAKE_MCAST; |
|
2485 if (cfg5 & Cfg5_BWF) |
|
2486 wol->wolopts |= WAKE_BCAST; |
|
2487 } |
|
2488 spin_unlock_irq(&tp->lock); |
|
2489 } |
|
2490 |
|
2491 |
|
2492 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes |
|
2493 that wol points to kernel memory and other threads or interrupts |
|
2494 aren't messing with the 8139. */ |
|
2495 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
2496 { |
|
2497 struct rtl8139_private *tp = netdev_priv(dev); |
|
2498 void __iomem *ioaddr = tp->mmio_addr; |
|
2499 u32 support; |
|
2500 u8 cfg3, cfg5; |
|
2501 |
|
2502 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) |
|
2503 ? (WAKE_PHY | WAKE_MAGIC |
|
2504 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) |
|
2505 : 0); |
|
2506 if (wol->wolopts & ~support) |
|
2507 return -EINVAL; |
|
2508 |
|
2509 spin_lock_irq(&tp->lock); |
|
2510 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); |
|
2511 if (wol->wolopts & WAKE_PHY) |
|
2512 cfg3 |= Cfg3_LinkUp; |
|
2513 if (wol->wolopts & WAKE_MAGIC) |
|
2514 cfg3 |= Cfg3_Magic; |
|
2515 RTL_W8 (Cfg9346, Cfg9346_Unlock); |
|
2516 RTL_W8 (Config3, cfg3); |
|
2517 RTL_W8 (Cfg9346, Cfg9346_Lock); |
|
2518 |
|
2519 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); |
|
2520 /* (KON)FIXME: These are untested. We may have to set the |
|
2521 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no |
|
2522 documentation. */ |
|
2523 if (wol->wolopts & WAKE_UCAST) |
|
2524 cfg5 |= Cfg5_UWF; |
|
2525 if (wol->wolopts & WAKE_MCAST) |
|
2526 cfg5 |= Cfg5_MWF; |
|
2527 if (wol->wolopts & WAKE_BCAST) |
|
2528 cfg5 |= Cfg5_BWF; |
|
2529 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ |
|
2530 spin_unlock_irq(&tp->lock); |
|
2531 |
|
2532 return 0; |
|
2533 } |
|
2534 |
|
2535 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
|
2536 { |
|
2537 struct rtl8139_private *tp = netdev_priv(dev); |
|
2538 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
|
2539 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); |
|
2540 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); |
|
2541 info->regdump_len = tp->regs_len; |
|
2542 } |
|
2543 |
|
2544 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
2545 { |
|
2546 struct rtl8139_private *tp = netdev_priv(dev); |
|
2547 spin_lock_irq(&tp->lock); |
|
2548 mii_ethtool_gset(&tp->mii, cmd); |
|
2549 spin_unlock_irq(&tp->lock); |
|
2550 return 0; |
|
2551 } |
|
2552 |
|
2553 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
2554 { |
|
2555 struct rtl8139_private *tp = netdev_priv(dev); |
|
2556 int rc; |
|
2557 spin_lock_irq(&tp->lock); |
|
2558 rc = mii_ethtool_sset(&tp->mii, cmd); |
|
2559 spin_unlock_irq(&tp->lock); |
|
2560 return rc; |
|
2561 } |
|
2562 |
|
2563 static int rtl8139_nway_reset(struct net_device *dev) |
|
2564 { |
|
2565 struct rtl8139_private *tp = netdev_priv(dev); |
|
2566 return mii_nway_restart(&tp->mii); |
|
2567 } |
|
2568 |
|
2569 static u32 rtl8139_get_link(struct net_device *dev) |
|
2570 { |
|
2571 struct rtl8139_private *tp = netdev_priv(dev); |
|
2572 return mii_link_ok(&tp->mii); |
|
2573 } |
|
2574 |
|
2575 static u32 rtl8139_get_msglevel(struct net_device *dev) |
|
2576 { |
|
2577 struct rtl8139_private *tp = netdev_priv(dev); |
|
2578 return tp->msg_enable; |
|
2579 } |
|
2580 |
|
2581 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) |
|
2582 { |
|
2583 struct rtl8139_private *tp = netdev_priv(dev); |
|
2584 tp->msg_enable = datum; |
|
2585 } |
|
2586 |
|
2587 static int rtl8139_get_regs_len(struct net_device *dev) |
|
2588 { |
|
2589 struct rtl8139_private *tp; |
|
2590 /* TODO: we are too slack to do reg dumping for pio, for now */ |
|
2591 if (use_io) |
|
2592 return 0; |
|
2593 tp = netdev_priv(dev); |
|
2594 return tp->regs_len; |
|
2595 } |
|
2596 |
|
2597 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) |
|
2598 { |
|
2599 struct rtl8139_private *tp; |
|
2600 |
|
2601 /* TODO: we are too slack to do reg dumping for pio, for now */ |
|
2602 if (use_io) |
|
2603 return; |
|
2604 tp = netdev_priv(dev); |
|
2605 |
|
2606 regs->version = RTL_REGS_VER; |
|
2607 |
|
2608 spin_lock_irq(&tp->lock); |
|
2609 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); |
|
2610 spin_unlock_irq(&tp->lock); |
|
2611 } |
|
2612 |
|
2613 static int rtl8139_get_sset_count(struct net_device *dev, int sset) |
|
2614 { |
|
2615 switch (sset) { |
|
2616 case ETH_SS_STATS: |
|
2617 return RTL_NUM_STATS; |
|
2618 default: |
|
2619 return -EOPNOTSUPP; |
|
2620 } |
|
2621 } |
|
2622 |
|
2623 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) |
|
2624 { |
|
2625 struct rtl8139_private *tp = netdev_priv(dev); |
|
2626 |
|
2627 data[0] = tp->xstats.early_rx; |
|
2628 data[1] = tp->xstats.tx_buf_mapped; |
|
2629 data[2] = tp->xstats.tx_timeouts; |
|
2630 data[3] = tp->xstats.rx_lost_in_ring; |
|
2631 } |
|
2632 |
|
2633 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
2634 { |
|
2635 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); |
|
2636 } |
|
2637 |
|
2638 static const struct ethtool_ops rtl8139_ethtool_ops = { |
|
2639 .get_drvinfo = rtl8139_get_drvinfo, |
|
2640 .get_settings = rtl8139_get_settings, |
|
2641 .set_settings = rtl8139_set_settings, |
|
2642 .get_regs_len = rtl8139_get_regs_len, |
|
2643 .get_regs = rtl8139_get_regs, |
|
2644 .nway_reset = rtl8139_nway_reset, |
|
2645 .get_link = rtl8139_get_link, |
|
2646 .get_msglevel = rtl8139_get_msglevel, |
|
2647 .set_msglevel = rtl8139_set_msglevel, |
|
2648 .get_wol = rtl8139_get_wol, |
|
2649 .set_wol = rtl8139_set_wol, |
|
2650 .get_strings = rtl8139_get_strings, |
|
2651 .get_sset_count = rtl8139_get_sset_count, |
|
2652 .get_ethtool_stats = rtl8139_get_ethtool_stats, |
|
2653 }; |
|
2654 |
|
2655 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
|
2656 { |
|
2657 struct rtl8139_private *tp = netdev_priv(dev); |
|
2658 int rc; |
|
2659 |
|
2660 if (tp->ecdev || !netif_running(dev)) |
|
2661 return -EINVAL; |
|
2662 |
|
2663 spin_lock_irq(&tp->lock); |
|
2664 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); |
|
2665 spin_unlock_irq(&tp->lock); |
|
2666 |
|
2667 return rc; |
|
2668 } |
|
2669 |
|
2670 |
|
2671 static struct rtnl_link_stats64 * |
|
2672 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
|
2673 { |
|
2674 struct rtl8139_private *tp = netdev_priv(dev); |
|
2675 void __iomem *ioaddr = tp->mmio_addr; |
|
2676 unsigned long flags; |
|
2677 unsigned int start; |
|
2678 |
|
2679 if (tp->ecdev || netif_running(dev)) { |
|
2680 spin_lock_irqsave (&tp->lock, flags); |
|
2681 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); |
|
2682 RTL_W32 (RxMissed, 0); |
|
2683 spin_unlock_irqrestore (&tp->lock, flags); |
|
2684 } |
|
2685 |
|
2686 netdev_stats_to_stats64(stats, &dev->stats); |
|
2687 |
|
2688 do { |
|
2689 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp); |
|
2690 stats->rx_packets = tp->rx_stats.packets; |
|
2691 stats->rx_bytes = tp->rx_stats.bytes; |
|
2692 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start)); |
|
2693 |
|
2694 do { |
|
2695 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp); |
|
2696 stats->tx_packets = tp->tx_stats.packets; |
|
2697 stats->tx_bytes = tp->tx_stats.bytes; |
|
2698 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start)); |
|
2699 |
|
2700 return stats; |
|
2701 } |
|
2702 |
|
2703 /* Set or clear the multicast filter for this adaptor. |
|
2704 This routine is not state sensitive and need not be SMP locked. */ |
|
2705 |
|
2706 static void __set_rx_mode (struct net_device *dev) |
|
2707 { |
|
2708 struct rtl8139_private *tp = netdev_priv(dev); |
|
2709 void __iomem *ioaddr = tp->mmio_addr; |
|
2710 u32 mc_filter[2]; /* Multicast hash filter */ |
|
2711 int rx_mode; |
|
2712 u32 tmp; |
|
2713 |
|
2714 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", |
|
2715 dev->flags, RTL_R32(RxConfig)); |
|
2716 |
|
2717 /* Note: do not reorder, GCC is clever about common statements. */ |
|
2718 if (dev->flags & IFF_PROMISC) { |
|
2719 rx_mode = |
|
2720 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
2721 AcceptAllPhys; |
|
2722 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
2723 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
2724 (dev->flags & IFF_ALLMULTI)) { |
|
2725 /* Too many to filter perfectly -- accept all multicasts. */ |
|
2726 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
2727 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
2728 } else { |
|
2729 struct netdev_hw_addr *ha; |
|
2730 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
2731 mc_filter[1] = mc_filter[0] = 0; |
|
2732 netdev_for_each_mc_addr(ha, dev) { |
|
2733 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
|
2734 |
|
2735 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
2736 rx_mode |= AcceptMulticast; |
|
2737 } |
|
2738 } |
|
2739 |
|
2740 if (dev->features & NETIF_F_RXALL) |
|
2741 rx_mode |= (AcceptErr | AcceptRunt); |
|
2742 |
|
2743 /* We can safely update without stopping the chip. */ |
|
2744 tmp = rtl8139_rx_config | rx_mode; |
|
2745 if (tp->rx_config != tmp) { |
|
2746 RTL_W32_F (RxConfig, tmp); |
|
2747 tp->rx_config = tmp; |
|
2748 } |
|
2749 RTL_W32_F (MAR0 + 0, mc_filter[0]); |
|
2750 RTL_W32_F (MAR0 + 4, mc_filter[1]); |
|
2751 } |
|
2752 |
|
2753 static void rtl8139_set_rx_mode (struct net_device *dev) |
|
2754 { |
|
2755 unsigned long flags; |
|
2756 struct rtl8139_private *tp = netdev_priv(dev); |
|
2757 |
|
2758 spin_lock_irqsave (&tp->lock, flags); |
|
2759 __set_rx_mode(dev); |
|
2760 spin_unlock_irqrestore (&tp->lock, flags); |
|
2761 } |
|
2762 |
|
2763 #ifdef CONFIG_PM |
|
2764 |
|
2765 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state) |
|
2766 { |
|
2767 struct net_device *dev = pci_get_drvdata (pdev); |
|
2768 struct rtl8139_private *tp = netdev_priv(dev); |
|
2769 void __iomem *ioaddr = tp->mmio_addr; |
|
2770 unsigned long flags; |
|
2771 |
|
2772 pci_save_state (pdev); |
|
2773 |
|
2774 if (tp->ecdev || !netif_running (dev)) |
|
2775 return 0; |
|
2776 |
|
2777 netif_device_detach (dev); |
|
2778 |
|
2779 spin_lock_irqsave (&tp->lock, flags); |
|
2780 |
|
2781 /* Disable interrupts, stop Tx and Rx. */ |
|
2782 RTL_W16 (IntrMask, 0); |
|
2783 RTL_W8 (ChipCmd, 0); |
|
2784 |
|
2785 /* Update the error counts. */ |
|
2786 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); |
|
2787 RTL_W32 (RxMissed, 0); |
|
2788 |
|
2789 spin_unlock_irqrestore (&tp->lock, flags); |
|
2790 |
|
2791 pci_set_power_state (pdev, PCI_D3hot); |
|
2792 |
|
2793 return 0; |
|
2794 } |
|
2795 |
|
2796 |
|
2797 static int rtl8139_resume (struct pci_dev *pdev) |
|
2798 { |
|
2799 struct net_device *dev = pci_get_drvdata (pdev); |
|
2800 struct rtl8139_private *tp = netdev_priv(dev); |
|
2801 |
|
2802 pci_restore_state (pdev); |
|
2803 if (tp->ecdev || !netif_running (dev)) |
|
2804 return 0; |
|
2805 pci_set_power_state (pdev, PCI_D0); |
|
2806 rtl8139_init_ring (dev); |
|
2807 rtl8139_hw_start (dev); |
|
2808 netif_device_attach (dev); |
|
2809 return 0; |
|
2810 } |
|
2811 |
|
2812 #endif /* CONFIG_PM */ |
|
2813 |
|
2814 |
|
2815 static struct pci_driver rtl8139_pci_driver = { |
|
2816 .name = DRV_NAME, |
|
2817 .id_table = rtl8139_pci_tbl, |
|
2818 .probe = rtl8139_init_one, |
|
2819 .remove = rtl8139_remove_one, |
|
2820 #ifdef CONFIG_PM |
|
2821 .suspend = rtl8139_suspend, |
|
2822 .resume = rtl8139_resume, |
|
2823 #endif /* CONFIG_PM */ |
|
2824 }; |
|
2825 |
|
2826 |
|
2827 static int __init rtl8139_init_module (void) |
|
2828 { |
|
2829 /* when we're a module, we always print a version message, |
|
2830 * even if no 8139 board is found. |
|
2831 */ |
|
2832 #ifdef MODULE |
|
2833 pr_info(RTL8139_DRIVER_NAME "\n"); |
|
2834 #endif |
|
2835 |
|
2836 return pci_register_driver(&rtl8139_pci_driver); |
|
2837 } |
|
2838 |
|
2839 |
|
2840 static void __exit rtl8139_cleanup_module (void) |
|
2841 { |
|
2842 pci_unregister_driver (&rtl8139_pci_driver); |
|
2843 } |
|
2844 |
|
2845 |
|
2846 module_init(rtl8139_init_module); |
|
2847 module_exit(rtl8139_cleanup_module); |