1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *****************************************************************************/

    29 

    30 /**

    31    \file

    32    EtherCAT driver for RTL8139-compatible NICs.

    33 */

    34 

    35 /*****************************************************************************/

    36 

    37 /*

    38   Former documentation:

    39 

    40 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41 

    42 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43 	Copyright 2000-2002 Jeff Garzik

    44 

    45 	Much code comes from Donald Becker's rtl8139.c driver,

    46 	versions 1.13 and older.  This driver was originally based

    47 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48 

    49 	-----<snip>-----

    50 

    51         	Written 1997-2001 by Donald Becker.

    52 		This software may be used and distributed according to the

    53 		terms of the GNU General Public License (GPL), incorporated

    54 		herein by reference.  Drivers based on or derived from this

    55 		code fall under the GPL and must retain the authorship,

    56 		copyright and license notice.  This file is not a complete

    57 		program and may only be used when the entire operating

    58 		system is licensed under the GPL.

    59 

    60 		This driver is for boards based on the RTL8129 and RTL8139

    61 		PCI ethernet chips.

    62 

    63 		The author may be reached as becker@scyld.com, or C/O Scyld

    64 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65 		MD 21403

    66 

    67 		Support and updates available at

    68 		http://www.scyld.com/network/rtl8139.html

    69 

    70 		Twister-tuning table provided by Kinston

    71 		<shangh@realtek.com.tw>.

    72 

    73 	-----<snip>-----

    74 

    75 	This software may be used and distributed according to the terms

    76 	of the GNU General Public License, incorporated herein by reference.

    77 

    78 	Contributors:

    79 

    80 		Donald Becker - he wrote the original driver, kudos to him!

    81 		(but please don't e-mail him for support, this isn't his driver)

    82 

    83 		Tigran Aivazian - bug fixes, skbuff free cleanup

    84 

    85 		Martin Mares - suggestions for PCI cleanup

    86 

    87 		David S. Miller - PCI DMA and softnet updates

    88 

    89 		Ernst Gill - fixes ported from BSD driver

    90 

    91 		Daniel Kobras - identified specific locations of

    92 			posted MMIO write bugginess

    93 

    94 		Gerard Sharp - bug fix, testing and feedback

    95 

    96 		David Ford - Rx ring wrap fix

    97 

    98 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    99 		to find and fix a crucial bug on older chipsets.

   100 

   101 		Donald Becker/Chris Butterworth/Marcus Westergren -

   102 		Noticed various Rx packet size-related buglets.

   103 

   104 		Santiago Garcia Mantinan - testing and feedback

   105 

   106 		Jens David - 2.2.x kernel backports

   107 

   108 		Martin Dennett - incredibly helpful insight on undocumented

   109 		features of the 8139 chips

   110 

   111 		Jean-Jacques Michel - bug fix

   112 

   113 		Tobias Ringström - Rx interrupt status checking suggestion

   114 

   115 		Andrew Morton - Clear blocked signals, avoid

   116 		buffer overrun setting current->comm.

   117 

   118 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   119 

   120 		Robert Kuebel - Save kernel thread from dying on any signal.

   121 

   122 	Submitting bug reports:

   123 

   124 		"rtl8139-diag -mmmaaavvveefN" output

   125 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   126 

   127 */

   128 

   129 #define DRV_NAME	"ec_8139too"

   130 #define DRV_VERSION	"0.9.28"

   131 

   132 

   133 #include <linux/module.h>

   134 #include <linux/kernel.h>

   135 #include <linux/compiler.h>

   136 #include <linux/pci.h>

   137 #include <linux/init.h>

   138 #include <linux/netdevice.h>

   139 #include <linux/etherdevice.h>

   140 #include <linux/rtnetlink.h>

   141 #include <linux/delay.h>

   142 #include <linux/ethtool.h>

   143 #include <linux/mii.h>

   144 #include <linux/completion.h>

   145 #include <linux/crc32.h>

   146 #include <linux/io.h>

   147 #include <linux/uaccess.h>

   148 #include <asm/irq.h>

   149 

   150 #include "../globals.h"

   151 #include "ecdev.h"

   152 

   153 #define RTL8139_DRIVER_NAME DRV_NAME \

   154                             " EtherCAT-capable Fast Ethernet driver " \

   155                             DRV_VERSION ", master " EC_MASTER_VERSION

   156 

   157 #define PFX DRV_NAME ": "

   158 

   159 /* Default Message level */

   160 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   161                                  NETIF_MSG_PROBE  | \

   162                                  NETIF_MSG_LINK)

   163 

   164 

   165 /* define to 1, 2 or 3 to enable copious debugging info */

   166 #define RTL8139_DEBUG 0

   167 

   168 /* define to 1 to disable lightweight runtime debugging checks */

   169 #undef RTL8139_NDEBUG

   170 

   171 

   172 #if RTL8139_DEBUG

   173 /* note: prints function name for you */

   174 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)

   175 #else

   176 #  define DPRINTK(fmt, args...)

   177 #endif

   178 

   179 #ifdef RTL8139_NDEBUG

   180 #  define assert(expr) do {} while (0)

   181 #else

   182 #  define assert(expr) \

   183         if(unlikely(!(expr))) {				        \

   184         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   185 	#expr, __FILE__, __func__, __LINE__);			\

   186         }

   187 #endif

   188 

   189 

   190 /* A few user-configurable values. */

   191 /* media options */

   192 #define MAX_UNITS 8

   193 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   194 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   195 

   196 /* Whether to use MMIO or PIO. Default to MMIO. */

   197 #ifdef CONFIG_8139TOO_PIO

   198 static int use_io = 1;

   199 #else

   200 static int use_io = 0;

   201 #endif

   202 

   203 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   204    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   205 static int multicast_filter_limit = 32;

   206 

   207 /* bitmapped message enable number */

   208 static int debug = -1;

   209 

   210 /*

   211  * Receive ring size

   212  * Warning: 64K ring has hardware issues and may lock up.

   213  */

   214 #if defined(CONFIG_SH_DREAMCAST)

   215 #define RX_BUF_IDX 0	/* 8K ring */

   216 #else

   217 #define RX_BUF_IDX	2	/* 32K ring */

   218 #endif

   219 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   220 #define RX_BUF_PAD	16

   221 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   222 

   223 #if RX_BUF_LEN == 65536

   224 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   225 #else

   226 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   227 #endif

   228 

   229 /* Number of Tx descriptor registers. */

   230 #define NUM_TX_DESC	4

   231 

   232 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   233 #define MAX_ETH_FRAME_SIZE	1536

   234 

   235 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   236 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   237 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   238 

   239 /* PCI Tuning Parameters

   240    Threshold is bytes transferred to chip before transmission starts. */

   241 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   242 

   243 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   244 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   245 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   246 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   247 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   248 

   249 /* Operational parameters that usually are not changed. */

   250 /* Time in jiffies before concluding the transmitter is hung. */

   251 #define TX_TIMEOUT  (6*HZ)

   252 

   253 

   254 enum {

   255 	HAS_MII_XCVR = 0x010000,

   256 	HAS_CHIP_XCVR = 0x020000,

   257 	HAS_LNK_CHNG = 0x040000,

   258 };

   259 

   260 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   261 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   262 #define RTL_MIN_IO_SIZE 0x80

   263 #define RTL8139B_IO_SIZE 256

   264 

   265 #define RTL8129_CAPS	HAS_MII_XCVR

   266 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   267 

   268 typedef enum {

   269 	RTL8139 = 0,

   270 	RTL8129,

   271 } board_t;

   272 

   273 

   274 /* indexed by board_t, above */

   275 static const struct {

   276 	const char *name;

   277 	u32 hw_flags;

   278 } board_info[] __devinitdata = {

   279 	{ "RealTek RTL8139", RTL8139_CAPS },

   280 	{ "RealTek RTL8129", RTL8129_CAPS },

   281 };

   282 

   283 

   284 static struct pci_device_id rtl8139_pci_tbl[] = {

   285 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 

   305 #ifdef CONFIG_SH_SECUREEDGE5410

   306 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   307 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308 #endif

   309 #ifdef CONFIG_8139TOO_8129

   310 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   311 #endif

   312 

   313 	/* some crazy cards report invalid vendor ids like

   314 	 * 0x0001 here.  The other ids are valid and constant,

   315 	 * so we simply don't match on the main vendor id.

   316 	 */

   317 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   318 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   319 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   320 

   321 	{0,}

   322 };

   323 

   324 /* prevent driver from being loaded automatically */

   325 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   326 

   327 static struct {

   328 	const char str[ETH_GSTRING_LEN];

   329 } ethtool_stats_keys[] = {

   330 	{ "early_rx" },

   331 	{ "tx_buf_mapped" },

   332 	{ "tx_timeouts" },

   333 	{ "rx_lost_in_ring" },

   334 };

   335 

   336 /* The rest of these values should never change. */

   337 

   338 /* Symbolic offsets to registers. */

   339 enum RTL8139_registers {

   340 	MAC0		= 0,	 /* Ethernet hardware address. */

   341 	MAR0		= 8,	 /* Multicast filter. */

   342 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   343 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   344 	RxBuf		= 0x30,

   345 	ChipCmd		= 0x37,

   346 	RxBufPtr	= 0x38,

   347 	RxBufAddr	= 0x3A,

   348 	IntrMask	= 0x3C,

   349 	IntrStatus	= 0x3E,

   350 	TxConfig	= 0x40,

   351 	RxConfig	= 0x44,

   352 	Timer		= 0x48,	 /* A general-purpose counter. */

   353 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   354 	Cfg9346		= 0x50,

   355 	Config0		= 0x51,

   356 	Config1		= 0x52,

   357 	FlashReg	= 0x54,

   358 	MediaStatus	= 0x58,

   359 	Config3		= 0x59,

   360 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   361 	HltClk		= 0x5B,

   362 	MultiIntr	= 0x5C,

   363 	TxSummary	= 0x60,

   364 	BasicModeCtrl	= 0x62,

   365 	BasicModeStatus	= 0x64,

   366 	NWayAdvert	= 0x66,

   367 	NWayLPAR	= 0x68,

   368 	NWayExpansion	= 0x6A,

   369 	/* Undocumented registers, but required for proper operation. */

   370 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   371 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   372 	PARA78		= 0x78,

   373 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   374 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   375 };

   376 

   377 enum ClearBitMasks {

   378 	MultiIntrClear	= 0xF000,

   379 	ChipCmdClear	= 0xE2,

   380 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   381 };

   382 

   383 enum ChipCmdBits {

   384 	CmdReset	= 0x10,

   385 	CmdRxEnb	= 0x08,

   386 	CmdTxEnb	= 0x04,

   387 	RxBufEmpty	= 0x01,

   388 };

   389 

   390 /* Interrupt register bits, using my own meaningful names. */

   391 enum IntrStatusBits {

   392 	PCIErr		= 0x8000,

   393 	PCSTimeout	= 0x4000,

   394 	RxFIFOOver	= 0x40,

   395 	RxUnderrun	= 0x20,

   396 	RxOverflow	= 0x10,

   397 	TxErr		= 0x08,

   398 	TxOK		= 0x04,

   399 	RxErr		= 0x02,

   400 	RxOK		= 0x01,

   401 

   402 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   403 };

   404 

   405 enum TxStatusBits {

   406 	TxHostOwns	= 0x2000,

   407 	TxUnderrun	= 0x4000,

   408 	TxStatOK	= 0x8000,

   409 	TxOutOfWindow	= 0x20000000,

   410 	TxAborted	= 0x40000000,

   411 	TxCarrierLost	= 0x80000000,

   412 };

   413 enum RxStatusBits {

   414 	RxMulticast	= 0x8000,

   415 	RxPhysical	= 0x4000,

   416 	RxBroadcast	= 0x2000,

   417 	RxBadSymbol	= 0x0020,

   418 	RxRunt		= 0x0010,

   419 	RxTooLong	= 0x0008,

   420 	RxCRCErr	= 0x0004,

   421 	RxBadAlign	= 0x0002,

   422 	RxStatusOK	= 0x0001,

   423 };

   424 

   425 /* Bits in RxConfig. */

   426 enum rx_mode_bits {

   427 	AcceptErr	= 0x20,

   428 	AcceptRunt	= 0x10,

   429 	AcceptBroadcast	= 0x08,

   430 	AcceptMulticast	= 0x04,

   431 	AcceptMyPhys	= 0x02,

   432 	AcceptAllPhys	= 0x01,

   433 };

   434 

   435 /* Bits in TxConfig. */

   436 enum tx_config_bits {

   437         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   438         TxIFGShift	= 24,

   439         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   440         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   441         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   442         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   443 

   444 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   445 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   446 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   447 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   448 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   449 

   450 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   451 };

   452 

   453 /* Bits in Config1 */

   454 enum Config1Bits {

   455 	Cfg1_PM_Enable	= 0x01,

   456 	Cfg1_VPD_Enable	= 0x02,

   457 	Cfg1_PIO	= 0x04,

   458 	Cfg1_MMIO	= 0x08,

   459 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   460 	Cfg1_Driver_Load = 0x20,

   461 	Cfg1_LED0	= 0x40,

   462 	Cfg1_LED1	= 0x80,

   463 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   464 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   465 };

   466 

   467 /* Bits in Config3 */

   468 enum Config3Bits {

   469 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   470 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   471 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   472 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   473 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   474 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   475 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   476 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   477 };

   478 

   479 /* Bits in Config4 */

   480 enum Config4Bits {

   481 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   482 };

   483 

   484 /* Bits in Config5 */

   485 enum Config5Bits {

   486 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   487 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   488 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   489 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   490 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   491 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   492 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   493 };

   494 

   495 enum RxConfigBits {

   496 	/* rx fifo threshold */

   497 	RxCfgFIFOShift	= 13,

   498 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   499 

   500 	/* Max DMA burst */

   501 	RxCfgDMAShift	= 8,

   502 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   503 

   504 	/* rx ring buffer length */

   505 	RxCfgRcv8K	= 0,

   506 	RxCfgRcv16K	= (1 << 11),

   507 	RxCfgRcv32K	= (1 << 12),

   508 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   509 

   510 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   511 	RxNoWrap	= (1 << 7),

   512 };

   513 

   514 /* Twister tuning parameters from RealTek.

   515    Completely undocumented, but required to tune bad links on some boards. */

   516 enum CSCRBits {

   517 	CSCR_LinkOKBit		= 0x0400,

   518 	CSCR_LinkChangeBit	= 0x0800,

   519 	CSCR_LinkStatusBits	= 0x0f000,

   520 	CSCR_LinkDownOffCmd	= 0x003c0,

   521 	CSCR_LinkDownCmd	= 0x0f3c0,

   522 };

   523 

   524 enum Cfg9346Bits {

   525 	Cfg9346_Lock	= 0x00,

   526 	Cfg9346_Unlock	= 0xC0,

   527 };

   528 

   529 typedef enum {

   530 	CH_8139	= 0,

   531 	CH_8139_K,

   532 	CH_8139A,

   533 	CH_8139A_G,

   534 	CH_8139B,

   535 	CH_8130,

   536 	CH_8139C,

   537 	CH_8100,

   538 	CH_8100B_8139D,

   539 	CH_8101,

   540 } chip_t;

   541 

   542 enum chip_flags {

   543 	HasHltClk	= (1 << 0),

   544 	HasLWake	= (1 << 1),

   545 };

   546 

   547 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   548 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   549 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   550 

   551 /* directly indexed by chip_t, above */

   552 static const struct {

   553 	const char *name;

   554 	u32 version; /* from RTL8139C/RTL8139D docs */

   555 	u32 flags;

   556 } rtl_chip_info[] = {

   557 	{ "RTL-8139",

   558 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   559 	  HasHltClk,

   560 	},

   561 

   562 	{ "RTL-8139 rev K",

   563 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   564 	  HasHltClk,

   565 	},

   566 

   567 	{ "RTL-8139A",

   568 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   569 	  HasHltClk, /* XXX undocumented? */

   570 	},

   571 

   572 	{ "RTL-8139A rev G",

   573 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   574 	  HasHltClk, /* XXX undocumented? */

   575 	},

   576 

   577 	{ "RTL-8139B",

   578 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   579 	  HasLWake,

   580 	},

   581 

   582 	{ "RTL-8130",

   583 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   584 	  HasLWake,

   585 	},

   586 

   587 	{ "RTL-8139C",

   588 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   589 	  HasLWake,

   590 	},

   591 

   592 	{ "RTL-8100",

   593 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   594  	  HasLWake,

   595  	},

   596 

   597 	{ "RTL-8100B/8139D",

   598 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   599 	  HasHltClk /* XXX undocumented? */

   600 	| HasLWake,

   601 	},

   602 

   603 	{ "RTL-8101",

   604 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   605 	  HasLWake,

   606 	},

   607 };

   608 

   609 struct rtl_extra_stats {

   610 	unsigned long early_rx;

   611 	unsigned long tx_buf_mapped;

   612 	unsigned long tx_timeouts;

   613 	unsigned long rx_lost_in_ring;

   614 };

   615 

   616 struct rtl8139_private {

   617 	void __iomem		*mmio_addr;

   618 	int			drv_flags;

   619 	struct pci_dev		*pci_dev;

   620 	u32			msg_enable;

   621 	struct napi_struct	napi;

   622 	struct net_device	*dev;

   623 

   624 	unsigned char		*rx_ring;

   625 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   626 	dma_addr_t		rx_ring_dma;

   627 

   628 	unsigned int		tx_flag;

   629 	unsigned long		cur_tx;

   630 	unsigned long		dirty_tx;

   631 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   632 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   633 	dma_addr_t		tx_bufs_dma;

   634 

   635 	signed char		phys[4];	/* MII device addresses. */

   636 

   637 				/* Twister tune state. */

   638 	char			twistie, twist_row, twist_col;

   639 

   640 	unsigned int		watchdog_fired : 1;

   641 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   642 	unsigned int		have_thread : 1;

   643 

   644 	spinlock_t		lock;

   645 	spinlock_t		rx_lock;

   646 

   647 	chip_t			chipset;

   648 	u32			rx_config;

   649 	struct rtl_extra_stats	xstats;

   650 

   651 	struct delayed_work	thread;

   652 

   653 	struct mii_if_info	mii;

   654 	unsigned int		regs_len;

   655 	unsigned long		fifo_copy_timeout;

   656     

   657 	ec_device_t *ecdev;

   658 };

   659 

   660 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   661 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   662 MODULE_LICENSE("GPL");

   663 MODULE_VERSION(EC_MASTER_VERSION);

   664 

   665 module_param(use_io, int, 0);

   666 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   667 module_param(multicast_filter_limit, int, 0);

   668 module_param_array(media, int, NULL, 0);

   669 module_param_array(full_duplex, int, NULL, 0);

   670 module_param(debug, int, 0);

   671 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   672 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   673 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   674 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   675 

   676 void ec_poll(struct net_device *);

   677 

   678 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   679 static int rtl8139_open (struct net_device *dev);

   680 static int mdio_read (struct net_device *dev, int phy_id, int location);

   681 static void mdio_write (struct net_device *dev, int phy_id, int location,

   682 			int val);

   683 static void rtl8139_start_thread(struct rtl8139_private *tp);

   684 static void rtl8139_tx_timeout (struct net_device *dev);

   685 static void rtl8139_init_ring (struct net_device *dev);

   686 static int rtl8139_start_xmit (struct sk_buff *skb,

   687 			       struct net_device *dev);

   688 #ifdef CONFIG_NET_POLL_CONTROLLER

   689 static void rtl8139_poll_controller(struct net_device *dev);

   690 #endif

   691 static int rtl8139_poll(struct napi_struct *napi, int budget);

   692 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   693 static int rtl8139_close (struct net_device *dev);

   694 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   695 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   696 static void rtl8139_set_rx_mode (struct net_device *dev);

   697 static void __set_rx_mode (struct net_device *dev);

   698 static void rtl8139_hw_start (struct net_device *dev);

   699 static void rtl8139_thread (struct work_struct *work);

   700 static void rtl8139_tx_timeout_task(struct work_struct *work);

   701 static const struct ethtool_ops rtl8139_ethtool_ops;

   702 

   703 /* write MMIO register, with flush */

   704 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   705 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   706 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   707 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   708 

   709 /* write MMIO register */

   710 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   711 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   712 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   713 

   714 /* read MMIO register */

   715 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   716 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   717 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   718 

   719 

   720 static const u16 rtl8139_intr_mask =

   721 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   722 	TxErr | TxOK | RxErr | RxOK;

   723 

   724 static const u16 rtl8139_norx_intr_mask =

   725 	PCIErr | PCSTimeout | RxUnderrun |

   726 	TxErr | TxOK | RxErr ;

   727 

   728 #if RX_BUF_IDX == 0

   729 static const unsigned int rtl8139_rx_config =

   730 	RxCfgRcv8K | RxNoWrap |

   731 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   732 	(RX_DMA_BURST << RxCfgDMAShift);

   733 #elif RX_BUF_IDX == 1

   734 static const unsigned int rtl8139_rx_config =

   735 	RxCfgRcv16K | RxNoWrap |

   736 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   737 	(RX_DMA_BURST << RxCfgDMAShift);

   738 #elif RX_BUF_IDX == 2

   739 static const unsigned int rtl8139_rx_config =

   740 	RxCfgRcv32K | RxNoWrap |

   741 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   742 	(RX_DMA_BURST << RxCfgDMAShift);

   743 #elif RX_BUF_IDX == 3

   744 static const unsigned int rtl8139_rx_config =

   745 	RxCfgRcv64K |

   746 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   747 	(RX_DMA_BURST << RxCfgDMAShift);

   748 #else

   749 #error "Invalid configuration for 8139_RXBUF_IDX"

   750 #endif

   751 

   752 static const unsigned int rtl8139_tx_config =

   753 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   754 

   755 static void __rtl8139_cleanup_dev (struct net_device *dev)

   756 {

   757 	struct rtl8139_private *tp = netdev_priv(dev);

   758 	struct pci_dev *pdev;

   759 

   760 	assert (dev != NULL);

   761 	assert (tp->pci_dev != NULL);

   762 	pdev = tp->pci_dev;

   763 

   764 	if (tp->mmio_addr)

   765 		pci_iounmap (pdev, tp->mmio_addr);

   766 

   767 	/* it's ok to call this even if we have no regions to free */

   768 	pci_release_regions (pdev);

   769 

   770 	free_netdev(dev);

   771 	pci_set_drvdata (pdev, NULL);

   772 }

   773 

   774 

   775 static void rtl8139_chip_reset (void __iomem *ioaddr)

   776 {

   777 	int i;

   778 

   779 	/* Soft reset the chip. */

   780 	RTL_W8 (ChipCmd, CmdReset);

   781 

   782 	/* Check that the chip has finished the reset. */

   783 	for (i = 1000; i > 0; i--) {

   784 		barrier();

   785 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   786 			break;

   787 		udelay (10);

   788 	}

   789 }

   790 

   791 

   792 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   793 					 struct net_device **dev_out)

   794 {

   795 	void __iomem *ioaddr;

   796 	struct net_device *dev;

   797 	struct rtl8139_private *tp;

   798 	u8 tmp8;

   799 	int rc, disable_dev_on_err = 0;

   800 	unsigned int i;

   801 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   802 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   803 	u32 version;

   804 

   805 	assert (pdev != NULL);

   806 

   807 	*dev_out = NULL;

   808 

   809 	/* dev and priv zeroed in alloc_etherdev */

   810 	dev = alloc_etherdev (sizeof (*tp));

   811 	if (dev == NULL) {

   812 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   813 		return -ENOMEM;

   814 	}

   815 	SET_NETDEV_DEV(dev, &pdev->dev);

   816 

   817 	tp = netdev_priv(dev);

   818 	tp->pci_dev = pdev;

   819 

   820 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   821 	rc = pci_enable_device (pdev);

   822 	if (rc)

   823 		goto err_out;

   824 

   825 	pio_start = pci_resource_start (pdev, 0);

   826 	pio_end = pci_resource_end (pdev, 0);

   827 	pio_flags = pci_resource_flags (pdev, 0);

   828 	pio_len = pci_resource_len (pdev, 0);

   829 

   830 	mmio_start = pci_resource_start (pdev, 1);

   831 	mmio_end = pci_resource_end (pdev, 1);

   832 	mmio_flags = pci_resource_flags (pdev, 1);

   833 	mmio_len = pci_resource_len (pdev, 1);

   834 

   835 	/* set this immediately, we need to know before

   836 	 * we talk to the chip directly */

   837 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   838 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   839 

   840 retry:

   841 	if (use_io) {

   842 		/* make sure PCI base addr 0 is PIO */

   843 		if (!(pio_flags & IORESOURCE_IO)) {

   844 			dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   845 			rc = -ENODEV;

   846 			goto err_out;

   847 		}

   848 		/* check for weird/broken PCI region reporting */

   849 		if (pio_len < RTL_MIN_IO_SIZE) {

   850 			dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   851 			rc = -ENODEV;

   852 			goto err_out;

   853 		}

   854 	} else {

   855 		/* make sure PCI base addr 1 is MMIO */

   856 		if (!(mmio_flags & IORESOURCE_MEM)) {

   857 			dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   858 			rc = -ENODEV;

   859 			goto err_out;

   860 		}

   861 		if (mmio_len < RTL_MIN_IO_SIZE) {

   862 			dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   863 			rc = -ENODEV;

   864 			goto err_out;

   865 		}

   866 	}

   867 

   868 	rc = pci_request_regions (pdev, DRV_NAME);

   869 	if (rc)

   870 		goto err_out;

   871 	disable_dev_on_err = 1;

   872 

   873 	/* enable PCI bus-mastering */

   874 	pci_set_master (pdev);

   875 

   876 	if (use_io) {

   877 		ioaddr = pci_iomap(pdev, 0, 0);

   878 		if (!ioaddr) {

   879 			dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   880 			rc = -EIO;

   881 			goto err_out;

   882 		}

   883 		dev->base_addr = pio_start;

   884 		tp->regs_len = pio_len;

   885 	} else {

   886 		/* ioremap MMIO region */

   887 		ioaddr = pci_iomap(pdev, 1, 0);

   888 		if (ioaddr == NULL) {

   889 			dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");

   890 			pci_release_regions(pdev);

   891 			use_io = 1;

   892 			goto retry;

   893 		}

   894 		dev->base_addr = (long) ioaddr;

   895 		tp->regs_len = mmio_len;

   896 	}

   897 	tp->mmio_addr = ioaddr;

   898 

   899 	/* Bring old chips out of low-power mode. */

   900 	RTL_W8 (HltClk, 'R');

   901 

   902 	/* check for missing/broken hardware */

   903 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   904 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   905 		rc = -EIO;

   906 		goto err_out;

   907 	}

   908 

   909 	/* identify chip attached to board */

   910 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   911 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   912 		if (version == rtl_chip_info[i].version) {

   913 			tp->chipset = i;

   914 			goto match;

   915 		}

   916 

   917 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   918 	dev_printk (KERN_DEBUG, &pdev->dev,

   919 		    "unknown chip version, assuming RTL-8139\n");

   920 	dev_printk (KERN_DEBUG, &pdev->dev,

   921 		    "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   922 	tp->chipset = 0;

   923 

   924 match:

   925 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   926 		 version, i, rtl_chip_info[i].name);

   927 

   928 	if (tp->chipset >= CH_8139B) {

   929 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   930 		DPRINTK("PCI PM wakeup\n");

   931 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   932 		    (tmp8 & LWAKE))

   933 			new_tmp8 &= ~LWAKE;

   934 		new_tmp8 |= Cfg1_PM_Enable;

   935 		if (new_tmp8 != tmp8) {

   936 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   937 			RTL_W8 (Config1, tmp8);

   938 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   939 		}

   940 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   941 			tmp8 = RTL_R8 (Config4);

   942 			if (tmp8 & LWPTN) {

   943 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   944 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   945 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   946 			}

   947 		}

   948 	} else {

   949 		DPRINTK("Old chip wakeup\n");

   950 		tmp8 = RTL_R8 (Config1);

   951 		tmp8 &= ~(SLEEP | PWRDN);

   952 		RTL_W8 (Config1, tmp8);

   953 	}

   954 

   955 	rtl8139_chip_reset (ioaddr);

   956 

   957 	*dev_out = dev;

   958 	return 0;

   959 

   960 err_out:

   961 	__rtl8139_cleanup_dev (dev);

   962 	if (disable_dev_on_err)

   963 		pci_disable_device (pdev);

   964 	return rc;

   965 }

   966 

   967 

   968 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   969 				       const struct pci_device_id *ent)

   970 {

   971 	struct net_device *dev = NULL;

   972 	struct rtl8139_private *tp;

   973 	int i, addr_len, option;

   974 	void __iomem *ioaddr;

   975 	static int board_idx = -1;

   976 	DECLARE_MAC_BUF(mac);

   977 

   978 	assert (pdev != NULL);

   979 	assert (ent != NULL);

   980 

   981 	board_idx++;

   982 

   983 	/* when we're built into the kernel, the driver version message

   984 	 * is only printed if at least one 8139 board has been found

   985 	 */

   986 #ifndef MODULE

   987 	{

   988 		static int printed_version;

   989 		if (!printed_version++)

   990 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

   991 	}

   992 #endif

   993 

   994 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

   995 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

   996 		dev_info(&pdev->dev,

   997 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

   998 		       	   pdev->vendor, pdev->device, pdev->revision);

   999 		dev_info(&pdev->dev,

  1000 			   "Use the \"8139cp\" driver for improved performance and stability.\n");

  1001 	}

  1002 

  1003 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1004 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1005 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1006 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1007 		printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");

  1008 		use_io = 1;

  1009 	}

  1010 

  1011 	i = rtl8139_init_board (pdev, &dev);

  1012 	if (i < 0)

  1013 		return i;

  1014 

  1015 	assert (dev != NULL);

  1016 	tp = netdev_priv(dev);

  1017 	tp->dev = dev;

  1018 

  1019 	ioaddr = tp->mmio_addr;

  1020 	assert (ioaddr != NULL);

  1021 

  1022 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1023 	for (i = 0; i < 3; i++)

  1024 		((__le16 *) (dev->dev_addr))[i] =

  1025 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1026 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1027 

  1028 	/* The Rtl8139-specific entries in the device structure. */

  1029 	dev->open = rtl8139_open;

  1030 	dev->hard_start_xmit = rtl8139_start_xmit;

  1031 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1032 	dev->stop = rtl8139_close;

  1033 	dev->get_stats = rtl8139_get_stats;

  1034 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1035 	dev->do_ioctl = netdev_ioctl;

  1036 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1037 	dev->tx_timeout = rtl8139_tx_timeout;

  1038 	dev->watchdog_timeo = TX_TIMEOUT;

  1039 #ifdef CONFIG_NET_POLL_CONTROLLER

  1040 	dev->poll_controller = rtl8139_poll_controller;

  1041 #endif

  1042 

  1043 	/* note: the hardware is not capable of sg/csum/highdma, however

  1044 	 * through the use of skb_copy_and_csum_dev we enable these

  1045 	 * features

  1046 	 */

  1047 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1048 

  1049 	dev->irq = pdev->irq;

  1050 

  1051 	/* tp zeroed and aligned in alloc_etherdev */

  1052 	tp = netdev_priv(dev);

  1053 

  1054 	/* note: tp->chipset set in rtl8139_init_board */

  1055 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1056 	tp->mmio_addr = ioaddr;

  1057 	tp->msg_enable =

  1058 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1059 	spin_lock_init (&tp->lock);

  1060 	spin_lock_init (&tp->rx_lock);

  1061 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1062 	tp->mii.dev = dev;

  1063 	tp->mii.mdio_read = mdio_read;

  1064 	tp->mii.mdio_write = mdio_write;

  1065 	tp->mii.phy_id_mask = 0x3f;

  1066 	tp->mii.reg_num_mask = 0x1f;

  1067 

  1068 	/* dev is fully set up and ready to use now */

  1069     

  1070 	// offer device to EtherCAT master module

  1071 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1072 

  1073 	if (!tp->ecdev) {

  1074 		DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);

  1075 		i = register_netdev (dev);

  1076 		if (i) goto err_out;

  1077 	}

  1078 

  1079 	pci_set_drvdata (pdev, dev);

  1080 

  1081 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1082 		"%s, IRQ %d\n",

  1083 		dev->name,

  1084 		board_info[ent->driver_data].name,

  1085 		dev->base_addr,

  1086 		print_mac(mac, dev->dev_addr),

  1087 		dev->irq);

  1088 

  1089 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1090 		dev->name, rtl_chip_info[tp->chipset].name);

  1091 

  1092 	/* Find the connected MII xcvrs.

  1093 	   Doing this in open() would allow detecting external xcvrs later, but

  1094 	   takes too much time. */

  1095 #ifdef CONFIG_8139TOO_8129

  1096 	if (tp->drv_flags & HAS_MII_XCVR) {

  1097 		int phy, phy_idx = 0;

  1098 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1099 			int mii_status = mdio_read(dev, phy, 1);

  1100 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1101 				u16 advertising = mdio_read(dev, phy, 4);

  1102 				tp->phys[phy_idx++] = phy;

  1103 				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1104 					   "advertising %4.4x.\n",

  1105 					   dev->name, phy, mii_status, advertising);

  1106 			}

  1107 		}

  1108 		if (phy_idx == 0) {

  1109 			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "

  1110 				   "transceiver.\n",

  1111 				   dev->name);

  1112 			tp->phys[0] = 32;

  1113 		}

  1114 	} else

  1115 #endif

  1116 		tp->phys[0] = 32;

  1117 	tp->mii.phy_id = tp->phys[0];

  1118 

  1119 	/* The lower four bits are the media type. */

  1120 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1121 	if (option > 0) {

  1122 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1123 		tp->default_port = option & 0xFF;

  1124 		if (tp->default_port)

  1125 			tp->mii.force_media = 1;

  1126 	}

  1127 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1128 		tp->mii.full_duplex = full_duplex[board_idx];

  1129 	if (tp->mii.full_duplex) {

  1130 		printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);

  1131 		/* Changing the MII-advertised media because might prevent

  1132 		   re-connection. */

  1133 		tp->mii.force_media = 1;

  1134 	}

  1135 	if (tp->default_port) {