1

/*

     2

     3

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

     4

     5

	Maintained by Jeff Garzik <jgarzik@pobox.com>

     6

	Copyright 2000-2002 Jeff Garzik

     7

     8

	Much code comes from Donald Becker's rtl8139.c driver,

     9

	versions 1.13 and older.  This driver was originally based

    10

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    11

    12

	-----<snip>-----

    13

    14

        	Written 1997-2001 by Donald Becker.

    15

		This software may be used and distributed according to the

    16

		terms of the GNU General Public License (GPL), incorporated

    17

		herein by reference.  Drivers based on or derived from this

    18

		code fall under the GPL and must retain the authorship,

    19

		copyright and license notice.  This file is not a complete

    20

		program and may only be used when the entire operating

    21

		system is licensed under the GPL.

    22

    23

		This driver is for boards based on the RTL8129 and RTL8139

    24

		PCI ethernet chips.

    25

    26

		The author may be reached as becker@scyld.com, or C/O Scyld

    27

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    28

		MD 21403

    29

    30

		Support and updates available at

    31

		http://www.scyld.com/network/rtl8139.html

    32

    33

		Twister-tuning table provided by Kinston

    34

		<shangh@realtek.com.tw>.

    35

    36

	-----<snip>-----

    37

    38

	This software may be used and distributed according to the terms

    39

	of the GNU General Public License, incorporated herein by reference.

    40

    41

	Contributors:

    42

    43

		Donald Becker - he wrote the original driver, kudos to him!

    44

		(but please don't e-mail him for support, this isn't his driver)

    45

    46

		Tigran Aivazian - bug fixes, skbuff free cleanup

    47

    48

		Martin Mares - suggestions for PCI cleanup

    49

    50

		David S. Miller - PCI DMA and softnet updates

    51

    52

		Ernst Gill - fixes ported from BSD driver

    53

    54

		Daniel Kobras - identified specific locations of

    55

			posted MMIO write bugginess

    56

    57

		Gerard Sharp - bug fix, testing and feedback

    58

    59

		David Ford - Rx ring wrap fix

    60

    61

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    62

		to find and fix a crucial bug on older chipsets.

    63

    64

		Donald Becker/Chris Butterworth/Marcus Westergren -

    65

		Noticed various Rx packet size-related buglets.

    66

    67

		Santiago Garcia Mantinan - testing and feedback

    68

    69

		Jens David - 2.2.x kernel backports

    70

    71

		Martin Dennett - incredibly helpful insight on undocumented

    72

		features of the 8139 chips

    73

    74

		Jean-Jacques Michel - bug fix

    75

    76

		Tobias Ringström - Rx interrupt status checking suggestion

    77

    78

		Andrew Morton - Clear blocked signals, avoid

    79

		buffer overrun setting current->comm.

    80

    81

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

    82

    83

		Robert Kuebel - Save kernel thread from dying on any signal.

    84

    85

	Submitting bug reports:

    86

    87

		"rtl8139-diag -mmmaaavvveefN" output

    88

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

    89

    90

*/

    91

    92

#define DRV_NAME	"8139too"

    93

#define DRV_VERSION	"0.9.28"

    94

    95

    96

#include <linux/module.h>

    97

#include <linux/kernel.h>

    98

#include <linux/compiler.h>

    99

#include <linux/pci.h>

   100

#include <linux/init.h>

   101

#include <linux/netdevice.h>

   102

#include <linux/etherdevice.h>

   103

#include <linux/rtnetlink.h>

   104

#include <linux/delay.h>

   105

#include <linux/ethtool.h>

   106

#include <linux/mii.h>

   107

#include <linux/completion.h>

   108

#include <linux/crc32.h>

   109

#include <linux/io.h>

   110

#include <linux/uaccess.h>

   111

#include <asm/irq.h>

   112

   113

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   114

#define PFX DRV_NAME ": "

   115

   116

/* Default Message level */

   117

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   118

                                 NETIF_MSG_PROBE  | \

   119

                                 NETIF_MSG_LINK)

   120

   121

   122

/* define to 1, 2 or 3 to enable copious debugging info */

   123

#define RTL8139_DEBUG 0

   124

   125

/* define to 1 to disable lightweight runtime debugging checks */

   126

#undef RTL8139_NDEBUG

   127

   128

   129

#ifdef RTL8139_NDEBUG

   130

#  define assert(expr) do {} while (0)

   131

#else

   132

#  define assert(expr) \

   133

        if(unlikely(!(expr))) {				        \

   134

        pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   135

	#expr, __FILE__, __func__, __LINE__);			\

   136

        }

   137

#endif

   138

   139

   140

/* A few user-configurable values. */

   141

/* media options */

   142

#define MAX_UNITS 8

   143

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   144

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   145

   146

/* Whether to use MMIO or PIO. Default to MMIO. */

   147

#ifdef CONFIG_8139TOO_PIO

   148

static int use_io = 1;

   149

#else

   150

static int use_io = 0;

   151

#endif

   152

   153

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   154

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   155

static int multicast_filter_limit = 32;

   156

   157

/* bitmapped message enable number */

   158

static int debug = -1;

   159

   160

/*

   161

 * Receive ring size

   162

 * Warning: 64K ring has hardware issues and may lock up.

   163

 */

   164

#if defined(CONFIG_SH_DREAMCAST)

   165

#define RX_BUF_IDX 0	/* 8K ring */

   166

#else

   167

#define RX_BUF_IDX	2	/* 32K ring */

   168

#endif

   169

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   170

#define RX_BUF_PAD	16

   171

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   172

   173

#if RX_BUF_LEN == 65536

   174

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   175

#else

   176

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   177

#endif

   178

   179

/* Number of Tx descriptor registers. */

   180

#define NUM_TX_DESC	4

   181

   182

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   183

#define MAX_ETH_FRAME_SIZE	1536

   184

   185

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   186

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   187

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   188

   189

/* PCI Tuning Parameters

   190

   Threshold is bytes transferred to chip before transmission starts. */

   191

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   192

   193

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   194

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   195

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   196

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   197

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   198

   199

/* Operational parameters that usually are not changed. */

   200

/* Time in jiffies before concluding the transmitter is hung. */

   201

#define TX_TIMEOUT  (6*HZ)

   202

   203

   204

enum {

   205

	HAS_MII_XCVR = 0x010000,

   206

	HAS_CHIP_XCVR = 0x020000,

   207

	HAS_LNK_CHNG = 0x040000,

   208

};

   209

   210

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   211

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   212

#define RTL_MIN_IO_SIZE 0x80

   213

#define RTL8139B_IO_SIZE 256

   214

   215

#define RTL8129_CAPS	HAS_MII_XCVR

   216

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   217

   218

typedef enum {

   219

	RTL8139 = 0,

   220

	RTL8129,

   221

} board_t;

   222

   223

   224

/* indexed by board_t, above */

   225

static const struct {

   226

	const char *name;

   227

	u32 hw_flags;

   228

} board_info[] __devinitdata = {

   229

	{ "RealTek RTL8139", RTL8139_CAPS },

   230

	{ "RealTek RTL8129", RTL8129_CAPS },

   231

};

   232

   233

   234

static struct pci_device_id rtl8139_pci_tbl[] = {

   235

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   236

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   237

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   238

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   239

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   240

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   241

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   242

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   243

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   244

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   245

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   246

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   247

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   248

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   249

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   250

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   251

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   252

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   253

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   254

   255

#ifdef CONFIG_SH_SECUREEDGE5410

   256

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   257

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   258

#endif

   259

#ifdef CONFIG_8139TOO_8129

   260

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   261

#endif

   262

   263

	/* some crazy cards report invalid vendor ids like

   264

	 * 0x0001 here.  The other ids are valid and constant,

   265

	 * so we simply don't match on the main vendor id.

   266

	 */

   267

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   268

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   269

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   270

   271

	{0,}

   272

};

   273

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   274

   275

static struct {

   276

	const char str[ETH_GSTRING_LEN];

   277

} ethtool_stats_keys[] = {

   278

	{ "early_rx" },

   279

	{ "tx_buf_mapped" },

   280

	{ "tx_timeouts" },

   281

	{ "rx_lost_in_ring" },

   282

};

   283

   284

/* The rest of these values should never change. */

   285

   286

/* Symbolic offsets to registers. */

   287

enum RTL8139_registers {

   288

	MAC0		= 0,	 /* Ethernet hardware address. */

   289

	MAR0		= 8,	 /* Multicast filter. */

   290

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   291

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   292

	RxBuf		= 0x30,

   293

	ChipCmd		= 0x37,

   294

	RxBufPtr	= 0x38,

   295

	RxBufAddr	= 0x3A,

   296

	IntrMask	= 0x3C,

   297

	IntrStatus	= 0x3E,

   298

	TxConfig	= 0x40,

   299

	RxConfig	= 0x44,

   300

	Timer		= 0x48,	 /* A general-purpose counter. */

   301

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   302

	Cfg9346		= 0x50,

   303

	Config0		= 0x51,

   304

	Config1		= 0x52,

   305

	TimerInt	= 0x54,

   306

	MediaStatus	= 0x58,

   307

	Config3		= 0x59,

   308

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   309

	HltClk		= 0x5B,

   310

	MultiIntr	= 0x5C,

   311

	TxSummary	= 0x60,

   312

	BasicModeCtrl	= 0x62,

   313

	BasicModeStatus	= 0x64,

   314

	NWayAdvert	= 0x66,

   315

	NWayLPAR	= 0x68,

   316

	NWayExpansion	= 0x6A,

   317

	/* Undocumented registers, but required for proper operation. */

   318

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   319

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   320

	PARA78		= 0x78,

   321

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   322

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   323

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   324

};

   325

   326

enum ClearBitMasks {

   327

	MultiIntrClear	= 0xF000,

   328

	ChipCmdClear	= 0xE2,

   329

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   330

};

   331

   332

enum ChipCmdBits {

   333

	CmdReset	= 0x10,

   334

	CmdRxEnb	= 0x08,

   335

	CmdTxEnb	= 0x04,

   336

	RxBufEmpty	= 0x01,

   337

};

   338

   339

/* Interrupt register bits, using my own meaningful names. */

   340

enum IntrStatusBits {

   341

	PCIErr		= 0x8000,

   342

	PCSTimeout	= 0x4000,

   343

	RxFIFOOver	= 0x40,

   344

	RxUnderrun	= 0x20,

   345

	RxOverflow	= 0x10,

   346

	TxErr		= 0x08,

   347

	TxOK		= 0x04,

   348

	RxErr		= 0x02,

   349

	RxOK		= 0x01,

   350

   351

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   352

};

   353

   354

enum TxStatusBits {

   355

	TxHostOwns	= 0x2000,

   356

	TxUnderrun	= 0x4000,

   357

	TxStatOK	= 0x8000,

   358

	TxOutOfWindow	= 0x20000000,

   359

	TxAborted	= 0x40000000,

   360

	TxCarrierLost	= 0x80000000,

   361

};

   362

enum RxStatusBits {

   363

	RxMulticast	= 0x8000,

   364

	RxPhysical	= 0x4000,

   365

	RxBroadcast	= 0x2000,

   366

	RxBadSymbol	= 0x0020,

   367

	RxRunt		= 0x0010,

   368

	RxTooLong	= 0x0008,

   369

	RxCRCErr	= 0x0004,

   370

	RxBadAlign	= 0x0002,

   371

	RxStatusOK	= 0x0001,

   372

};

   373

   374

/* Bits in RxConfig. */

   375

enum rx_mode_bits {

   376

	AcceptErr	= 0x20,

   377

	AcceptRunt	= 0x10,

   378

	AcceptBroadcast	= 0x08,

   379

	AcceptMulticast	= 0x04,

   380

	AcceptMyPhys	= 0x02,

   381

	AcceptAllPhys	= 0x01,

   382

};

   383

   384

/* Bits in TxConfig. */

   385

enum tx_config_bits {

   386

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   387

        TxIFGShift	= 24,

   388

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   389

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   390

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   391

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   392

   393

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   394

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   395

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   396

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   397

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   398

   399

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   400

};

   401

   402

/* Bits in Config1 */

   403

enum Config1Bits {

   404

	Cfg1_PM_Enable	= 0x01,

   405

	Cfg1_VPD_Enable	= 0x02,

   406

	Cfg1_PIO	= 0x04,

   407

	Cfg1_MMIO	= 0x08,

   408

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   409

	Cfg1_Driver_Load = 0x20,

   410

	Cfg1_LED0	= 0x40,

   411

	Cfg1_LED1	= 0x80,

   412

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   413

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   414

};

   415

   416

/* Bits in Config3 */

   417

enum Config3Bits {

   418

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   419

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   420

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   421

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   422

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   423

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   424

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   425

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   426

};

   427

   428

/* Bits in Config4 */

   429

enum Config4Bits {

   430

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   431

};

   432

   433

/* Bits in Config5 */

   434

enum Config5Bits {

   435

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   436

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   437

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   438

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   439

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   440

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   441

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   442

};

   443

   444

enum RxConfigBits {

   445

	/* rx fifo threshold */

   446

	RxCfgFIFOShift	= 13,

   447

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   448

   449

	/* Max DMA burst */

   450

	RxCfgDMAShift	= 8,

   451

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   452

   453

	/* rx ring buffer length */

   454

	RxCfgRcv8K	= 0,

   455

	RxCfgRcv16K	= (1 << 11),

   456

	RxCfgRcv32K	= (1 << 12),

   457

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   458

   459

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   460

	RxNoWrap	= (1 << 7),

   461

};

   462

   463

/* Twister tuning parameters from RealTek.

   464

   Completely undocumented, but required to tune bad links on some boards. */

   465

enum CSCRBits {

   466

	CSCR_LinkOKBit		= 0x0400,

   467

	CSCR_LinkChangeBit	= 0x0800,

   468

	CSCR_LinkStatusBits	= 0x0f000,

   469

	CSCR_LinkDownOffCmd	= 0x003c0,

   470

	CSCR_LinkDownCmd	= 0x0f3c0,

   471

};

   472

   473

enum Cfg9346Bits {

   474

	Cfg9346_Lock	= 0x00,

   475

	Cfg9346_Unlock	= 0xC0,

   476

};

   477

   478

typedef enum {

   479

	CH_8139	= 0,

   480

	CH_8139_K,

   481

	CH_8139A,

   482

	CH_8139A_G,

   483

	CH_8139B,

   484

	CH_8130,

   485

	CH_8139C,

   486

	CH_8100,

   487

	CH_8100B_8139D,

   488

	CH_8101,

   489

} chip_t;

   490

   491

enum chip_flags {

   492

	HasHltClk	= (1 << 0),

   493

	HasLWake	= (1 << 1),

   494

};

   495

   496

#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   497

	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   498

#define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   499

   500

/* directly indexed by chip_t, above */

   501

static const struct {

   502

	const char *name;

   503

	u32 version; /* from RTL8139C/RTL8139D docs */

   504

	u32 flags;

   505

} rtl_chip_info[] = {

   506

	{ "RTL-8139",

   507

	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   508

	  HasHltClk,

   509

	},

   510

   511

	{ "RTL-8139 rev K",

   512

	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   513

	  HasHltClk,

   514

	},

   515

   516

	{ "RTL-8139A",

   517

	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   518

	  HasHltClk, /* XXX undocumented? */

   519

	},

   520

   521

	{ "RTL-8139A rev G",

   522

	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   523

	  HasHltClk, /* XXX undocumented? */

   524

	},

   525

   526

	{ "RTL-8139B",

   527

	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   528

	  HasLWake,

   529

	},