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/******************************************************************************

     2

 *

     3

 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006-2008  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  Using the EtherCAT technology and brand is permitted in compliance with

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 *  the industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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    27

/**

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   \file

    29

   EtherCAT driver for RTL8139-compatible NICs.

    30

*/

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    32

/*****************************************************************************/

    33

    34

/*

    35

  Former documentation:

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    37

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    38

    39

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

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    42

	Much code comes from Donald Becker's rtl8139.c driver,

    43

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    45

    46

	-----<snip>-----

    47

    48

        	Written 1997-2001 by Donald Becker.

    49

		This software may be used and distributed according to the

    50

		terms of the GNU General Public License (GPL), incorporated

    51

		herein by reference.  Drivers based on or derived from this

    52

		code fall under the GPL and must retain the authorship,

    53

		copyright and license notice.  This file is not a complete

    54

		program and may only be used when the entire operating

    55

		system is licensed under the GPL.

    56

    57

		This driver is for boards based on the RTL8129 and RTL8139

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		PCI ethernet chips.

    59

    60

		The author may be reached as becker@scyld.com, or C/O Scyld

    61

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    62

		MD 21403

    63

    64

		Support and updates available at

    65

		http://www.scyld.com/network/rtl8139.html

    66

    67

		Twister-tuning table provided by Kinston

    68

		<shangh@realtek.com.tw>.

    69

    70

	-----<snip>-----

    71

    72

	This software may be used and distributed according to the terms

    73

	of the GNU General Public License, incorporated herein by reference.

    74

    75

	Contributors:

    76

    77

		Donald Becker - he wrote the original driver, kudos to him!

    78

		(but please don't e-mail him for support, this isn't his driver)

    79

    80

		Tigran Aivazian - bug fixes, skbuff free cleanup

    81

    82

		Martin Mares - suggestions for PCI cleanup

    83

    84

		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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		Gerard Sharp - bug fix, testing and feedback

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    93

		David Ford - Rx ring wrap fix

    94

    95

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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    98

		Donald Becker/Chris Butterworth/Marcus Westergren -

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		Noticed various Rx packet size-related buglets.

   100

   101

		Santiago Garcia Mantinan - testing and feedback

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   103

		Jens David - 2.2.x kernel backports

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   105

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

   107

   108

		Jean-Jacques Michel - bug fix

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   110

		Tobias Ringström - Rx interrupt status checking suggestion

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   112

		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   121

		"rtl8139-diag -mmmaaavvveefN" output

   122

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   123

   124

*/

   125

   126

#define DRV_NAME	"ec_8139too"

   127

#define DRV_VERSION	"0.9.27"

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   129

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/compiler.h>

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#include <linux/pci.h>

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#include <linux/init.h>

   135

#include <linux/ioport.h>

   136

#include <linux/netdevice.h>

   137

#include <linux/etherdevice.h>

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#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

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#include <linux/completion.h>

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#include <linux/crc32.h>

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#include <asm/io.h>

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#include <asm/uaccess.h>

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#include <asm/irq.h>

   147

   148

#include "../globals.h"

   149

#include "ecdev.h"

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   151

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

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   155

#define PFX DRV_NAME ": "

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   157

/* Default Message level */

   158

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   159

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   161

   162

   163

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   164

#ifdef CONFIG_8139TOO_PIO

   165

#define USE_IO_OPS 1

   166

#endif

   167

   168

/* define to 1, 2 or 3 to enable copious debugging info */

   169

#define RTL8139_DEBUG 0

   170

   171

/* define to 1 to disable lightweight runtime debugging checks */

   172

#undef RTL8139_NDEBUG

   173

   174

   175

#if RTL8139_DEBUG

   176

/* note: prints function name for you */

   177

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   178

#else

   179

#  define DPRINTK(fmt, args...)

   180

#endif

   181

   182

#ifdef RTL8139_NDEBUG

   183

#  define assert(expr) do {} while (0)

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#else

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#  define assert(expr) \

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        if(unlikely(!(expr))) {				        \

   187

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

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        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   189

        }

   190

#endif

   191

   192

   193

/* A few user-configurable values. */

   194

/* media options */

   195

#define MAX_UNITS 8

   196

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   197

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   198

   199

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   200

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   201

static int multicast_filter_limit = 32;

   202

   203

/* bitmapped message enable number */

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static int debug = -1;

   205

   206

/*

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 * Receive ring size

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 * Warning: 64K ring has hardware issues and may lock up.

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 */

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#if defined(CONFIG_SH_DREAMCAST)

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#define RX_BUF_IDX	1	/* 16K ring */

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#else

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#define RX_BUF_IDX	2	/* 32K ring */

   214

#endif

   215

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   216

#define RX_BUF_PAD	16

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#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   218

   219

#if RX_BUF_LEN == 65536

   220

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   221

#else

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#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   223

#endif

   224

   225

/* Number of Tx descriptor registers. */

   226

#define NUM_TX_DESC	4

   227

   228

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   229

#define MAX_ETH_FRAME_SIZE	1536

   230

   231

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   232

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   233

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   234

   235

/* PCI Tuning Parameters

   236

   Threshold is bytes transferred to chip before transmission starts. */

   237

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   238

   239

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   240

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   241

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   242

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   243

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   244

   245

/* Operational parameters that usually are not changed. */

   246

/* Time in jiffies before concluding the transmitter is hung. */

   247

#define TX_TIMEOUT  (6*HZ)

   248

   249

   250

enum {

   251

	HAS_MII_XCVR = 0x010000,

   252

	HAS_CHIP_XCVR = 0x020000,

   253

	HAS_LNK_CHNG = 0x040000,

   254

};

   255

   256

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   257

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   258

#define RTL_MIN_IO_SIZE 0x80

   259

#define RTL8139B_IO_SIZE 256

   260

   261

#define RTL8129_CAPS	HAS_MII_XCVR

   262

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   263

   264

typedef enum {

   265

	RTL8139 = 0,

   266

	RTL8129,

   267

} board_t;

   268

   269

   270

/* indexed by board_t, above */

   271

static const struct {

   272

	const char *name;

   273

	u32 hw_flags;

   274

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

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	{ "RealTek RTL8129", RTL8129_CAPS },

   277

};

   278

   279

   280

static struct pci_device_id rtl8139_pci_tbl[] = {

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	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300

   301

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

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#ifdef CONFIG_8139TOO_8129

   306

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   307

#endif

   308

   309

	/* some crazy cards report invalid vendor ids like

   310

	 * 0x0001 here.  The other ids are valid and constant,

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	 * so we simply don't match on the main vendor id.

   312

	 */

   313

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   316

   317

	{0,}

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};

   319

   320

/* prevent driver from being loaded automatically */

   321

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   322

   323

static struct {

   324

	const char str[ETH_GSTRING_LEN];

   325

} ethtool_stats_keys[] = {

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	{ "early_rx" },

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	{ "tx_buf_mapped" },

   328

	{ "tx_timeouts" },

   329

	{ "rx_lost_in_ring" },

   330

};

   331

   332

/* The rest of these values should never change. */

   333

   334

/* Symbolic offsets to registers. */

   335

enum RTL8139_registers {

   336

	MAC0 = 0,		/* Ethernet hardware address. */

   337

	MAR0 = 8,		/* Multicast filter. */

   338

	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   339

	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   340

	RxBuf = 0x30,

   341

	ChipCmd = 0x37,

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	RxBufPtr = 0x38,

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	RxBufAddr = 0x3A,

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	IntrMask = 0x3C,

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	IntrStatus = 0x3E,

   346

	TxConfig = 0x40,

   347

	RxConfig = 0x44,

   348

	Timer = 0x48,		/* A general-purpose counter. */

   349

	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   350

	Cfg9346 = 0x50,

   351

	Config0 = 0x51,

   352

	Config1 = 0x52,

   353

	FlashReg = 0x54,

   354

	MediaStatus = 0x58,

   355

	Config3 = 0x59,

   356

	Config4 = 0x5A,		/* absent on RTL-8139A */

   357

	HltClk = 0x5B,

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	MultiIntr = 0x5C,

   359

	TxSummary = 0x60,

   360

	BasicModeCtrl = 0x62,

   361

	BasicModeStatus = 0x64,

   362

	NWayAdvert = 0x66,

   363

	NWayLPAR = 0x68,

   364

	NWayExpansion = 0x6A,

   365

	/* Undocumented registers, but required for proper operation. */

   366

	FIFOTMS = 0x70,		/* FIFO Control and test. */

   367

	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   368

	PARA78 = 0x78,

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	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   370

	Config5 = 0xD8,		/* absent on RTL-8139A */

   371

};

   372

   373

enum ClearBitMasks {

   374

	MultiIntrClear = 0xF000,

   375

	ChipCmdClear = 0xE2,

   376

	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

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};

   378

   379

enum ChipCmdBits {

   380

	CmdReset = 0x10,

   381

	CmdRxEnb = 0x08,

   382

	CmdTxEnb = 0x04,

   383

	RxBufEmpty = 0x01,

   384

};

   385

   386

/* Interrupt register bits, using my own meaningful names. */

   387

enum IntrStatusBits {

   388

	PCIErr = 0x8000,

   389

	PCSTimeout = 0x4000,

   390

	RxFIFOOver = 0x40,

   391

	RxUnderrun = 0x20,

   392

	RxOverflow = 0x10,

   393

	TxErr = 0x08,

   394

	TxOK = 0x04,

   395

	RxErr = 0x02,

   396

	RxOK = 0x01,

   397

   398

	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   399

};

   400

   401

enum TxStatusBits {

   402

	TxHostOwns = 0x2000,

   403

	TxUnderrun = 0x4000,

   404

	TxStatOK = 0x8000,

   405

	TxOutOfWindow = 0x20000000,

   406

	TxAborted = 0x40000000,

   407

	TxCarrierLost = 0x80000000,

   408

};

   409

enum RxStatusBits {

   410

	RxMulticast = 0x8000,

   411

	RxPhysical = 0x4000,

   412

	RxBroadcast = 0x2000,

   413

	RxBadSymbol = 0x0020,

   414

	RxRunt = 0x0010,

   415

	RxTooLong = 0x0008,

   416

	RxCRCErr = 0x0004,

   417

	RxBadAlign = 0x0002,

   418

	RxStatusOK = 0x0001,

   419

};

   420

   421

/* Bits in RxConfig. */

   422

enum rx_mode_bits {

   423

	AcceptErr = 0x20,

   424

	AcceptRunt = 0x10,

   425

	AcceptBroadcast = 0x08,

   426

	AcceptMulticast = 0x04,

   427

	AcceptMyPhys = 0x02,

   428

	AcceptAllPhys = 0x01,

   429

};

   430

   431

/* Bits in TxConfig. */

   432

enum tx_config_bits {

   433

   434

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   435

        TxIFGShift = 24,

   436

        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   437

        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   438

        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   439

        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   440

   441

	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   442

	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   443

	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   444

	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   445

	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   446

   447

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   448

};

   449

   450

/* Bits in Config1 */

   451

enum Config1Bits {

   452

	Cfg1_PM_Enable = 0x01,

   453

	Cfg1_VPD_Enable = 0x02,

   454

	Cfg1_PIO = 0x04,

   455

	Cfg1_MMIO = 0x08,

   456

	LWAKE = 0x10,		/* not on 8139, 8139A */

   457

	Cfg1_Driver_Load = 0x20,

   458

	Cfg1_LED0 = 0x40,

   459

	Cfg1_LED1 = 0x80,

   460

	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   461

	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   462

};

   463

   464

/* Bits in Config3 */

   465

enum Config3Bits {

   466

	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   467

	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   468

	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   469

	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   470

	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   471

	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   472

	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   473

	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   474

};

   475

   476

/* Bits in Config4 */

   477

enum Config4Bits {

   478

	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   479

};

   480

   481

/* Bits in Config5 */

   482

enum Config5Bits {

   483

	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   484

	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   485

	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   486

	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   487

	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   488

	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   489

	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   490

};

   491

   492

enum RxConfigBits {

   493

	/* rx fifo threshold */

   494

	RxCfgFIFOShift = 13,

   495

	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   496

   497

	/* Max DMA burst */

   498

	RxCfgDMAShift = 8,

   499

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   500

   501

	/* rx ring buffer length */

   502

	RxCfgRcv8K = 0,

   503

	RxCfgRcv16K = (1 << 11),

   504

	RxCfgRcv32K = (1 << 12),

   505

	RxCfgRcv64K = (1 << 11) | (1 << 12),

   506

   507

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   508

	RxNoWrap = (1 << 7),

   509

};

   510

   511

/* Twister tuning parameters from RealTek.

   512

   Completely undocumented, but required to tune bad links on some boards. */

   513

enum CSCRBits {

   514

	CSCR_LinkOKBit = 0x0400,

   515

	CSCR_LinkChangeBit = 0x0800,

   516

	CSCR_LinkStatusBits = 0x0f000,

   517

	CSCR_LinkDownOffCmd = 0x003c0,

   518

	CSCR_LinkDownCmd = 0x0f3c0,

   519

};

   520

   521

enum Cfg9346Bits {

   522

	Cfg9346_Lock = 0x00,

   523

	Cfg9346_Unlock = 0xC0,

   524

};

   525

   526

typedef enum {

   527

	CH_8139 = 0,

   528

	CH_8139_K,