1

/*

     2

     3

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

     4

     5

	Maintained by Jeff Garzik <jgarzik@pobox.com>

     6

	Copyright 2000-2002 Jeff Garzik

     7

     8

	Much code comes from Donald Becker's rtl8139.c driver,

     9

	versions 1.13 and older.  This driver was originally based

    10

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    11

    12

	-----<snip>-----

    13

    14

        	Written 1997-2001 by Donald Becker.

    15

		This software may be used and distributed according to the

    16

		terms of the GNU General Public License (GPL), incorporated

    17

		herein by reference.  Drivers based on or derived from this

    18

		code fall under the GPL and must retain the authorship,

    19

		copyright and license notice.  This file is not a complete

    20

		program and may only be used when the entire operating

    21

		system is licensed under the GPL.

    22

    23

		This driver is for boards based on the RTL8129 and RTL8139

    24

		PCI ethernet chips.

    25

    26

		The author may be reached as becker@scyld.com, or C/O Scyld

    27

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    28

		MD 21403

    29

    30

		Support and updates available at

    31

		http://www.scyld.com/network/rtl8139.html

    32

    33

		Twister-tuning table provided by Kinston

    34

		<shangh@realtek.com.tw>.

    35

    36

	-----<snip>-----

    37

    38

	This software may be used and distributed according to the terms

    39

	of the GNU General Public License, incorporated herein by reference.

    40

    41

	Contributors:

    42

    43

		Donald Becker - he wrote the original driver, kudos to him!

    44

		(but please don't e-mail him for support, this isn't his driver)

    45

    46

		Tigran Aivazian - bug fixes, skbuff free cleanup

    47

    48

		Martin Mares - suggestions for PCI cleanup

    49

    50

		David S. Miller - PCI DMA and softnet updates

    51

    52

		Ernst Gill - fixes ported from BSD driver

    53

    54

		Daniel Kobras - identified specific locations of

    55

			posted MMIO write bugginess

    56

    57

		Gerard Sharp - bug fix, testing and feedback

    58

    59

		David Ford - Rx ring wrap fix

    60

    61

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    62

		to find and fix a crucial bug on older chipsets.

    63

    64

		Donald Becker/Chris Butterworth/Marcus Westergren -

    65

		Noticed various Rx packet size-related buglets.

    66

    67

		Santiago Garcia Mantinan - testing and feedback

    68

    69

		Jens David - 2.2.x kernel backports

    70

    71

		Martin Dennett - incredibly helpful insight on undocumented

    72

		features of the 8139 chips

    73

    74

		Jean-Jacques Michel - bug fix

    75

    76

		Tobias Ringström - Rx interrupt status checking suggestion

    77

    78

		Andrew Morton - Clear blocked signals, avoid

    79

		buffer overrun setting current->comm.

    80

    81

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

    82

    83

		Robert Kuebel - Save kernel thread from dying on any signal.

    84

    85

	Submitting bug reports:

    86

    87

		"rtl8139-diag -mmmaaavvveefN" output

    88

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

    89

    90

*/

    91

    92

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

    93

    94

#define DRV_NAME	"8139too"

    95

#define DRV_VERSION	"0.9.28"

    96

    97

    98

#include <linux/module.h>

    99

#include <linux/kernel.h>

   100

#include <linux/compiler.h>

   101

#include <linux/pci.h>

   102

#include <linux/init.h>

   103

#include <linux/interrupt.h>

   104

#include <linux/netdevice.h>

   105

#include <linux/etherdevice.h>

   106

#include <linux/rtnetlink.h>

   107

#include <linux/delay.h>

   108

#include <linux/ethtool.h>

   109

#include <linux/mii.h>

   110

#include <linux/completion.h>

   111

#include <linux/crc32.h>

   112

#include <linux/io.h>

   113

#include <linux/uaccess.h>

   114

#include <linux/gfp.h>

   115

#include <asm/irq.h>

   116

   117

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   118

   119

/* Default Message level */

   120

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   121

                                 NETIF_MSG_PROBE  | \

   122

                                 NETIF_MSG_LINK)

   123

   124

   125

/* define to 1, 2 or 3 to enable copious debugging info */

   126

#define RTL8139_DEBUG 0

   127

   128

/* define to 1 to disable lightweight runtime debugging checks */

   129

#undef RTL8139_NDEBUG

   130

   131

   132

#ifdef RTL8139_NDEBUG

   133

#  define assert(expr) do {} while (0)

   134

#else

   135

#  define assert(expr) \

   136

        if (unlikely(!(expr))) {				\

   137

		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   138

		       #expr, __FILE__, __func__, __LINE__);	\

   139

        }

   140

#endif

   141

   142

   143

/* A few user-configurable values. */

   144

/* media options */

   145

#define MAX_UNITS 8

   146

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   147

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   148

   149

/* Whether to use MMIO or PIO. Default to MMIO. */

   150

#ifdef CONFIG_8139TOO_PIO

   151

static bool use_io = true;

   152

#else

   153

static bool use_io = false;

   154

#endif

   155

   156

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   157

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   158

static int multicast_filter_limit = 32;

   159

   160

/* bitmapped message enable number */

   161

static int debug = -1;

   162

   163

/*

   164

 * Receive ring size

   165

 * Warning: 64K ring has hardware issues and may lock up.

   166

 */

   167

#if defined(CONFIG_SH_DREAMCAST)

   168

#define RX_BUF_IDX 0	/* 8K ring */

   169

#else

   170

#define RX_BUF_IDX	2	/* 32K ring */

   171

#endif

   172

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   173

#define RX_BUF_PAD	16

   174

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   175

   176

#if RX_BUF_LEN == 65536

   177

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   178

#else

   179

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   180

#endif

   181

   182

/* Number of Tx descriptor registers. */

   183

#define NUM_TX_DESC	4

   184

   185

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   186

#define MAX_ETH_FRAME_SIZE	1536

   187

   188

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   189

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   190

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   191

   192

/* PCI Tuning Parameters

   193

   Threshold is bytes transferred to chip before transmission starts. */

   194

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   195

   196

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   197

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   198

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   199

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   200

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   201

   202

/* Operational parameters that usually are not changed. */

   203

/* Time in jiffies before concluding the transmitter is hung. */

   204

#define TX_TIMEOUT  (6*HZ)

   205

   206

   207

enum {

   208

	HAS_MII_XCVR = 0x010000,

   209

	HAS_CHIP_XCVR = 0x020000,

   210

	HAS_LNK_CHNG = 0x040000,

   211

};

   212

   213

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   214

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   215

#define RTL_MIN_IO_SIZE 0x80

   216

#define RTL8139B_IO_SIZE 256

   217

   218

#define RTL8129_CAPS	HAS_MII_XCVR

   219

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   220

   221

typedef enum {

   222

	RTL8139 = 0,

   223

	RTL8129,

   224

} board_t;

   225

   226

   227

/* indexed by board_t, above */

   228

static const struct {

   229

	const char *name;

   230

	u32 hw_flags;

   231

} board_info[] = {

   232

	{ "RealTek RTL8139", RTL8139_CAPS },

   233

	{ "RealTek RTL8129", RTL8129_CAPS },

   234

};

   235

   236

   237

static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   238

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   239

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   240

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   241

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   242

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   243

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   244

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   245

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   246

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   247

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   248

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   249

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   250

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   251

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   252

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   253

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   254

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   255

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   256

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   257

   258

#ifdef CONFIG_SH_SECUREEDGE5410

   259

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   260

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   261

#endif

   262

#ifdef CONFIG_8139TOO_8129

   263

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   264

#endif

   265

   266

	/* some crazy cards report invalid vendor ids like

   267

	 * 0x0001 here.  The other ids are valid and constant,

   268

	 * so we simply don't match on the main vendor id.

   269

	 */

   270

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   271

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   272

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   273

   274

	{0,}

   275

};

   276

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   277

   278

static struct {

   279

	const char str[ETH_GSTRING_LEN];

   280

} ethtool_stats_keys[] = {

   281

	{ "early_rx" },

   282

	{ "tx_buf_mapped" },

   283

	{ "tx_timeouts" },

   284

	{ "rx_lost_in_ring" },

   285

};

   286

   287

/* The rest of these values should never change. */

   288

   289

/* Symbolic offsets to registers. */

   290

enum RTL8139_registers {

   291

	MAC0		= 0,	 /* Ethernet hardware address. */

   292

	MAR0		= 8,	 /* Multicast filter. */

   293

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   294

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   295

	RxBuf		= 0x30,

   296

	ChipCmd		= 0x37,

   297

	RxBufPtr	= 0x38,

   298

	RxBufAddr	= 0x3A,

   299

	IntrMask	= 0x3C,

   300

	IntrStatus	= 0x3E,

   301

	TxConfig	= 0x40,

   302

	RxConfig	= 0x44,

   303

	Timer		= 0x48,	 /* A general-purpose counter. */

   304

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   305

	Cfg9346		= 0x50,

   306

	Config0		= 0x51,

   307

	Config1		= 0x52,

   308

	TimerInt	= 0x54,

   309

	MediaStatus	= 0x58,

   310

	Config3		= 0x59,

   311

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   312

	HltClk		= 0x5B,

   313

	MultiIntr	= 0x5C,

   314

	TxSummary	= 0x60,

   315

	BasicModeCtrl	= 0x62,

   316

	BasicModeStatus	= 0x64,

   317

	NWayAdvert	= 0x66,

   318

	NWayLPAR	= 0x68,

   319

	NWayExpansion	= 0x6A,

   320

	/* Undocumented registers, but required for proper operation. */

   321

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   322

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   323

	PARA78		= 0x78,

   324

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   325

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   326

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   327

};

   328

   329

enum ClearBitMasks {

   330

	MultiIntrClear	= 0xF000,

   331

	ChipCmdClear	= 0xE2,

   332

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   333

};

   334

   335

enum ChipCmdBits {

   336

	CmdReset	= 0x10,

   337

	CmdRxEnb	= 0x08,

   338

	CmdTxEnb	= 0x04,

   339

	RxBufEmpty	= 0x01,

   340

};

   341

   342

/* Interrupt register bits, using my own meaningful names. */

   343

enum IntrStatusBits {

   344

	PCIErr		= 0x8000,

   345

	PCSTimeout	= 0x4000,

   346

	RxFIFOOver	= 0x40,

   347

	RxUnderrun	= 0x20,

   348

	RxOverflow	= 0x10,

   349

	TxErr		= 0x08,

   350

	TxOK		= 0x04,

   351

	RxErr		= 0x02,

   352

	RxOK		= 0x01,

   353

   354

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   355

};

   356

   357

enum TxStatusBits {

   358

	TxHostOwns	= 0x2000,

   359

	TxUnderrun	= 0x4000,

   360

	TxStatOK	= 0x8000,

   361

	TxOutOfWindow	= 0x20000000,

   362

	TxAborted	= 0x40000000,

   363

	TxCarrierLost	= 0x80000000,

   364

};

   365

enum RxStatusBits {

   366

	RxMulticast	= 0x8000,

   367

	RxPhysical	= 0x4000,

   368

	RxBroadcast	= 0x2000,

   369

	RxBadSymbol	= 0x0020,

   370

	RxRunt		= 0x0010,

   371

	RxTooLong	= 0x0008,

   372

	RxCRCErr	= 0x0004,

   373

	RxBadAlign	= 0x0002,

   374

	RxStatusOK	= 0x0001,

   375

};

   376

   377

/* Bits in RxConfig. */

   378

enum rx_mode_bits {

   379

	AcceptErr	= 0x20,

   380

	AcceptRunt	= 0x10,

   381

	AcceptBroadcast	= 0x08,

   382

	AcceptMulticast	= 0x04,

   383

	AcceptMyPhys	= 0x02,

   384

	AcceptAllPhys	= 0x01,

   385

};

   386

   387

/* Bits in TxConfig. */

   388

enum tx_config_bits {

   389

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   390

        TxIFGShift	= 24,

   391

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   392

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   393

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   394

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   395

   396

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   397

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   398

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   399

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   400

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   401

   402

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   403

};

   404

   405

/* Bits in Config1 */

   406

enum Config1Bits {

   407

	Cfg1_PM_Enable	= 0x01,

   408

	Cfg1_VPD_Enable	= 0x02,

   409

	Cfg1_PIO	= 0x04,

   410

	Cfg1_MMIO	= 0x08,

   411

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   412

	Cfg1_Driver_Load = 0x20,

   413

	Cfg1_LED0	= 0x40,

   414

	Cfg1_LED1	= 0x80,

   415

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   416

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   417

};

   418

   419

/* Bits in Config3 */

   420

enum Config3Bits {

   421

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   422

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   423

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   424

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   425

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   426

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   427

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   428

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   429

};

   430

   431

/* Bits in Config4 */

   432

enum Config4Bits {

   433

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   434

};

   435

   436

/* Bits in Config5 */

   437

enum Config5Bits {

   438

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   439

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   440

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   441

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   442

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   443

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   444

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   445

};

   446

   447

enum RxConfigBits {

   448

	/* rx fifo threshold */

   449

	RxCfgFIFOShift	= 13,

   450

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   451

   452

	/* Max DMA burst */

   453

	RxCfgDMAShift	= 8,

   454

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   455

   456

	/* rx ring buffer length */

   457

	RxCfgRcv8K	= 0,

   458

	RxCfgRcv16K	= (1 << 11),

   459

	RxCfgRcv32K	= (1 << 12),

   460

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   461

   462

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   463

	RxNoWrap	= (1 << 7),

   464

};

   465

   466

/* Twister tuning parameters from RealTek.

   467

   Completely undocumented, but required to tune bad links on some boards. */

   468

enum CSCRBits {

   469

	CSCR_LinkOKBit		= 0x0400,

   470

	CSCR_LinkChangeBit	= 0x0800,

   471

	CSCR_LinkStatusBits	= 0x0f000,

   472

	CSCR_LinkDownOffCmd	= 0x003c0,

   473

	CSCR_LinkDownCmd	= 0x0f3c0,

   474

};

   475

   476

enum Cfg9346Bits {

   477

	Cfg9346_Lock	= 0x00,

   478

	Cfg9346_Unlock	= 0xC0,

   479

};

   480

   481

typedef enum {

   482

	CH_8139	= 0,

   483

	CH_8139_K,

   484

	CH_8139A,

   485

	CH_8139A_G,

   486

	CH_8139B,

   487

	CH_8130,

   488

	CH_8139C,

   489

	CH_8100,

   490

	CH_8100B_8139D,

   491

	CH_8101,

   492

} chip_t;

   493

   494

enum chip_flags {

   495

	HasHltClk	= (1 << 0),

   496

	HasLWake	= (1 << 1),

   497

};

   498

   499

#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   500

	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   501

#define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   502

   503

/* directly indexed by chip_t, above */

   504

static const struct {

   505

	const char *name;

   506

	u32 version; /* from RTL8139C/RTL8139D docs */

   507

	u32 flags;

   508

} rtl_chip_info[] = {

   509

	{ "RTL-8139",

   510

	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   511

	  HasHltClk,

   512

	},

   513

   514

	{ "RTL-8139 rev K",

   515

	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   516

	  HasHltClk,

   517

	},

   518

   519

	{ "RTL-8139A",

   520

	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   521

	  HasHltClk, /* XXX undocumented? */

   522

	},

   523

   524

	{ "RTL-8139A rev G",

   525

	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   526

	  HasHltClk, /* XXX undocumented? */

   527

	},

   528

   529

	{ "RTL-8139B",

   530

	  HW_REVID(1, 1, 1, 1, 0, 0, 0),