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/******************************************************************************

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 *

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 *  $Id$

     4

 *

     5

 *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it

    10

 *  and/or modify it under the terms of the GNU General Public License

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 *  as published by the Free Software Foundation; either version 2 of the

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 *  License, or (at your option) any later version.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be

    15

 *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 *  GNU General Public License for more details.

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 *

    19

 *  You should have received a copy of the GNU General Public License

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 *  along with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

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 *  The right to use EtherCAT Technology is granted and comes free of

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 *  charge under condition of compatibility of product made by

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 *  Licensee. People intending to distribute/sell products based on the

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 *  code, have to sign an agreement to guarantee that products using

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 *  software based on IgH EtherCAT master stay compatible with the actual

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 *  EtherCAT specification (which are released themselves as an open

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 *  standard) as the (only) precondition to have the right to use EtherCAT

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 *  Technology, IP and trade marks.

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 *

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 *****************************************************************************/

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    34

/**

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   \file

    36

   EtherCAT driver for RTL8139-compatible NICs.

    37

*/

    38

    39

/*****************************************************************************/

    40

    41

/*

    42

  Former documentation:

    43

    44

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45

    46

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    48

    49

	Much code comes from Donald Becker's rtl8139.c driver,

    50

	versions 1.13 and older.  This driver was originally based

    51

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52

    53

	-----<snip>-----

    54

    55

        	Written 1997-2001 by Donald Becker.

    56

		This software may be used and distributed according to the

    57

		terms of the GNU General Public License (GPL), incorporated

    58

		herein by reference.  Drivers based on or derived from this

    59

		code fall under the GPL and must retain the authorship,

    60

		copyright and license notice.  This file is not a complete

    61

		program and may only be used when the entire operating

    62

		system is licensed under the GPL.

    63

    64

		This driver is for boards based on the RTL8129 and RTL8139

    65

		PCI ethernet chips.

    66

    67

		The author may be reached as becker@scyld.com, or C/O Scyld

    68

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69

		MD 21403

    70

    71

		Support and updates available at

    72

		http://www.scyld.com/network/rtl8139.html

    73

    74

		Twister-tuning table provided by Kinston

    75

		<shangh@realtek.com.tw>.

    76

    77

	-----<snip>-----

    78

    79

	This software may be used and distributed according to the terms

    80

	of the GNU General Public License, incorporated herein by reference.

    81

    82

	Contributors:

    83

    84

		Donald Becker - he wrote the original driver, kudos to him!

    85

		(but please don't e-mail him for support, this isn't his driver)

    86

    87

		Tigran Aivazian - bug fixes, skbuff free cleanup

    88

    89

		Martin Mares - suggestions for PCI cleanup

    90

    91

		David S. Miller - PCI DMA and softnet updates

    92

    93

		Ernst Gill - fixes ported from BSD driver

    94

    95

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

    97

    98

		Gerard Sharp - bug fix, testing and feedback

    99

   100

		David Ford - Rx ring wrap fix

   101

   102

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103

		to find and fix a crucial bug on older chipsets.

   104

   105

		Donald Becker/Chris Butterworth/Marcus Westergren -

   106

		Noticed various Rx packet size-related buglets.

   107

   108

		Santiago Garcia Mantinan - testing and feedback

   109

   110

		Jens David - 2.2.x kernel backports

   111

   112

		Martin Dennett - incredibly helpful insight on undocumented

   113

		features of the 8139 chips

   114

   115

		Jean-Jacques Michel - bug fix

   116

   117

		Tobias Ringström - Rx interrupt status checking suggestion

   118

   119

		Andrew Morton - Clear blocked signals, avoid

   120

		buffer overrun setting current->comm.

   121

   122

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   123

   124

		Robert Kuebel - Save kernel thread from dying on any signal.

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   126

	Submitting bug reports:

   127

   128

		"rtl8139-diag -mmmaaavvveefN" output

   129

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130

   131

*/

   132

   133

#define DRV_NAME	"ec_8139too"

   134

#define DRV_VERSION	"0.9.28"

   135

   136

   137

#include <linux/module.h>

   138

#include <linux/kernel.h>

   139

#include <linux/compiler.h>

   140

#include <linux/pci.h>

   141

#include <linux/init.h>

   142

#include <linux/ioport.h>

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#include <linux/netdevice.h>

   144

#include <linux/etherdevice.h>

   145

#include <linux/rtnetlink.h>

   146

#include <linux/delay.h>

   147

#include <linux/ethtool.h>

   148

#include <linux/mii.h>

   149

#include <linux/completion.h>

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#include <linux/crc32.h>

   151

#include <asm/io.h>

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#include <asm/uaccess.h>

   153

#include <asm/irq.h>

   154

   155

#include "../globals.h"

   156

#include "ecdev.h"

   157

   158

#define RTL8139_DRIVER_NAME DRV_NAME \

   159

                            " EtherCAT-capable Fast Ethernet driver " \

   160

                            DRV_VERSION ", master " EC_MASTER_VERSION

   161

   162

#define PFX DRV_NAME ": "

   163

   164

/* Default Message level */

   165

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   166

                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   168

   169

   170

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   171

#ifdef CONFIG_8139TOO_PIO

   172

#define USE_IO_OPS 1

   173

#endif

   174

   175

/* define to 1, 2 or 3 to enable copious debugging info */

   176

#define RTL8139_DEBUG 0

   177

   178

/* define to 1 to disable lightweight runtime debugging checks */

   179

#undef RTL8139_NDEBUG

   180

   181

   182

#if RTL8139_DEBUG

   183

/* note: prints function name for you */

   184

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   185

#else

   186

#  define DPRINTK(fmt, args...)

   187

#endif

   188

   189

#ifdef RTL8139_NDEBUG

   190

#  define assert(expr) do {} while (0)

   191

#else

   192

#  define assert(expr) \

   193

        if(unlikely(!(expr))) {				        \

   194

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   195

        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   196

        }

   197

#endif

   198

   199

   200

/* A few user-configurable values. */

   201

/* media options */

   202

#define MAX_UNITS 8

   203

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   204

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   205

   206

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   207

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   208

static int multicast_filter_limit = 32;

   209

   210

/* bitmapped message enable number */

   211

static int debug = -1;

   212

   213

/*

   214

 * Receive ring size

   215

 * Warning: 64K ring has hardware issues and may lock up.

   216

 */

   217

#if defined(CONFIG_SH_DREAMCAST)

   218

#define RX_BUF_IDX	1	/* 16K ring */

   219

#else

   220

#define RX_BUF_IDX	2	/* 32K ring */

   221

#endif

   222

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   223

#define RX_BUF_PAD	16

   224

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   225

   226

#if RX_BUF_LEN == 65536

   227

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   228

#else

   229

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   230

#endif

   231

   232

/* Number of Tx descriptor registers. */

   233

#define NUM_TX_DESC	4

   234

   235

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   236

#define MAX_ETH_FRAME_SIZE	1536

   237

   238

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   239

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   240

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   241

   242

/* PCI Tuning Parameters

   243

   Threshold is bytes transferred to chip before transmission starts. */

   244

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   245

   246

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   247

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   248

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   249

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   250

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   251

   252

/* Operational parameters that usually are not changed. */

   253

/* Time in jiffies before concluding the transmitter is hung. */

   254

#define TX_TIMEOUT  (6*HZ)

   255

   256

   257

enum {

   258

	HAS_MII_XCVR = 0x010000,

   259

	HAS_CHIP_XCVR = 0x020000,

   260

	HAS_LNK_CHNG = 0x040000,

   261

};

   262

   263

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   264

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   265

#define RTL_MIN_IO_SIZE 0x80

   266

#define RTL8139B_IO_SIZE 256

   267

   268

#define RTL8129_CAPS	HAS_MII_XCVR

   269

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   270

   271

typedef enum {

   272

	RTL8139 = 0,

   273

	RTL8129,

   274

} board_t;

   275

   276

   277

/* indexed by board_t, above */

   278

static const struct {

   279

	const char *name;

   280

	u32 hw_flags;

   281

} board_info[] __devinitdata = {

   282

	{ "RealTek RTL8139", RTL8139_CAPS },

   283

	{ "RealTek RTL8129", RTL8129_CAPS },

   284

};

   285

   286

   287

static struct pci_device_id rtl8139_pci_tbl[] = {

   288

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307

   308

#ifdef CONFIG_SH_SECUREEDGE5410

   309

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   310

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311

#endif

   312

#ifdef CONFIG_8139TOO_8129

   313

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   314

#endif

   315

   316

	/* some crazy cards report invalid vendor ids like

   317

	 * 0x0001 here.  The other ids are valid and constant,

   318

	 * so we simply don't match on the main vendor id.

   319

	 */

   320

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   322

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   323

   324

	{0,}

   325

};

   326

   327

/* prevent driver from being loaded automatically */

   328

//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   329

   330

static struct {

   331

	const char str[ETH_GSTRING_LEN];

   332

} ethtool_stats_keys[] = {

   333

	{ "early_rx" },

   334

	{ "tx_buf_mapped" },

   335

	{ "tx_timeouts" },

   336

	{ "rx_lost_in_ring" },

   337

};

   338

   339

/* The rest of these values should never change. */

   340

   341

/* Symbolic offsets to registers. */

   342

enum RTL8139_registers {

   343

	MAC0		= 0,	 /* Ethernet hardware address. */

   344

	MAR0		= 8,	 /* Multicast filter. */

   345

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   346

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   347

	RxBuf		= 0x30,

   348

	ChipCmd		= 0x37,

   349

	RxBufPtr	= 0x38,

   350

	RxBufAddr	= 0x3A,

   351

	IntrMask	= 0x3C,

   352

	IntrStatus	= 0x3E,

   353

	TxConfig	= 0x40,

   354

	RxConfig	= 0x44,

   355

	Timer		= 0x48,	 /* A general-purpose counter. */

   356

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   357

	Cfg9346		= 0x50,

   358

	Config0		= 0x51,

   359

	Config1		= 0x52,

   360

	FlashReg	= 0x54,

   361

	MediaStatus	= 0x58,

   362

	Config3		= 0x59,

   363

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   364

	HltClk		= 0x5B,

   365

	MultiIntr	= 0x5C,

   366

	TxSummary	= 0x60,

   367

	BasicModeCtrl	= 0x62,

   368

	BasicModeStatus	= 0x64,

   369

	NWayAdvert	= 0x66,

   370

	NWayLPAR	= 0x68,

   371

	NWayExpansion	= 0x6A,

   372

	/* Undocumented registers, but required for proper operation. */

   373

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   374

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   375

	PARA78		= 0x78,

   376

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   377

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   378

};

   379

   380

enum ClearBitMasks {

   381

	MultiIntrClear	= 0xF000,

   382

	ChipCmdClear	= 0xE2,

   383

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   384

};

   385

   386

enum ChipCmdBits {

   387

	CmdReset	= 0x10,

   388

	CmdRxEnb	= 0x08,

   389

	CmdTxEnb	= 0x04,

   390

	RxBufEmpty	= 0x01,

   391

};

   392

   393

/* Interrupt register bits, using my own meaningful names. */

   394

enum IntrStatusBits {

   395

	PCIErr		= 0x8000,

   396

	PCSTimeout	= 0x4000,

   397

	RxFIFOOver	= 0x40,

   398

	RxUnderrun	= 0x20,

   399

	RxOverflow	= 0x10,

   400

	TxErr		= 0x08,

   401

	TxOK		= 0x04,

   402

	RxErr		= 0x02,

   403

	RxOK		= 0x01,

   404

   405

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   406

};

   407

   408

enum TxStatusBits {

   409

	TxHostOwns	= 0x2000,

   410

	TxUnderrun	= 0x4000,

   411

	TxStatOK	= 0x8000,

   412

	TxOutOfWindow	= 0x20000000,

   413

	TxAborted	= 0x40000000,

   414

	TxCarrierLost	= 0x80000000,

   415

};

   416

enum RxStatusBits {

   417

	RxMulticast	= 0x8000,

   418

	RxPhysical	= 0x4000,

   419

	RxBroadcast	= 0x2000,

   420

	RxBadSymbol	= 0x0020,

   421

	RxRunt		= 0x0010,

   422

	RxTooLong	= 0x0008,

   423

	RxCRCErr	= 0x0004,

   424

	RxBadAlign	= 0x0002,

   425

	RxStatusOK	= 0x0001,

   426

};

   427

   428

/* Bits in RxConfig. */

   429

enum rx_mode_bits {

   430

	AcceptErr	= 0x20,

   431

	AcceptRunt	= 0x10,

   432

	AcceptBroadcast	= 0x08,

   433

	AcceptMulticast	= 0x04,

   434

	AcceptMyPhys	= 0x02,

   435

	AcceptAllPhys	= 0x01,

   436

};

   437

   438

/* Bits in TxConfig. */

   439

enum tx_config_bits {

   440

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   441

        TxIFGShift	= 24,

   442

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   443

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   444

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   445

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   446

   447

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   448

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   449

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   450

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   451

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   452

   453

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   454

};

   455

   456

/* Bits in Config1 */

   457

enum Config1Bits {

   458

	Cfg1_PM_Enable	= 0x01,

   459

	Cfg1_VPD_Enable	= 0x02,

   460

	Cfg1_PIO	= 0x04,

   461

	Cfg1_MMIO	= 0x08,

   462

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   463

	Cfg1_Driver_Load = 0x20,

   464

	Cfg1_LED0	= 0x40,

   465

	Cfg1_LED1	= 0x80,

   466

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   467

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   468

};

   469

   470

/* Bits in Config3 */

   471

enum Config3Bits {

   472

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   473

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   474

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   475

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   476

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   477

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   478

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   479

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   480

};

   481

   482

/* Bits in Config4 */

   483

enum Config4Bits {

   484

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   485

};

   486

   487

/* Bits in Config5 */

   488

enum Config5Bits {

   489

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   490

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   491

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   492

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   493

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   494

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   495

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   496

};

   497

   498

enum RxConfigBits {

   499

	/* rx fifo threshold */

   500

	RxCfgFIFOShift	= 13,

   501

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   502

   503

	/* Max DMA burst */

   504

	RxCfgDMAShift	= 8,

   505

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   506

   507

	/* rx ring buffer length */

   508

	RxCfgRcv8K	= 0,

   509

	RxCfgRcv16K	= (1 << 11),

   510

	RxCfgRcv32K	= (1 << 12),

   511

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   512

   513

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   514

	RxNoWrap	= (1 << 7),

   515

};

   516

   517

/* Twister tuning parameters from RealTek.

   518

   Completely undocumented, but required to tune bad links on some boards. */

   519

enum CSCRBits {

   520

	CSCR_LinkOKBit		= 0x0400,

   521

	CSCR_LinkChangeBit	= 0x0800,

   522

	CSCR_LinkStatusBits	= 0x0f000,

   523

	CSCR_LinkDownOffCmd	= 0x003c0,

   524

	CSCR_LinkDownCmd	= 0x0f3c0,

   525

};

   526

   527

enum Cfg9346Bits {

   528

	Cfg9346_Lock	= 0x00,

   529

	Cfg9346_Unlock	= 0xC0,