1

/* Intel(R) Gigabit Ethernet Linux driver

     2

 * Copyright(c) 2007-2014 Intel Corporation.

     3

 *

     4

 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

     8

 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

    13

 * You should have received a copy of the GNU General Public License along with

    14

 * this program; if not, see <http://www.gnu.org/licenses/>.

    15

 *

    16

 * The full GNU General Public License is included in this distribution in

    17

 * the file called "COPYING".

    18

 *

    19

 * Contact Information:

    20

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    21

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    22

 */

    23

    24

#include <linux/if_ether.h>

    25

#include <linux/delay.h>

    26

    27

#include "e1000_mac.h"

    28

#include "e1000_phy.h"

    29

    30

static s32  igb_phy_setup_autoneg(struct e1000_hw *hw);

    31

static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,

    32

					     u16 *phy_ctrl);

    33

static s32  igb_wait_autoneg(struct e1000_hw *hw);

    34

static s32  igb_set_master_slave_mode(struct e1000_hw *hw);

    35

    36

/* Cable length tables */

    37

static const u16 e1000_m88_cable_length_table[] = {

    38

	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };

    39

#define M88E1000_CABLE_LENGTH_TABLE_SIZE \

    40

	(sizeof(e1000_m88_cable_length_table) / \

    41

	sizeof(e1000_m88_cable_length_table[0]))

    42

    43

static const u16 e1000_igp_2_cable_length_table[] = {

    44

	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,

    45

	0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,

    46

	6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,

    47

	21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,

    48

	40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,

    49

	60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,

    50

	83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,

    51

	104, 109, 114, 118, 121, 124};

    52

#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \

    53

	(sizeof(e1000_igp_2_cable_length_table) / \

    54

	 sizeof(e1000_igp_2_cable_length_table[0]))

    55

    56

/**

    57

 *  igb_check_reset_block - Check if PHY reset is blocked

    58

 *  @hw: pointer to the HW structure

    59

 *

    60

 *  Read the PHY management control register and check whether a PHY reset

    61

 *  is blocked.  If a reset is not blocked return 0, otherwise

    62

 *  return E1000_BLK_PHY_RESET (12).

    63

 **/

    64

s32 igb_check_reset_block(struct e1000_hw *hw)

    65

{

    66

	u32 manc;

    67

    68

	manc = rd32(E1000_MANC);

    69

    70

	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;

    71

}

    72

    73

/**

    74

 *  igb_get_phy_id - Retrieve the PHY ID and revision

    75

 *  @hw: pointer to the HW structure

    76

 *

    77

 *  Reads the PHY registers and stores the PHY ID and possibly the PHY

    78

 *  revision in the hardware structure.

    79

 **/

    80

s32 igb_get_phy_id(struct e1000_hw *hw)

    81

{

    82

	struct e1000_phy_info *phy = &hw->phy;

    83

	s32 ret_val = 0;

    84

	u16 phy_id;

    85

    86

	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);

    87

	if (ret_val)

    88

		goto out;

    89

    90

	phy->id = (u32)(phy_id << 16);

    91

	udelay(20);

    92

	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);

    93

	if (ret_val)

    94

		goto out;

    95

    96

	phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

    97

	phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

    98

    99

out:

   100

	return ret_val;

   101

}

   102

   103

/**

   104

 *  igb_phy_reset_dsp - Reset PHY DSP

   105

 *  @hw: pointer to the HW structure

   106

 *

   107

 *  Reset the digital signal processor.

   108

 **/

   109

static s32 igb_phy_reset_dsp(struct e1000_hw *hw)

   110

{

   111

	s32 ret_val = 0;

   112

   113

	if (!(hw->phy.ops.write_reg))

   114

		goto out;

   115

   116

	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

   117

	if (ret_val)

   118

		goto out;

   119

   120

	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);

   121

   122

out:

   123

	return ret_val;

   124

}

   125

   126

/**

   127

 *  igb_read_phy_reg_mdic - Read MDI control register

   128

 *  @hw: pointer to the HW structure

   129

 *  @offset: register offset to be read

   130

 *  @data: pointer to the read data

   131

 *

   132

 *  Reads the MDI control regsiter in the PHY at offset and stores the

   133

 *  information read to data.

   134

 **/

   135

s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)

   136

{

   137

	struct e1000_phy_info *phy = &hw->phy;

   138

	u32 i, mdic = 0;

   139

	s32 ret_val = 0;

   140

   141

	if (offset > MAX_PHY_REG_ADDRESS) {

   142

		hw_dbg("PHY Address %d is out of range\n", offset);

   143

		ret_val = -E1000_ERR_PARAM;

   144

		goto out;

   145

	}

   146

   147

	/* Set up Op-code, Phy Address, and register offset in the MDI

   148

	 * Control register.  The MAC will take care of interfacing with the

   149

	 * PHY to retrieve the desired data.

   150

	 */

   151

	mdic = ((offset << E1000_MDIC_REG_SHIFT) |

   152

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   153

		(E1000_MDIC_OP_READ));

   154

   155

	wr32(E1000_MDIC, mdic);

   156

   157

	/* Poll the ready bit to see if the MDI read completed

   158

	 * Increasing the time out as testing showed failures with

   159

	 * the lower time out

   160

	 */

   161

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   162

		udelay(50);

   163

		mdic = rd32(E1000_MDIC);

   164

		if (mdic & E1000_MDIC_READY)

   165

			break;

   166

	}

   167

	if (!(mdic & E1000_MDIC_READY)) {

   168

		hw_dbg("MDI Read did not complete\n");

   169

		ret_val = -E1000_ERR_PHY;

   170

		goto out;

   171

	}

   172

	if (mdic & E1000_MDIC_ERROR) {

   173

		hw_dbg("MDI Error\n");

   174

		ret_val = -E1000_ERR_PHY;

   175

		goto out;

   176

	}

   177

	*data = (u16) mdic;

   178

   179

out:

   180

	return ret_val;

   181

}

   182

   183

/**

   184

 *  igb_write_phy_reg_mdic - Write MDI control register

   185

 *  @hw: pointer to the HW structure

   186

 *  @offset: register offset to write to

   187

 *  @data: data to write to register at offset

   188

 *

   189

 *  Writes data to MDI control register in the PHY at offset.

   190

 **/

   191

s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)

   192

{

   193

	struct e1000_phy_info *phy = &hw->phy;

   194

	u32 i, mdic = 0;

   195

	s32 ret_val = 0;

   196

   197

	if (offset > MAX_PHY_REG_ADDRESS) {

   198

		hw_dbg("PHY Address %d is out of range\n", offset);

   199

		ret_val = -E1000_ERR_PARAM;

   200

		goto out;

   201

	}

   202

   203

	/* Set up Op-code, Phy Address, and register offset in the MDI

   204

	 * Control register.  The MAC will take care of interfacing with the

   205

	 * PHY to retrieve the desired data.

   206

	 */

   207

	mdic = (((u32)data) |

   208

		(offset << E1000_MDIC_REG_SHIFT) |

   209

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   210

		(E1000_MDIC_OP_WRITE));

   211

   212

	wr32(E1000_MDIC, mdic);

   213

   214

	/* Poll the ready bit to see if the MDI read completed

   215

	 * Increasing the time out as testing showed failures with

   216

	 * the lower time out

   217

	 */

   218

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   219

		udelay(50);

   220

		mdic = rd32(E1000_MDIC);

   221

		if (mdic & E1000_MDIC_READY)

   222

			break;

   223

	}

   224

	if (!(mdic & E1000_MDIC_READY)) {

   225

		hw_dbg("MDI Write did not complete\n");

   226

		ret_val = -E1000_ERR_PHY;

   227

		goto out;

   228

	}

   229

	if (mdic & E1000_MDIC_ERROR) {

   230

		hw_dbg("MDI Error\n");

   231

		ret_val = -E1000_ERR_PHY;

   232

		goto out;

   233

	}

   234

   235

out:

   236

	return ret_val;

   237

}

   238

   239

/**

   240

 *  igb_read_phy_reg_i2c - Read PHY register using i2c

   241

 *  @hw: pointer to the HW structure

   242

 *  @offset: register offset to be read

   243

 *  @data: pointer to the read data

   244

 *

   245

 *  Reads the PHY register at offset using the i2c interface and stores the

   246

 *  retrieved information in data.

   247

 **/

   248

s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)

   249

{

   250

	struct e1000_phy_info *phy = &hw->phy;

   251

	u32 i, i2ccmd = 0;

   252

   253

	/* Set up Op-code, Phy Address, and register address in the I2CCMD

   254

	 * register.  The MAC will take care of interfacing with the

   255

	 * PHY to retrieve the desired data.

   256

	 */

   257

	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |

   258

		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |

   259

		  (E1000_I2CCMD_OPCODE_READ));

   260

   261

	wr32(E1000_I2CCMD, i2ccmd);

   262

   263

	/* Poll the ready bit to see if the I2C read completed */

   264

	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {

   265

		udelay(50);

   266

		i2ccmd = rd32(E1000_I2CCMD);

   267

		if (i2ccmd & E1000_I2CCMD_READY)

   268

			break;

   269

	}

   270

	if (!(i2ccmd & E1000_I2CCMD_READY)) {

   271

		hw_dbg("I2CCMD Read did not complete\n");

   272

		return -E1000_ERR_PHY;

   273

	}

   274

	if (i2ccmd & E1000_I2CCMD_ERROR) {

   275

		hw_dbg("I2CCMD Error bit set\n");

   276

		return -E1000_ERR_PHY;

   277

	}

   278

   279

	/* Need to byte-swap the 16-bit value. */

   280

	*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);

   281

   282

	return 0;

   283

}

   284

   285

/**

   286

 *  igb_write_phy_reg_i2c - Write PHY register using i2c

   287

 *  @hw: pointer to the HW structure

   288

 *  @offset: register offset to write to

   289

 *  @data: data to write at register offset

   290

 *

   291

 *  Writes the data to PHY register at the offset using the i2c interface.

   292

 **/

   293

s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)

   294

{

   295

	struct e1000_phy_info *phy = &hw->phy;

   296

	u32 i, i2ccmd = 0;

   297

	u16 phy_data_swapped;

   298

   299

	/* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/

   300

	if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {

   301

		hw_dbg("PHY I2C Address %d is out of range.\n",

   302

			  hw->phy.addr);

   303

		return -E1000_ERR_CONFIG;

   304

	}

   305

   306

	/* Swap the data bytes for the I2C interface */

   307

	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);

   308

   309

	/* Set up Op-code, Phy Address, and register address in the I2CCMD

   310

	 * register.  The MAC will take care of interfacing with the

   311

	 * PHY to retrieve the desired data.

   312

	 */

   313

	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |

   314

		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |

   315

		  E1000_I2CCMD_OPCODE_WRITE |

   316

		  phy_data_swapped);

   317

   318

	wr32(E1000_I2CCMD, i2ccmd);

   319

   320

	/* Poll the ready bit to see if the I2C read completed */

   321

	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {

   322

		udelay(50);

   323

		i2ccmd = rd32(E1000_I2CCMD);

   324

		if (i2ccmd & E1000_I2CCMD_READY)

   325

			break;

   326

	}

   327

	if (!(i2ccmd & E1000_I2CCMD_READY)) {

   328

		hw_dbg("I2CCMD Write did not complete\n");

   329

		return -E1000_ERR_PHY;

   330

	}

   331

	if (i2ccmd & E1000_I2CCMD_ERROR) {

   332

		hw_dbg("I2CCMD Error bit set\n");

   333

		return -E1000_ERR_PHY;

   334

	}

   335

   336

	return 0;

   337

}

   338

   339

/**

   340

 *  igb_read_sfp_data_byte - Reads SFP module data.

   341

 *  @hw: pointer to the HW structure

   342

 *  @offset: byte location offset to be read

   343

 *  @data: read data buffer pointer

   344

 *

   345

 *  Reads one byte from SFP module data stored

   346

 *  in SFP resided EEPROM memory or SFP diagnostic area.

   347

 *  Function should be called with

   348

 *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access

   349

 *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters

   350

 *  access

   351

 **/

   352

s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)

   353

{

   354

	u32 i = 0;

   355

	u32 i2ccmd = 0;

   356

	u32 data_local = 0;

   357

   358

	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {

   359

		hw_dbg("I2CCMD command address exceeds upper limit\n");

   360

		return -E1000_ERR_PHY;

   361

	}

   362

   363

	/* Set up Op-code, EEPROM Address,in the I2CCMD

   364

	 * register. The MAC will take care of interfacing with the

   365

	 * EEPROM to retrieve the desired data.

   366

	 */

   367

	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |

   368

		  E1000_I2CCMD_OPCODE_READ);

   369

   370

	wr32(E1000_I2CCMD, i2ccmd);

   371

   372

	/* Poll the ready bit to see if the I2C read completed */

   373

	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {

   374

		udelay(50);

   375

		data_local = rd32(E1000_I2CCMD);

   376

		if (data_local & E1000_I2CCMD_READY)

   377

			break;

   378

	}

   379

	if (!(data_local & E1000_I2CCMD_READY)) {

   380

		hw_dbg("I2CCMD Read did not complete\n");

   381

		return -E1000_ERR_PHY;

   382

	}

   383

	if (data_local & E1000_I2CCMD_ERROR) {

   384

		hw_dbg("I2CCMD Error bit set\n");

   385

		return -E1000_ERR_PHY;

   386

	}

   387

	*data = (u8) data_local & 0xFF;

   388

   389

	return 0;

   390

}

   391

   392

/**

   393

 *  igb_read_phy_reg_igp - Read igp PHY register

   394

 *  @hw: pointer to the HW structure

   395

 *  @offset: register offset to be read

   396

 *  @data: pointer to the read data

   397

 *

   398

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   399

 *  and storing the retrieved information in data.  Release any acquired

   400

 *  semaphores before exiting.

   401

 **/

   402

s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)

   403

{

   404

	s32 ret_val = 0;

   405

   406

	if (!(hw->phy.ops.acquire))

   407

		goto out;

   408

   409

	ret_val = hw->phy.ops.acquire(hw);

   410

	if (ret_val)

   411

		goto out;

   412

   413

	if (offset > MAX_PHY_MULTI_PAGE_REG) {

   414

		ret_val = igb_write_phy_reg_mdic(hw,

   415

						 IGP01E1000_PHY_PAGE_SELECT,

   416

						 (u16)offset);

   417

		if (ret_val) {

   418

			hw->phy.ops.release(hw);

   419

			goto out;

   420

		}

   421

	}

   422

   423

	ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   424

					data);

   425

   426

	hw->phy.ops.release(hw);

   427

   428

out:

   429

	return ret_val;

   430

}

   431

   432

/**

   433

 *  igb_write_phy_reg_igp - Write igp PHY register

   434

 *  @hw: pointer to the HW structure

   435

 *  @offset: register offset to write to

   436

 *  @data: data to write at register offset

   437

 *

   438

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   439

 *  at the offset.  Release any acquired semaphores before exiting.

   440

 **/

   441

s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)

   442

{

   443

	s32 ret_val = 0;

   444

   445

	if (!(hw->phy.ops.acquire))

   446

		goto out;

   447

   448

	ret_val = hw->phy.ops.acquire(hw);

   449

	if (ret_val)

   450

		goto out;

   451

   452

	if (offset > MAX_PHY_MULTI_PAGE_REG) {

   453

		ret_val = igb_write_phy_reg_mdic(hw,

   454

						 IGP01E1000_PHY_PAGE_SELECT,

   455

						 (u16)offset);

   456

		if (ret_val) {

   457

			hw->phy.ops.release(hw);

   458

			goto out;

   459

		}

   460

	}

   461

   462

	ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   463

					 data);

   464

   465

	hw->phy.ops.release(hw);

   466

   467

out:

   468

	return ret_val;

   469

}

   470

   471

/**

   472

 *  igb_copper_link_setup_82580 - Setup 82580 PHY for copper link

   473

 *  @hw: pointer to the HW structure

   474

 *

   475

 *  Sets up Carrier-sense on Transmit and downshift values.

   476

 **/

   477

s32 igb_copper_link_setup_82580(struct e1000_hw *hw)

   478

{

   479

	struct e1000_phy_info *phy = &hw->phy;

   480

	s32 ret_val;

   481

	u16 phy_data;

   482

   483

	if (phy->reset_disable) {

   484

		ret_val = 0;

   485

		goto out;

   486

	}

   487

   488

	if (phy->type == e1000_phy_82580) {

   489

		ret_val = hw->phy.ops.reset(hw);

   490

		if (ret_val) {

   491

			hw_dbg("Error resetting the PHY.\n");

   492

			goto out;

   493

		}

   494

	}

   495

   496

	/* Enable CRS on TX. This must be set for half-duplex operation. */

   497

	ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);

   498

	if (ret_val)

   499

		goto out;

   500

   501

	phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;

   502

   503

	/* Enable downshift */

   504

	phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;

   505

   506

	ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);

   507

	if (ret_val)

   508

		goto out;

   509

   510

	/* Set MDI/MDIX mode */

   511

	ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);

   512

	if (ret_val)

   513

		goto out;

   514

	phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;

   515

	/* Options:

   516

	 *   0 - Auto (default)

   517

	 *   1 - MDI mode

   518

	 *   2 - MDI-X mode

   519

	 */

   520

	switch (hw->phy.mdix) {

   521

	case 1:

   522

		break;

   523

	case 2:

   524

		phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;

   525

		break;

   526

	case 0:

   527

	default:

   528

		phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;

   529

		break;