1

/* Intel(R) Gigabit Ethernet Linux driver

     2

 * Copyright(c) 2007-2014 Intel Corporation.

     3

 *

     4

 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

     8

 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

    13

 * You should have received a copy of the GNU General Public License along with

    14

 * this program; if not, see <http://www.gnu.org/licenses/>.

    15

 *

    16

 * The full GNU General Public License is included in this distribution in

    17

 * the file called "COPYING".

    18

 *

    19

 * Contact Information:

    20

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    21

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    22

 */

    23

    24

/* e1000_82575

    25

 * e1000_82576

    26

 */

    27

    28

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

    29

    30

#include <linux/types.h>

    31

#include <linux/if_ether.h>

    32

#include <linux/i2c.h>

    33

    34

#include "e1000_mac-3.18-ethercat.h"

    35

#include "e1000_82575-3.18-ethercat.h"

    36

#include "e1000_i210-3.18-ethercat.h"

    37

    38

static s32  igb_get_invariants_82575(struct e1000_hw *);

    39

static s32  igb_acquire_phy_82575(struct e1000_hw *);

    40

static void igb_release_phy_82575(struct e1000_hw *);

    41

static s32  igb_acquire_nvm_82575(struct e1000_hw *);

    42

static void igb_release_nvm_82575(struct e1000_hw *);

    43

static s32  igb_check_for_link_82575(struct e1000_hw *);

    44

static s32  igb_get_cfg_done_82575(struct e1000_hw *);

    45

static s32  igb_init_hw_82575(struct e1000_hw *);

    46

static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);

    47

static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);

    48

static s32  igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);

    49

static s32  igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);

    50

static s32  igb_reset_hw_82575(struct e1000_hw *);

    51

static s32  igb_reset_hw_82580(struct e1000_hw *);

    52

static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);

    53

static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);

    54

static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);

    55

static s32  igb_setup_copper_link_82575(struct e1000_hw *);

    56

static s32  igb_setup_serdes_link_82575(struct e1000_hw *);

    57

static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);

    58

static void igb_clear_hw_cntrs_82575(struct e1000_hw *);

    59

static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);

    60

static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,

    61

						 u16 *);

    62

static s32  igb_get_phy_id_82575(struct e1000_hw *);

    63

static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);

    64

static bool igb_sgmii_active_82575(struct e1000_hw *);

    65

static s32  igb_reset_init_script_82575(struct e1000_hw *);

    66

static s32  igb_read_mac_addr_82575(struct e1000_hw *);

    67

static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);

    68

static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);

    69

static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);

    70

static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);

    71

static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);

    72

static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);

    73

static const u16 e1000_82580_rxpbs_table[] = {

    74

	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };

    75

    76

/**

    77

 *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO

    78

 *  @hw: pointer to the HW structure

    79

 *

    80

 *  Called to determine if the I2C pins are being used for I2C or as an

    81

 *  external MDIO interface since the two options are mutually exclusive.

    82

 **/

    83

static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)

    84

{

    85

	u32 reg = 0;

    86

	bool ext_mdio = false;

    87

    88

	switch (hw->mac.type) {

    89

	case e1000_82575:

    90

	case e1000_82576:

    91

		reg = rd32(E1000_MDIC);

    92

		ext_mdio = !!(reg & E1000_MDIC_DEST);

    93

		break;

    94

	case e1000_82580:

    95

	case e1000_i350:

    96

	case e1000_i354:

    97

	case e1000_i210:

    98

	case e1000_i211:

    99

		reg = rd32(E1000_MDICNFG);

   100

		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);

   101

		break;

   102

	default:

   103

		break;

   104

	}

   105

	return ext_mdio;

   106

}

   107

   108

/**

   109

 *  igb_check_for_link_media_swap - Check which M88E1112 interface linked

   110

 *  @hw: pointer to the HW structure

   111

 *

   112

 *  Poll the M88E1112 interfaces to see which interface achieved link.

   113

 */

   114

static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)

   115

{

   116

	struct e1000_phy_info *phy = &hw->phy;

   117

	s32 ret_val;

   118

	u16 data;

   119

	u8 port = 0;

   120

   121

	/* Check the copper medium. */

   122

	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

   123

	if (ret_val)

   124

		return ret_val;

   125

   126

	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);

   127

	if (ret_val)

   128

		return ret_val;

   129

   130

	if (data & E1000_M88E1112_STATUS_LINK)

   131

		port = E1000_MEDIA_PORT_COPPER;

   132

   133

	/* Check the other medium. */

   134

	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);

   135

	if (ret_val)

   136

		return ret_val;

   137

   138

	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);

   139

	if (ret_val)

   140

		return ret_val;

   141

   142

	/* reset page to 0 */

   143

	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);

   144

	if (ret_val)

   145

		return ret_val;

   146

   147

	if (data & E1000_M88E1112_STATUS_LINK)

   148

		port = E1000_MEDIA_PORT_OTHER;

   149

   150

	/* Determine if a swap needs to happen. */

   151

	if (port && (hw->dev_spec._82575.media_port != port)) {

   152

		hw->dev_spec._82575.media_port = port;

   153

		hw->dev_spec._82575.media_changed = true;

   154

	} else {

   155

		ret_val = igb_check_for_link_82575(hw);

   156

	}

   157

   158

	return 0;

   159

}

   160

   161

/**

   162

 *  igb_init_phy_params_82575 - Init PHY func ptrs.

   163

 *  @hw: pointer to the HW structure

   164

 **/

   165

static s32 igb_init_phy_params_82575(struct e1000_hw *hw)

   166

{

   167

	struct e1000_phy_info *phy = &hw->phy;

   168

	s32 ret_val = 0;

   169

	u32 ctrl_ext;

   170

   171

	if (hw->phy.media_type != e1000_media_type_copper) {

   172

		phy->type = e1000_phy_none;

   173

		goto out;

   174

	}

   175

   176

	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

   177

	phy->reset_delay_us	= 100;

   178

   179

	ctrl_ext = rd32(E1000_CTRL_EXT);

   180

   181

	if (igb_sgmii_active_82575(hw)) {

   182

		phy->ops.reset = igb_phy_hw_reset_sgmii_82575;

   183

		ctrl_ext |= E1000_CTRL_I2C_ENA;

   184

	} else {

   185

		phy->ops.reset = igb_phy_hw_reset;

   186

		ctrl_ext &= ~E1000_CTRL_I2C_ENA;

   187

	}

   188

   189

	wr32(E1000_CTRL_EXT, ctrl_ext);

   190

	igb_reset_mdicnfg_82580(hw);

   191

   192

	if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {

   193

		phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;

   194

		phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;

   195

	} else {

   196

		switch (hw->mac.type) {

   197

		case e1000_82580:

   198

		case e1000_i350:

   199

		case e1000_i354:

   200

			phy->ops.read_reg = igb_read_phy_reg_82580;

   201

			phy->ops.write_reg = igb_write_phy_reg_82580;

   202

			break;

   203

		case e1000_i210:

   204

		case e1000_i211:

   205

			phy->ops.read_reg = igb_read_phy_reg_gs40g;

   206

			phy->ops.write_reg = igb_write_phy_reg_gs40g;

   207

			break;

   208

		default:

   209

			phy->ops.read_reg = igb_read_phy_reg_igp;

   210

			phy->ops.write_reg = igb_write_phy_reg_igp;

   211

		}

   212

	}

   213

   214

	/* set lan id */

   215

	hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>

   216

			E1000_STATUS_FUNC_SHIFT;

   217

   218

	/* Set phy->phy_addr and phy->id. */

   219

	ret_val = igb_get_phy_id_82575(hw);

   220

	if (ret_val)

   221

		return ret_val;

   222

   223

	/* Verify phy id and set remaining function pointers */

   224

	switch (phy->id) {

   225

	case M88E1543_E_PHY_ID:

   226

	case I347AT4_E_PHY_ID:

   227

	case M88E1112_E_PHY_ID:

   228

	case M88E1111_I_PHY_ID:

   229

		phy->type		= e1000_phy_m88;

   230

		phy->ops.check_polarity	= igb_check_polarity_m88;

   231

		phy->ops.get_phy_info	= igb_get_phy_info_m88;

   232

		if (phy->id != M88E1111_I_PHY_ID)

   233

			phy->ops.get_cable_length =

   234

					 igb_get_cable_length_m88_gen2;

   235

		else

   236

			phy->ops.get_cable_length = igb_get_cable_length_m88;

   237

		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;

   238

		/* Check if this PHY is confgured for media swap. */

   239

		if (phy->id == M88E1112_E_PHY_ID) {

   240

			u16 data;

   241

   242

			ret_val = phy->ops.write_reg(hw,

   243

						     E1000_M88E1112_PAGE_ADDR,

   244

						     2);

   245

			if (ret_val)

   246

				goto out;

   247

   248

			ret_val = phy->ops.read_reg(hw,

   249

						    E1000_M88E1112_MAC_CTRL_1,

   250

						    &data);

   251

			if (ret_val)

   252

				goto out;

   253

   254

			data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>

   255

			       E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;

   256

			if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||

   257

			    data == E1000_M88E1112_AUTO_COPPER_BASEX)

   258

				hw->mac.ops.check_for_link =

   259

						igb_check_for_link_media_swap;

   260

		}

   261

		break;

   262

	case IGP03E1000_E_PHY_ID:

   263

		phy->type = e1000_phy_igp_3;

   264

		phy->ops.get_phy_info = igb_get_phy_info_igp;

   265

		phy->ops.get_cable_length = igb_get_cable_length_igp_2;

   266

		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;

   267

		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;

   268

		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;

   269

		break;

   270

	case I82580_I_PHY_ID:

   271

	case I350_I_PHY_ID:

   272

		phy->type = e1000_phy_82580;

   273

		phy->ops.force_speed_duplex =

   274

					 igb_phy_force_speed_duplex_82580;

   275

		phy->ops.get_cable_length = igb_get_cable_length_82580;

   276

		phy->ops.get_phy_info = igb_get_phy_info_82580;

   277

		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;

   278

		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;

   279

		break;

   280

	case I210_I_PHY_ID:

   281

		phy->type		= e1000_phy_i210;

   282

		phy->ops.check_polarity	= igb_check_polarity_m88;

   283

		phy->ops.get_phy_info	= igb_get_phy_info_m88;

   284

		phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;

   285

		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;

   286

		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;

   287

		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;

   288

		break;

   289

	default:

   290

		ret_val = -E1000_ERR_PHY;

   291

		goto out;

   292

	}

   293

   294

out:

   295

	return ret_val;

   296

}

   297

   298

/**

   299

 *  igb_init_nvm_params_82575 - Init NVM func ptrs.

   300

 *  @hw: pointer to the HW structure

   301

 **/

   302

static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)

   303

{

   304

	struct e1000_nvm_info *nvm = &hw->nvm;

   305

	u32 eecd = rd32(E1000_EECD);

   306

	u16 size;

   307

   308

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   309

		     E1000_EECD_SIZE_EX_SHIFT);

   310

   311

	/* Added to a constant, "size" becomes the left-shift value

   312

	 * for setting word_size.

   313

	 */

   314

	size += NVM_WORD_SIZE_BASE_SHIFT;

   315

   316

	/* Just in case size is out of range, cap it to the largest

   317

	 * EEPROM size supported

   318

	 */

   319

	if (size > 15)

   320

		size = 15;

   321

   322

	nvm->word_size = 1 << size;

   323

	nvm->opcode_bits = 8;

   324

	nvm->delay_usec = 1;

   325

   326

	switch (nvm->override) {

   327

	case e1000_nvm_override_spi_large:

   328

		nvm->page_size = 32;

   329

		nvm->address_bits = 16;

   330

		break;

   331

	case e1000_nvm_override_spi_small:

   332

		nvm->page_size = 8;

   333

		nvm->address_bits = 8;

   334

		break;

   335

	default:

   336

		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   337

		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?

   338

				    16 : 8;

   339

		break;

   340

	}

   341

	if (nvm->word_size == (1 << 15))

   342

		nvm->page_size = 128;

   343

   344

	nvm->type = e1000_nvm_eeprom_spi;

   345

   346

	/* NVM Function Pointers */

   347

	nvm->ops.acquire = igb_acquire_nvm_82575;

   348

	nvm->ops.release = igb_release_nvm_82575;

   349

	nvm->ops.write = igb_write_nvm_spi;

   350

	nvm->ops.validate = igb_validate_nvm_checksum;

   351

	nvm->ops.update = igb_update_nvm_checksum;

   352

	if (nvm->word_size < (1 << 15))

   353

		nvm->ops.read = igb_read_nvm_eerd;

   354

	else

   355

		nvm->ops.read = igb_read_nvm_spi;

   356

   357

	/* override generic family function pointers for specific descendants */

   358

	switch (hw->mac.type) {

   359

	case e1000_82580:

   360

		nvm->ops.validate = igb_validate_nvm_checksum_82580;

   361

		nvm->ops.update = igb_update_nvm_checksum_82580;

   362

		break;

   363

	case e1000_i354:

   364

	case e1000_i350:

   365

		nvm->ops.validate = igb_validate_nvm_checksum_i350;

   366

		nvm->ops.update = igb_update_nvm_checksum_i350;

   367

		break;

   368

	default:

   369

		break;

   370

	}

   371

   372

	return 0;

   373

}

   374

   375

/**

   376

 *  igb_init_mac_params_82575 - Init MAC func ptrs.

   377

 *  @hw: pointer to the HW structure

   378

 **/

   379

static s32 igb_init_mac_params_82575(struct e1000_hw *hw)

   380

{

   381

	struct e1000_mac_info *mac = &hw->mac;

   382

	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;

   383

   384

	/* Set mta register count */

   385

	mac->mta_reg_count = 128;

   386

	/* Set rar entry count */

   387

	switch (mac->type) {

   388

	case e1000_82576:

   389

		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;

   390

		break;

   391

	case e1000_82580:

   392

		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;

   393

		break;

   394

	case e1000_i350:

   395

	case e1000_i354:

   396

		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;

   397

		break;

   398

	default:

   399

		mac->rar_entry_count = E1000_RAR_ENTRIES_82575;

   400

		break;

   401

	}

   402

	/* reset */

   403

	if (mac->type >= e1000_82580)

   404

		mac->ops.reset_hw = igb_reset_hw_82580;

   405

	else

   406

		mac->ops.reset_hw = igb_reset_hw_82575;

   407

   408

	if (mac->type >= e1000_i210) {

   409

		mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;

   410

		mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;

   411

   412

	} else {

   413

		mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;

   414

		mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;

   415

	}

   416

   417

	/* Set if part includes ASF firmware */

   418

	mac->asf_firmware_present = true;

   419

	/* Set if manageability features are enabled. */

   420

	mac->arc_subsystem_valid =

   421

		(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)

   422

			? true : false;

   423

	/* enable EEE on i350 parts and later parts */

   424

	if (mac->type >= e1000_i350)

   425

		dev_spec->eee_disable = false;

   426

	else

   427

		dev_spec->eee_disable = true;

   428

	/* Allow a single clear of the SW semaphore on I210 and newer */

   429

	if (mac->type >= e1000_i210)

   430

		dev_spec->clear_semaphore_once = true;

   431

	/* physical interface link setup */

   432

	mac->ops.setup_physical_interface =

   433

		(hw->phy.media_type == e1000_media_type_copper)

   434

			? igb_setup_copper_link_82575

   435

			: igb_setup_serdes_link_82575;

   436

   437

	if (mac->type == e1000_82580) {

   438

		switch (hw->device_id) {

   439

		/* feature not supported on these id's */

   440

		case E1000_DEV_ID_DH89XXCC_SGMII:

   441

		case E1000_DEV_ID_DH89XXCC_SERDES:

   442

		case E1000_DEV_ID_DH89XXCC_BACKPLANE:

   443

		case E1000_DEV_ID_DH89XXCC_SFP:

   444

			break;

   445

		default:

   446

			hw->dev_spec._82575.mas_capable = true;

   447

			break;

   448

		}

   449

	}

   450

	return 0;

   451

}

   452

   453

/**

   454

 *  igb_set_sfp_media_type_82575 - derives SFP module media type.

   455

 *  @hw: pointer to the HW structure

   456

 *

   457

 *  The media type is chosen based on SFP module.

   458

 *  compatibility flags retrieved from SFP ID EEPROM.

   459

 **/

   460

static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)

   461

{

   462

	s32 ret_val = E1000_ERR_CONFIG;

   463

	u32 ctrl_ext = 0;

   464

	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;

   465

	struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;

   466

	u8 tranceiver_type = 0;

   467

	s32 timeout = 3;

   468

   469

	/* Turn I2C interface ON and power on sfp cage */

   470

	ctrl_ext = rd32(E1000_CTRL_EXT);

   471

	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;

   472

	wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);

   473

   474

	wrfl();

   475

   476

	/* Read SFP module data */

   477

	while (timeout) {

   478

		ret_val = igb_read_sfp_data_byte(hw,

   479

			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),

   480

			&tranceiver_type);

   481

		if (ret_val == 0)

   482

			break;

   483

		msleep(100);

   484

		timeout--;

   485

	}

   486

	if (ret_val != 0)

   487

		goto out;

   488

   489

	ret_val = igb_read_sfp_data_byte(hw,

   490

			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),

   491

			(u8 *)eth_flags);

   492

	if (ret_val != 0)

   493

		goto out;

   494

   495

	/* Check if there is some SFP module plugged and powered */

   496

	if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||

   497

	    (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {

   498

		dev_spec->module_plugged = true;

   499

		if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {

   500

			hw->phy.media_type = e1000_media_type_internal_serdes;

   501

		} else if (eth_flags->e100_base_fx) {

   502

			dev_spec->sgmii_active = true;

   503

			hw->phy.media_type = e1000_media_type_internal_serdes;

   504

		} else if (eth_flags->e1000_base_t) {

   505

			dev_spec->sgmii_active = true;

   506

			hw->phy.media_type = e1000_media_type_copper;

   507

		} else {

   508

			hw->phy.media_type = e1000_media_type_unknown;

   509

			hw_dbg("PHY module has not been recognized\n");

   510

			goto out;

   511

		}

   512

	} else {

   513

		hw->phy.media_type = e1000_media_type_unknown;

   514

	}

   515

	ret_val = 0;

   516

out:

   517

	/* Restore I2C interface setting */

   518

	wr32(E1000_CTRL_EXT, ctrl_ext);

   519

	return ret_val;

   520

}

   521

   522

static s32 igb_get_invariants_82575(struct e1000_hw *hw)

   523

{

   524

	struct e1000_mac_info *mac = &hw->mac;

   525

	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;

   526

	s32 ret_val;

   527

	u32 ctrl_ext = 0;

   528

	u32 link_mode = 0;

   529