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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2012 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

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    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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*******************************************************************************/

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/* 82562G 10/100 Network Connection

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 * 82562G-2 10/100 Network Connection

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 * 82562GT 10/100 Network Connection

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 * 82562GT-2 10/100 Network Connection

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 * 82562V 10/100 Network Connection

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 * 82562V-2 10/100 Network Connection

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 * 82566DC-2 Gigabit Network Connection

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 * 82566DC Gigabit Network Connection

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 * 82566DM-2 Gigabit Network Connection

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 * 82566DM Gigabit Network Connection

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 * 82566MC Gigabit Network Connection

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 * 82566MM Gigabit Network Connection

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 * 82567LM Gigabit Network Connection

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 * 82567LF Gigabit Network Connection

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 * 82567V Gigabit Network Connection

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 * 82567LM-2 Gigabit Network Connection

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 * 82567LF-2 Gigabit Network Connection

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 * 82567V-2 Gigabit Network Connection

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 * 82567LF-3 Gigabit Network Connection

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 * 82567LM-3 Gigabit Network Connection

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 * 82567LM-4 Gigabit Network Connection

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 * 82577LM Gigabit Network Connection

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 * 82577LC Gigabit Network Connection

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 * 82578DM Gigabit Network Connection

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 * 82578DC Gigabit Network Connection

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 * 82579LM Gigabit Network Connection

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 * 82579V Gigabit Network Connection

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 */

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#include "e1000-3.8-ethercat.h"

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#define ICH_FLASH_GFPREG		0x0000

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#define ICH_FLASH_HSFSTS		0x0004

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#define ICH_FLASH_HSFCTL		0x0006

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#define ICH_FLASH_FADDR			0x0008

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#define ICH_FLASH_FDATA0		0x0010

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#define ICH_FLASH_PR0			0x0074

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#define ICH_FLASH_READ_COMMAND_TIMEOUT	500

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#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500

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#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000

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#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

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#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

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#define ICH_CYCLE_READ			0

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#define ICH_CYCLE_WRITE			2

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#define ICH_CYCLE_ERASE			3

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#define FLASH_GFPREG_BASE_MASK		0x1FFF

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#define FLASH_SECTOR_ADDR_SHIFT		12

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#define ICH_FLASH_SEG_SIZE_256		256

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#define ICH_FLASH_SEG_SIZE_4K		4096

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#define ICH_FLASH_SEG_SIZE_8K		8192

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#define ICH_FLASH_SEG_SIZE_64K		65536

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#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */

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/* FW established a valid mode */

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#define E1000_ICH_FWSM_FW_VALID		0x00008000

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    90

#define E1000_ICH_MNG_IAMT_MODE		0x2

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#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \

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				 (ID_LED_DEF1_OFF2 <<  8) | \

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				 (ID_LED_DEF1_ON2  <<  4) | \

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				 (ID_LED_DEF1_DEF2))

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#define E1000_ICH_NVM_SIG_WORD		0x13

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#define E1000_ICH_NVM_SIG_MASK		0xC000

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#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0

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#define E1000_ICH_NVM_SIG_VALUE         0x80

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#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

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#define E1000_FEXTNVM_SW_CONFIG		1

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#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

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#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK    0x0C000000

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#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC  0x08000000

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#define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7

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#define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7

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#define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3

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#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL

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   116

#define E1000_ICH_RAR_ENTRIES		7

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#define E1000_PCH2_RAR_ENTRIES		5 /* RAR[0], SHRA[0-3] */

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#define E1000_PCH_LPT_RAR_ENTRIES	12 /* RAR[0], SHRA[0-10] */

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#define PHY_PAGE_SHIFT 5

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#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

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			   ((reg) & MAX_PHY_REG_ADDRESS))

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#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */

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#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */

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#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002

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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

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#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200

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#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */

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   132

#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */

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/* SMBus Control Phy Register */

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#define CV_SMB_CTRL		PHY_REG(769, 23)

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#define CV_SMB_CTRL_FORCE_SMBUS	0x0001

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/* SMBus Address Phy Register */

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#define HV_SMB_ADDR            PHY_REG(768, 26)

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#define HV_SMB_ADDR_MASK       0x007F

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#define HV_SMB_ADDR_PEC_EN     0x0200

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#define HV_SMB_ADDR_VALID      0x0080

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#define HV_SMB_ADDR_FREQ_MASK           0x1100

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#define HV_SMB_ADDR_FREQ_LOW_SHIFT      8

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#define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12

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   147

/* PHY Power Management Control */

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#define HV_PM_CTRL		PHY_REG(770, 17)

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#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA	0x100

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   151

/* PHY Low Power Idle Control */

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#define I82579_LPI_CTRL				PHY_REG(772, 20)

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#define I82579_LPI_CTRL_ENABLE_MASK		0x6000

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#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80

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/* EMI Registers */

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#define I82579_EMI_ADDR         0x10

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#define I82579_EMI_DATA         0x11

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#define I82579_LPI_UPDATE_TIMER 0x4805	/* in 40ns units + 40 ns base value */

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#define I82579_MSE_THRESHOLD    0x084F	/* Mean Square Error Threshold */

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#define I82579_MSE_LINK_DOWN    0x2411	/* MSE count before dropping link */

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#define I217_EEE_ADVERTISEMENT  0x8001	/* IEEE MMD Register 7.60 */

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#define I217_EEE_LP_ABILITY     0x8002	/* IEEE MMD Register 7.61 */

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#define I217_EEE_100_SUPPORTED  (1 << 1)	/* 100BaseTx EEE supported */

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/* Intel Rapid Start Technology Support */

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#define I217_PROXY_CTRL                 BM_PHY_REG(BM_WUC_PAGE, 70)

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#define I217_PROXY_CTRL_AUTO_DISABLE    0x0080

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#define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)

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#define I217_SxCTRL_ENABLE_LPI_RESET    0x1000

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#define I217_CGFREG                     PHY_REG(772, 29)

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#define I217_CGFREG_ENABLE_MTA_RESET    0x0002

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#define I217_MEMPWR                     PHY_REG(772, 26)

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#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010

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/* Strapping Option Register - RO */

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#define E1000_STRAP                     0x0000C

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#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

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#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

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#define E1000_STRAP_SMT_FREQ_MASK       0x00003000

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#define E1000_STRAP_SMT_FREQ_SHIFT      12

   182

   183

/* OEM Bits Phy Register */

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#define HV_OEM_BITS            PHY_REG(768, 25)

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#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */

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#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */

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#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */

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   189

#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */

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#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */

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   192

/* KMRN Mode Control */

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#define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)

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#define HV_KMRN_MDIO_SLOW      0x0400

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   196

/* KMRN FIFO Control and Status */

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#define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)

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#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000

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#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12

   200

   201

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

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/* Offset 04h HSFSTS */

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union ich8_hws_flash_status {

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	struct ich8_hsfsts {

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		u16 flcdone    :1; /* bit 0 Flash Cycle Done */

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		u16 flcerr     :1; /* bit 1 Flash Cycle Error */

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		u16 dael       :1; /* bit 2 Direct Access error Log */

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		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */

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		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */

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		u16 reserved1  :2; /* bit 13:6 Reserved */

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		u16 reserved2  :6; /* bit 13:6 Reserved */

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		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */

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		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */

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	} hsf_status;

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	u16 regval;

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};

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   218

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

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/* Offset 06h FLCTL */

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union ich8_hws_flash_ctrl {

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	struct ich8_hsflctl {

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		u16 flcgo      :1;   /* 0 Flash Cycle Go */

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		u16 flcycle    :2;   /* 2:1 Flash Cycle */

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		u16 reserved   :5;   /* 7:3 Reserved  */

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		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */

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		u16 flockdn    :6;   /* 15:10 Reserved */

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	} hsf_ctrl;

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	u16 regval;

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};

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/* ICH Flash Region Access Permissions */

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union ich8_hws_flash_regacc {

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	struct ich8_flracc {

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		u32 grra      :8; /* 0:7 GbE region Read Access */

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		u32 grwa      :8; /* 8:15 GbE region Write Access */

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		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */

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		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */

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	} hsf_flregacc;

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	u16 regval;

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};

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   242

/* ICH Flash Protected Region */

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union ich8_flash_protected_range {

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	struct ich8_pr {

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		u32 base:13;     /* 0:12 Protected Range Base */

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		u32 reserved1:2; /* 13:14 Reserved */

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		u32 rpe:1;       /* 15 Read Protection Enable */

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		u32 limit:13;    /* 16:28 Protected Range Limit */

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		u32 reserved2:2; /* 29:30 Reserved */

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		u32 wpe:1;       /* 31 Write Protection Enable */

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	} range;

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	u32 regval;

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};

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static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);

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static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

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static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

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static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

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static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

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						u32 offset, u8 byte);

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static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u8 *data);

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static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u16 *data);

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static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

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					 u8 size, u16 *data);

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static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

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static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

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static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);

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static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

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static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

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static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

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static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

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static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

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static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

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static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

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static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

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static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

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static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

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static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

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static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

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static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

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static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

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static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

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static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

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static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

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static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

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static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

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static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

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{

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	return readw(hw->flash_address + reg);

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}

   294

   295

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

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{

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	return readl(hw->flash_address + reg);

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}

   299

   300

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

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{

   302

	writew(val, hw->flash_address + reg);

   303

}

   304

   305

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

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{

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	writel(val, hw->flash_address + reg);

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}

   309

   310

#define er16flash(reg)		__er16flash(hw, (reg))

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#define er32flash(reg)		__er32flash(hw, (reg))

   312

#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

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#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   314

   315

/**

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 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers

   317

 *  @hw: pointer to the HW structure

   318

 *

   319

 *  Test access to the PHY registers by reading the PHY ID registers.  If

   320

 *  the PHY ID is already known (e.g. resume path) compare it with known ID,

   321

 *  otherwise assume the read PHY ID is correct if it is valid.

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 *

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 *  Assumes the sw/fw/hw semaphore is already acquired.

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 **/

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static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)

   326

{

   327

	u16 phy_reg = 0;

   328

	u32 phy_id = 0;

   329

	s32 ret_val;

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	u16 retry_count;

   331

   332

	for (retry_count = 0; retry_count < 2; retry_count++) {

   333

		ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg);

   334

		if (ret_val || (phy_reg == 0xFFFF))

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			continue;

   336

		phy_id = (u32)(phy_reg << 16);

   337

   338

		ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg);

   339

		if (ret_val || (phy_reg == 0xFFFF)) {

   340

			phy_id = 0;

   341

			continue;

   342

		}

   343

		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

   344

		break;

   345

	}

   346

   347

	if (hw->phy.id) {

   348

		if (hw->phy.id == phy_id)

   349

			return true;

   350

	} else if (phy_id) {

   351

		hw->phy.id = phy_id;

   352

		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

   353

		return true;

   354

	}

   355

   356

	/* In case the PHY needs to be in mdio slow mode,

   357

	 * set slow mode and try to get the PHY id again.

   358

	 */

   359

	hw->phy.ops.release(hw);

   360

	ret_val = e1000_set_mdio_slow_mode_hv(hw);

   361

	if (!ret_val)

   362

		ret_val = e1000e_get_phy_id(hw);

   363

	hw->phy.ops.acquire(hw);

   364

   365

	return !ret_val;

   366

}

   367

   368

/**

   369

 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds

   370

 *  @hw: pointer to the HW structure

   371

 *

   372

 *  Workarounds/flow necessary for PHY initialization during driver load

   373

 *  and resume paths.

   374

 **/

   375

static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

   376

{

   377

	u32 mac_reg, fwsm = er32(FWSM);

   378

	s32 ret_val;

   379

	u16 phy_reg;

   380

   381

	ret_val = hw->phy.ops.acquire(hw);

   382

	if (ret_val) {

   383

		e_dbg("Failed to initialize PHY flow\n");

   384

		return ret_val;

   385

	}

   386

   387

	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is

   388

	 * inaccessible and resetting the PHY is not blocked, toggle the

   389

	 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   390

	 */

   391

	switch (hw->mac.type) {

   392

	case e1000_pch_lpt:

   393

		if (e1000_phy_is_accessible_pchlan(hw))

   394

			break;

   395

   396

		/* Before toggling LANPHYPC, see if PHY is accessible by

   397

		 * forcing MAC to SMBus mode first.

   398

		 */

   399

		mac_reg = er32(CTRL_EXT);

   400

		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

   401

		ew32(CTRL_EXT, mac_reg);

   402

   403

		/* fall-through */

   404

	case e1000_pch2lan:

   405

		/* Gate automatic PHY configuration by hardware on

   406

		 * non-managed 82579

   407

		 */

   408

		if ((hw->mac.type == e1000_pch2lan) &&

   409

		    !(fwsm & E1000_ICH_FWSM_FW_VALID))

   410

			e1000_gate_hw_phy_config_ich8lan(hw, true);

   411

   412

		if (e1000_phy_is_accessible_pchlan(hw)) {

   413

			if (hw->mac.type == e1000_pch_lpt) {

   414

				/* Unforce SMBus mode in PHY */

   415

				e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);

   416

				phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;

   417

				e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

   418

   419

				/* Unforce SMBus mode in MAC */

   420

				mac_reg = er32(CTRL_EXT);

   421

				mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   422

				ew32(CTRL_EXT, mac_reg);

   423

			}

   424

			break;

   425

		}

   426

   427

		/* fall-through */

   428

	case e1000_pchlan:

   429

		if ((hw->mac.type == e1000_pchlan) &&

   430

		    (fwsm & E1000_ICH_FWSM_FW_VALID))

   431

			break;

   432

   433

		if (hw->phy.ops.check_reset_block(hw)) {

   434

			e_dbg("Required LANPHYPC toggle blocked by ME\n");

   435

			break;

   436

		}

   437

   438

		e_dbg("Toggling LANPHYPC\n");

   439

   440

		/* Set Phy Config Counter to 50msec */

   441

		mac_reg = er32(FEXTNVM3);

   442

		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

   443

		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

   444

		ew32(FEXTNVM3, mac_reg);

   445

   446

		/* Toggle LANPHYPC Value bit */

   447

		mac_reg = er32(CTRL);

   448

		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;

   449

		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

   450

		ew32(CTRL, mac_reg);

   451

		e1e_flush();

   452

		udelay(10);

   453

		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   454

		ew32(CTRL, mac_reg);

   455

		e1e_flush();

   456

		if (hw->mac.type < e1000_pch_lpt) {

   457

			msleep(50);

   458

		} else {

   459

			u16 count = 20;

   460

			do {

   461

				usleep_range(5000, 10000);

   462

			} while (!(er32(CTRL_EXT) &

   463

				   E1000_CTRL_EXT_LPCD) && count--);

   464

		}

   465

		break;

   466

	default:

   467

		break;

   468

	}

   469

   470

	hw->phy.ops.release(hw);

   471

   472

	/* Reset the PHY before any access to it.  Doing so, ensures

   473

	 * that the PHY is in a known good state before we read/write

   474

	 * PHY registers.  The generic reset is sufficient here,

   475

	 * because we haven't determined the PHY type yet.

   476

	 */

   477

	ret_val = e1000e_phy_hw_reset_generic(hw);

   478

   479

	/* Ungate automatic PHY configuration on non-managed 82579 */

   480

	if ((hw->mac.type == e1000_pch2lan) &&

   481

	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   482

		usleep_range(10000, 20000);

   483

		e1000_gate_hw_phy_config_ich8lan(hw, false);

   484

	}

   485

   486

	return ret_val;

   487

}

   488

   489

/**

   490

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   491

 *  @hw: pointer to the HW structure

   492

 *

   493

 *  Initialize family-specific PHY parameters and function pointers.

   494

 **/

   495

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   496

{

   497

	struct e1000_phy_info *phy = &hw->phy;

   498

	s32 ret_val = 0;

   499

   500

	phy->addr                     = 1;

   501

	phy->reset_delay_us           = 100;

   502

   503

	phy->ops.set_page             = e1000_set_page_igp;

   504

	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   505

	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   506

	phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;

   507

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   508

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   509

	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   510

	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   511

	phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;

   512

	phy->ops.power_up             = e1000_power_up_phy_copper;

   513

	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   514

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   515

   516

	phy->id = e1000_phy_unknown;

   517

   518

	ret_val = e1000_init_phy_workarounds_pchlan(hw);

   519

	if (ret_val)

   520

		return ret_val;

   521

   522

	if (phy->id == e1000_phy_unknown)

   523

		switch (hw->mac.type) {

   524

		default:

   525

			ret_val = e1000e_get_phy_id(hw);

   526

			if (ret_val)

   527

				return ret_val;

   528

			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   529

				break;