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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2008 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

    28

    29

/*

    30

 * 80003ES2LAN Gigabit Ethernet Controller (Copper)

    31

 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    32

 */

    33

    34

#include <linux/netdevice.h>

    35

#include <linux/ethtool.h>

    36

#include <linux/delay.h>

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#include <linux/pci.h>

    38

    39

#include "e1000.h"

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    41

#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00

    42

#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02

    43

#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10

    44

#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F

    45

    46

#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008

    47

#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800

    48

#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010

    49

    50

#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

    51

#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000

    52

#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000

    53

    54

#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

    55

#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000

    56

    57

#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8

    58

#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9

    59

    60

/* GG82563 PHY Specific Status Register (Page 0, Register 16 */

    61

#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */

    62

#define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060

    63

#define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */

    64

#define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */

    65

#define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */

    66

    67

/* PHY Specific Control Register 2 (Page 0, Register 26) */

    68

#define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000

    69

						/* 1=Reverse Auto-Negotiation */

    70

    71

/* MAC Specific Control Register (Page 2, Register 21) */

    72

/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

    73

#define GG82563_MSCR_TX_CLK_MASK		 0x0007

    74

#define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004

    75

#define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005

    76

#define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007

    77

    78

#define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */

    79

    80

/* DSP Distance Register (Page 5, Register 26) */

    81

#define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M

    82

							   1 = 50-80M

    83

							   2 = 80-110M

    84

							   3 = 110-140M

    85

							   4 = >140M */

    86

    87

/* Kumeran Mode Control Register (Page 193, Register 16) */

    88

#define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800

    89

    90

/* Max number of times Kumeran read/write should be validated */

    91

#define GG82563_MAX_KMRN_RETRY  0x5

    92

    93

/* Power Management Control Register (Page 193, Register 20) */

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#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001

    95

					   /* 1=Enable SERDES Electrical Idle */

    96

    97

/* In-Band Control Register (Page 194, Register 18) */

    98

#define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */

    99

   100

/*

   101

 * A table for the GG82563 cable length where the range is defined

   102

 * with a lower bound at "index" and the upper bound at

   103

 * "index + 5".

   104

 */

   105

static const u16 e1000_gg82563_cable_length_table[] =

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	 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };

   107

   108

static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

   109

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   110

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

   111

static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

   112

static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

   113

static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

   114

static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

   115

static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);

   116

static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

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                                            u16 *data);

   118

static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

   119

                                             u16 data);

   120

   121

/**

   122

 *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

   123

 *  @hw: pointer to the HW structure

   124

 *

   125

 *  This is a function pointer entry point called by the api module.

   126

 **/

   127

static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

   128

{

   129

	struct e1000_phy_info *phy = &hw->phy;

   130

	s32 ret_val;

   131

   132

	if (hw->phy.media_type != e1000_media_type_copper) {

   133

		phy->type	= e1000_phy_none;

   134

		return 0;

   135

	}

   136

   137

	phy->addr		= 1;

   138

	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

   139

	phy->reset_delay_us      = 100;

   140

	phy->type		= e1000_phy_gg82563;

   141

   142

	/* This can only be done after all function pointers are setup. */

   143

	ret_val = e1000e_get_phy_id(hw);

   144

   145

	/* Verify phy id */

   146

	if (phy->id != GG82563_E_PHY_ID)

   147

		return -E1000_ERR_PHY;

   148

   149

	return ret_val;

   150

}

   151

   152

/**

   153

 *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

   154

 *  @hw: pointer to the HW structure

   155

 *

   156

 *  This is a function pointer entry point called by the api module.

   157

 **/

   158

static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

   159

{

   160

	struct e1000_nvm_info *nvm = &hw->nvm;

   161

	u32 eecd = er32(EECD);

   162

	u16 size;

   163

   164

	nvm->opcode_bits	= 8;

   165

	nvm->delay_usec	 = 1;

   166

	switch (nvm->override) {

   167

	case e1000_nvm_override_spi_large:

   168

		nvm->page_size    = 32;

   169

		nvm->address_bits = 16;

   170

		break;

   171

	case e1000_nvm_override_spi_small:

   172

		nvm->page_size    = 8;

   173

		nvm->address_bits = 8;

   174

		break;

   175

	default:

   176

		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   177

		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   178

		break;

   179

	}

   180

   181

	nvm->type = e1000_nvm_eeprom_spi;

   182

   183

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   184

			  E1000_EECD_SIZE_EX_SHIFT);

   185

   186

	/*

   187

	 * Added to a constant, "size" becomes the left-shift value

   188

	 * for setting word_size.

   189

	 */

   190

	size += NVM_WORD_SIZE_BASE_SHIFT;

   191

   192

	/* EEPROM access above 16k is unsupported */

   193

	if (size > 14)

   194

		size = 14;

   195

	nvm->word_size	= 1 << size;

   196

   197

	return 0;

   198

}

   199

   200

/**

   201

 *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   202

 *  @hw: pointer to the HW structure

   203

 *

   204

 *  This is a function pointer entry point called by the api module.

   205

 **/

   206

static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)

   207

{

   208

	struct e1000_hw *hw = &adapter->hw;

   209

	struct e1000_mac_info *mac = &hw->mac;

   210

	struct e1000_mac_operations *func = &mac->ops;

   211

   212

	/* Set media type */

   213

	switch (adapter->pdev->device) {

   214

	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   215

		hw->phy.media_type = e1000_media_type_internal_serdes;

   216

		break;

   217

	default:

   218

		hw->phy.media_type = e1000_media_type_copper;

   219

		break;

   220

	}

   221

   222

	/* Set mta register count */

   223

	mac->mta_reg_count = 128;

   224

	/* Set rar entry count */

   225

	mac->rar_entry_count = E1000_RAR_ENTRIES;

   226

	/* Set if manageability features are enabled. */

   227

	mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;

   228

   229

	/* check for link */

   230

	switch (hw->phy.media_type) {

   231

	case e1000_media_type_copper:

   232

		func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;

   233

		func->check_for_link = e1000e_check_for_copper_link;

   234

		break;

   235

	case e1000_media_type_fiber:

   236

		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;

   237

		func->check_for_link = e1000e_check_for_fiber_link;

   238

		break;

   239

	case e1000_media_type_internal_serdes:

   240

		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;

   241

		func->check_for_link = e1000e_check_for_serdes_link;

   242

		break;

   243

	default:

   244

		return -E1000_ERR_CONFIG;

   245

		break;

   246

	}

   247

   248

	return 0;

   249

}

   250

   251

static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   252

{

   253

	struct e1000_hw *hw = &adapter->hw;

   254

	s32 rc;

   255

   256

	rc = e1000_init_mac_params_80003es2lan(adapter);

   257

	if (rc)

   258

		return rc;

   259

   260

	rc = e1000_init_nvm_params_80003es2lan(hw);

   261

	if (rc)

   262

		return rc;

   263

   264

	rc = e1000_init_phy_params_80003es2lan(hw);

   265

	if (rc)

   266

		return rc;

   267

   268

	return 0;

   269

}

   270

   271

/**

   272

 *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   273

 *  @hw: pointer to the HW structure

   274

 *

   275

 *  A wrapper to acquire access rights to the correct PHY.  This is a

   276

 *  function pointer entry point called by the api module.

   277

 **/

   278

static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   279

{

   280

	u16 mask;

   281

   282

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   283

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   284

}

   285

   286

/**

   287

 *  e1000_release_phy_80003es2lan - Release rights to access PHY

   288

 *  @hw: pointer to the HW structure

   289

 *

   290

 *  A wrapper to release access rights to the correct PHY.  This is a

   291

 *  function pointer entry point called by the api module.

   292

 **/

   293

static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   294

{

   295

	u16 mask;

   296

   297

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   298

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   299

}

   300

   301

/**

   302

 *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register

   303

 *  @hw: pointer to the HW structure

   304

 *

   305

 *  Acquire the semaphore to access the Kumeran interface.

   306

 *

   307

 **/

   308

static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   309

{

   310

	u16 mask;

   311

   312

	mask = E1000_SWFW_CSR_SM;

   313

   314

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   315

}

   316

   317

/**

   318

 *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register

   319

 *  @hw: pointer to the HW structure

   320

 *

   321

 *  Release the semaphore used to access the Kumeran interface

   322

 **/

   323

static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   324

{

   325

	u16 mask;

   326

   327

	mask = E1000_SWFW_CSR_SM;

   328

   329

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   330

}

   331

   332

/**

   333

 *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   334

 *  @hw: pointer to the HW structure

   335

 *

   336

 *  Acquire the semaphore to access the EEPROM.  This is a function

   337

 *  pointer entry point called by the api module.

   338

 **/

   339

static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   340

{

   341

	s32 ret_val;

   342

   343

	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   344

	if (ret_val)

   345

		return ret_val;

   346

   347

	ret_val = e1000e_acquire_nvm(hw);

   348

   349

	if (ret_val)

   350

		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   351

   352

	return ret_val;

   353

}

   354

   355

/**

   356

 *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   357

 *  @hw: pointer to the HW structure

   358

 *

   359

 *  Release the semaphore used to access the EEPROM.  This is a

   360

 *  function pointer entry point called by the api module.

   361

 **/

   362

static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   363

{

   364

	e1000e_release_nvm(hw);

   365

	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   366

}

   367

   368

/**

   369

 *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   370

 *  @hw: pointer to the HW structure

   371

 *  @mask: specifies which semaphore to acquire

   372

 *

   373

 *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   374

 *  will also specify which port we're acquiring the lock for.

   375

 **/

   376

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   377

{

   378

	u32 swfw_sync;

   379

	u32 swmask = mask;

   380

	u32 fwmask = mask << 16;

   381

	s32 i = 0;

   382

	s32 timeout = 50;

   383

   384

	while (i < timeout) {

   385

		if (e1000e_get_hw_semaphore(hw))

   386

			return -E1000_ERR_SWFW_SYNC;

   387

   388

		swfw_sync = er32(SW_FW_SYNC);

   389

		if (!(swfw_sync & (fwmask | swmask)))

   390

			break;

   391

   392

		/*

   393

		 * Firmware currently using resource (fwmask)

   394

		 * or other software thread using resource (swmask)

   395

		 */

   396

		e1000e_put_hw_semaphore(hw);

   397

		mdelay(5);

   398

		i++;

   399

	}

   400

   401

	if (i == timeout) {

   402

		hw_dbg(hw,

   403

		       "Driver can't access resource, SW_FW_SYNC timeout.\n");

   404

		return -E1000_ERR_SWFW_SYNC;

   405

	}

   406

   407

	swfw_sync |= swmask;

   408

	ew32(SW_FW_SYNC, swfw_sync);

   409

   410

	e1000e_put_hw_semaphore(hw);

   411

   412

	return 0;

   413

}

   414

   415

/**

   416

 *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   417

 *  @hw: pointer to the HW structure

   418

 *  @mask: specifies which semaphore to acquire

   419

 *

   420

 *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   421

 *  will also specify which port we're releasing the lock for.

   422

 **/

   423

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   424

{

   425

	u32 swfw_sync;

   426

   427

	while (e1000e_get_hw_semaphore(hw) != 0);

   428

	/* Empty */

   429

   430

	swfw_sync = er32(SW_FW_SYNC);

   431

	swfw_sync &= ~mask;

   432

	ew32(SW_FW_SYNC, swfw_sync);

   433

   434

	e1000e_put_hw_semaphore(hw);

   435

}

   436

   437

/**

   438

 *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   439

 *  @hw: pointer to the HW structure

   440

 *  @offset: offset of the register to read

   441

 *  @data: pointer to the data returned from the operation

   442

 *

   443

 *  Read the GG82563 PHY register.  This is a function pointer entry

   444

 *  point called by the api module.

   445

 **/

   446

static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   447

						  u32 offset, u16 *data)

   448

{

   449

	s32 ret_val;

   450

	u32 page_select;

   451

	u16 temp;

   452

   453

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   454

	if (ret_val)

   455

		return ret_val;

   456

   457

	/* Select Configuration Page */

   458

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   459

		page_select = GG82563_PHY_PAGE_SELECT;

   460

	} else {

   461

		/*

   462

		 * Use Alternative Page Select register to access

   463

		 * registers 30 and 31

   464

		 */

   465

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   466

	}

   467

   468

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   469

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   470

	if (ret_val) {

   471

		e1000_release_phy_80003es2lan(hw);

   472

		return ret_val;

   473

	}

   474

   475

	/*

   476

	 * The "ready" bit in the MDIC register may be incorrectly set

   477

	 * before the device has completed the "Page Select" MDI

   478

	 * transaction.  So we wait 200us after each MDI command...

   479

	 */

   480

	udelay(200);

   481

   482

	/* ...and verify the command was successful. */

   483

	ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   484

   485

	if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   486

		ret_val = -E1000_ERR_PHY;

   487

		e1000_release_phy_80003es2lan(hw);

   488

		return ret_val;

   489

	}

   490

   491

	udelay(200);

   492

   493

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   494

					   data);

   495

   496

	udelay(200);

   497

	e1000_release_phy_80003es2lan(hw);

   498

   499

	return ret_val;

   500

}

   501

   502

/**

   503

 *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   504

 *  @hw: pointer to the HW structure

   505

 *  @offset: offset of the register to read

   506

 *  @data: value to write to the register

   507

 *

   508

 *  Write to the GG82563 PHY register.  This is a function pointer entry

   509

 *  point called by the api module.

   510

 **/

   511

static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   512

						   u32 offset, u16 data)

   513

{

   514

	s32 ret_val;

   515

	u32 page_select;

   516

	u16 temp;

   517

   518

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   519

	if (ret_val)

   520

		return ret_val;

   521

   522

	/* Select Configuration Page */

   523

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   524

		page_select = GG82563_PHY_PAGE_SELECT;

   525

	} else {

   526

		/*

   527

		 * Use Alternative Page Select register to access

   528

		 * registers 30 and 31

   529

		 */