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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2013 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

    28

    29

/* 80003ES2LAN Gigabit Ethernet Controller (Copper)

    30

 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    31

 */

    32

    33

#include "e1000-3.10-ethercat.h"

    34

    35

/* A table for the GG82563 cable length where the range is defined

    36

 * with a lower bound at "index" and the upper bound at

    37

 * "index + 5".

    38

 */

    39

static const u16 e1000_gg82563_cable_length_table[] = {

    40

	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF

    41

};

    42

    43

#define GG82563_CABLE_LENGTH_TABLE_SIZE \

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		ARRAY_SIZE(e1000_gg82563_cable_length_table)

    45

    46

static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

    47

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

    48

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

    49

static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

    50

static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

    51

static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

    52

static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

    53

static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

    54

					   u16 *data);

    55

static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

    56

					    u16 data);

    57

static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);

    58

    59

/**

    60

 *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

    61

 *  @hw: pointer to the HW structure

    62

 **/

    63

static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

    64

{

    65

	struct e1000_phy_info *phy = &hw->phy;

    66

	s32 ret_val;

    67

    68

	if (hw->phy.media_type != e1000_media_type_copper) {

    69

		phy->type	= e1000_phy_none;

    70

		return 0;

    71

	} else {

    72

		phy->ops.power_up = e1000_power_up_phy_copper;

    73

		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

    74

	}

    75

    76

	phy->addr		= 1;

    77

	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;

    78

	phy->reset_delay_us      = 100;

    79

	phy->type		= e1000_phy_gg82563;

    80

    81

	/* This can only be done after all function pointers are setup. */

    82

	ret_val = e1000e_get_phy_id(hw);

    83

    84

	/* Verify phy id */

    85

	if (phy->id != GG82563_E_PHY_ID)

    86

		return -E1000_ERR_PHY;

    87

    88

	return ret_val;

    89

}

    90

    91

/**

    92

 *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

    93

 *  @hw: pointer to the HW structure

    94

 **/

    95

static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

    96

{

    97

	struct e1000_nvm_info *nvm = &hw->nvm;

    98

	u32 eecd = er32(EECD);

    99

	u16 size;

   100

   101

	nvm->opcode_bits	= 8;

   102

	nvm->delay_usec	 = 1;

   103

	switch (nvm->override) {

   104

	case e1000_nvm_override_spi_large:

   105

		nvm->page_size    = 32;

   106

		nvm->address_bits = 16;

   107

		break;

   108

	case e1000_nvm_override_spi_small:

   109

		nvm->page_size    = 8;

   110

		nvm->address_bits = 8;

   111

		break;

   112

	default:

   113

		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   114

		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   115

		break;

   116

	}

   117

   118

	nvm->type = e1000_nvm_eeprom_spi;

   119

   120

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   121

		     E1000_EECD_SIZE_EX_SHIFT);

   122

   123

	/* Added to a constant, "size" becomes the left-shift value

   124

	 * for setting word_size.

   125

	 */

   126

	size += NVM_WORD_SIZE_BASE_SHIFT;

   127

   128

	/* EEPROM access above 16k is unsupported */

   129

	if (size > 14)

   130

		size = 14;

   131

	nvm->word_size	= 1 << size;

   132

   133

	return 0;

   134

}

   135

   136

/**

   137

 *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   138

 *  @hw: pointer to the HW structure

   139

 **/

   140

static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)

   141

{

   142

	struct e1000_mac_info *mac = &hw->mac;

   143

   144

	/* Set media type and media-dependent function pointers */

   145

	switch (hw->adapter->pdev->device) {

   146

	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   147

		hw->phy.media_type = e1000_media_type_internal_serdes;

   148

		mac->ops.check_for_link = e1000e_check_for_serdes_link;

   149

		mac->ops.setup_physical_interface =

   150

		    e1000e_setup_fiber_serdes_link;

   151

		break;

   152

	default:

   153

		hw->phy.media_type = e1000_media_type_copper;

   154

		mac->ops.check_for_link = e1000e_check_for_copper_link;

   155

		mac->ops.setup_physical_interface =

   156

		    e1000_setup_copper_link_80003es2lan;

   157

		break;

   158

	}

   159

   160

	/* Set mta register count */

   161

	mac->mta_reg_count = 128;

   162

	/* Set rar entry count */

   163

	mac->rar_entry_count = E1000_RAR_ENTRIES;

   164

	/* FWSM register */

   165

	mac->has_fwsm = true;

   166

	/* ARC supported; valid only if manageability features are enabled. */

   167

	mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);

   168

	/* Adaptive IFS not supported */

   169

	mac->adaptive_ifs = false;

   170

   171

	/* set lan id for port to determine which phy lock to use */

   172

	hw->mac.ops.set_lan_id(hw);

   173

   174

	return 0;

   175

}

   176

   177

static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   178

{

   179

	struct e1000_hw *hw = &adapter->hw;

   180

	s32 rc;

   181

   182

	rc = e1000_init_mac_params_80003es2lan(hw);

   183

	if (rc)

   184

		return rc;

   185

   186

	rc = e1000_init_nvm_params_80003es2lan(hw);

   187

	if (rc)

   188

		return rc;

   189

   190

	rc = e1000_init_phy_params_80003es2lan(hw);

   191

	if (rc)

   192

		return rc;

   193

   194

	return 0;

   195

}

   196

   197

/**

   198

 *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   199

 *  @hw: pointer to the HW structure

   200

 *

   201

 *  A wrapper to acquire access rights to the correct PHY.

   202

 **/

   203

static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   204

{

   205

	u16 mask;

   206

   207

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   208

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   209

}

   210

   211

/**

   212

 *  e1000_release_phy_80003es2lan - Release rights to access PHY

   213

 *  @hw: pointer to the HW structure

   214

 *

   215

 *  A wrapper to release access rights to the correct PHY.

   216

 **/

   217

static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   218

{

   219

	u16 mask;

   220

   221

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   222

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   223

}

   224

   225

/**

   226

 *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register

   227

 *  @hw: pointer to the HW structure

   228

 *

   229

 *  Acquire the semaphore to access the Kumeran interface.

   230

 *

   231

 **/

   232

static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   233

{

   234

	u16 mask;

   235

   236

	mask = E1000_SWFW_CSR_SM;

   237

   238

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   239

}

   240

   241

/**

   242

 *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register

   243

 *  @hw: pointer to the HW structure

   244

 *

   245

 *  Release the semaphore used to access the Kumeran interface

   246

 **/

   247

static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   248

{

   249

	u16 mask;

   250

   251

	mask = E1000_SWFW_CSR_SM;

   252

   253

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   254

}

   255

   256

/**

   257

 *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   258

 *  @hw: pointer to the HW structure

   259

 *

   260

 *  Acquire the semaphore to access the EEPROM.

   261

 **/

   262

static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   263

{

   264

	s32 ret_val;

   265

   266

	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   267

	if (ret_val)

   268

		return ret_val;

   269

   270

	ret_val = e1000e_acquire_nvm(hw);

   271

   272

	if (ret_val)

   273

		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   274

   275

	return ret_val;

   276

}

   277

   278

/**

   279

 *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   280

 *  @hw: pointer to the HW structure

   281

 *

   282

 *  Release the semaphore used to access the EEPROM.

   283

 **/

   284

static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   285

{

   286

	e1000e_release_nvm(hw);

   287

	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   288

}

   289

   290

/**

   291

 *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   292

 *  @hw: pointer to the HW structure

   293

 *  @mask: specifies which semaphore to acquire

   294

 *

   295

 *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   296

 *  will also specify which port we're acquiring the lock for.

   297

 **/

   298

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   299

{

   300

	u32 swfw_sync;

   301

	u32 swmask = mask;

   302

	u32 fwmask = mask << 16;

   303

	s32 i = 0;

   304

	s32 timeout = 50;

   305

   306

	while (i < timeout) {

   307

		if (e1000e_get_hw_semaphore(hw))

   308

			return -E1000_ERR_SWFW_SYNC;

   309

   310

		swfw_sync = er32(SW_FW_SYNC);

   311

		if (!(swfw_sync & (fwmask | swmask)))

   312

			break;

   313

   314

		/* Firmware currently using resource (fwmask)

   315

		 * or other software thread using resource (swmask)

   316

		 */

   317

		e1000e_put_hw_semaphore(hw);

   318

		mdelay(5);

   319

		i++;

   320

	}

   321

   322

	if (i == timeout) {

   323

		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");

   324

		return -E1000_ERR_SWFW_SYNC;

   325

	}

   326

   327

	swfw_sync |= swmask;

   328

	ew32(SW_FW_SYNC, swfw_sync);

   329

   330

	e1000e_put_hw_semaphore(hw);

   331

   332

	return 0;

   333

}

   334

   335

/**

   336

 *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   337

 *  @hw: pointer to the HW structure

   338

 *  @mask: specifies which semaphore to acquire

   339

 *

   340

 *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   341

 *  will also specify which port we're releasing the lock for.

   342

 **/

   343

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   344

{

   345

	u32 swfw_sync;

   346

   347

	while (e1000e_get_hw_semaphore(hw) != 0)

   348

		; /* Empty */

   349

   350

	swfw_sync = er32(SW_FW_SYNC);

   351

	swfw_sync &= ~mask;

   352

	ew32(SW_FW_SYNC, swfw_sync);

   353

   354

	e1000e_put_hw_semaphore(hw);

   355

}

   356

   357

/**

   358

 *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   359

 *  @hw: pointer to the HW structure

   360

 *  @offset: offset of the register to read

   361

 *  @data: pointer to the data returned from the operation

   362

 *

   363

 *  Read the GG82563 PHY register.

   364

 **/

   365

static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   366

						  u32 offset, u16 *data)

   367

{

   368

	s32 ret_val;

   369

	u32 page_select;

   370

	u16 temp;

   371

   372

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   373

	if (ret_val)

   374

		return ret_val;

   375

   376

	/* Select Configuration Page */

   377

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   378

		page_select = GG82563_PHY_PAGE_SELECT;

   379

	} else {

   380

		/* Use Alternative Page Select register to access

   381

		 * registers 30 and 31

   382

		 */

   383

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   384

	}

   385

   386

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   387

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   388

	if (ret_val) {

   389

		e1000_release_phy_80003es2lan(hw);

   390

		return ret_val;

   391

	}

   392

   393

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   394

		/* The "ready" bit in the MDIC register may be incorrectly set

   395

		 * before the device has completed the "Page Select" MDI

   396

		 * transaction.  So we wait 200us after each MDI command...

   397

		 */

   398

		usleep_range(200, 400);

   399

   400

		/* ...and verify the command was successful. */

   401

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   402

   403

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   404

			e1000_release_phy_80003es2lan(hw);

   405

			return -E1000_ERR_PHY;

   406

		}

   407

   408

		usleep_range(200, 400);

   409

   410

		ret_val = e1000e_read_phy_reg_mdic(hw,

   411

						   MAX_PHY_REG_ADDRESS & offset,

   412

						   data);

   413

   414

		usleep_range(200, 400);

   415

	} else {

   416

		ret_val = e1000e_read_phy_reg_mdic(hw,

   417

						   MAX_PHY_REG_ADDRESS & offset,

   418

						   data);

   419

	}

   420

   421

	e1000_release_phy_80003es2lan(hw);

   422

   423

	return ret_val;

   424

}

   425

   426

/**

   427

 *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   428

 *  @hw: pointer to the HW structure

   429

 *  @offset: offset of the register to read

   430

 *  @data: value to write to the register

   431

 *

   432

 *  Write to the GG82563 PHY register.

   433

 **/

   434

static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   435

						   u32 offset, u16 data)

   436

{

   437

	s32 ret_val;

   438

	u32 page_select;

   439

	u16 temp;

   440

   441

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   442

	if (ret_val)

   443

		return ret_val;

   444

   445

	/* Select Configuration Page */

   446

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   447

		page_select = GG82563_PHY_PAGE_SELECT;

   448

	} else {

   449

		/* Use Alternative Page Select register to access

   450

		 * registers 30 and 31

   451

		 */

   452

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   453

	}

   454

   455

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   456

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   457

	if (ret_val) {

   458

		e1000_release_phy_80003es2lan(hw);

   459

		return ret_val;

   460

	}

   461

   462

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   463

		/* The "ready" bit in the MDIC register may be incorrectly set

   464

		 * before the device has completed the "Page Select" MDI

   465

		 * transaction.  So we wait 200us after each MDI command...

   466

		 */

   467

		usleep_range(200, 400);

   468

   469

		/* ...and verify the command was successful. */

   470

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   471

   472

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   473

			e1000_release_phy_80003es2lan(hw);

   474

			return -E1000_ERR_PHY;

   475

		}

   476

   477

		usleep_range(200, 400);

   478

   479

		ret_val = e1000e_write_phy_reg_mdic(hw,

   480

						    MAX_PHY_REG_ADDRESS &

   481

						    offset, data);

   482

   483

		usleep_range(200, 400);

   484

	} else {

   485

		ret_val = e1000e_write_phy_reg_mdic(hw,

   486

						    MAX_PHY_REG_ADDRESS &

   487

						    offset, data);

   488

	}

   489

   490

	e1000_release_phy_80003es2lan(hw);

   491

   492

	return ret_val;

   493

}

   494

   495

/**

   496

 *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM

   497

 *  @hw: pointer to the HW structure

   498

 *  @offset: offset of the register to read

   499

 *  @words: number of words to write

   500

 *  @data: buffer of data to write to the NVM

   501

 *

   502

 *  Write "words" of data to the ESB2 NVM.

   503

 **/

   504

static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,

   505

				       u16 words, u16 *data)

   506

{

   507

	return e1000e_write_nvm_spi(hw, offset, words, data);

   508

}

   509

   510

/**

   511

 *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete

   512

 *  @hw: pointer to the HW structure

   513

 *

   514

 *  Wait a specific amount of time for manageability processes to complete.

   515

 *  This is a function pointer entry point called by the phy module.

   516

 **/

   517

static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)

   518

{

   519

	s32 timeout = PHY_CFG_TIMEOUT;

   520

	u32 mask = E1000_NVM_CFG_DONE_PORT_0;

   521

   522

	if (hw->bus.func == 1)

   523

		mask = E1000_NVM_CFG_DONE_PORT_1;

   524

   525

	while (timeout) {

   526

		if (er32(EEMNGCTL) & mask)

   527

			break;

   528

		usleep_range(1000, 2000);

   529

		timeout--;