1

/*

     2

     3

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

     4

     5

	Maintained by Jeff Garzik <jgarzik@pobox.com>

     6

	Copyright 2000-2002 Jeff Garzik

     7

     8

	Much code comes from Donald Becker's rtl8139.c driver,

     9

	versions 1.13 and older.  This driver was originally based

    10

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    11

    12

	-----<snip>-----

    13

    14

        	Written 1997-2001 by Donald Becker.

    15

		This software may be used and distributed according to the

    16

		terms of the GNU General Public License (GPL), incorporated

    17

		herein by reference.  Drivers based on or derived from this

    18

		code fall under the GPL and must retain the authorship,

    19

		copyright and license notice.  This file is not a complete

    20

		program and may only be used when the entire operating

    21

		system is licensed under the GPL.

    22

    23

		This driver is for boards based on the RTL8129 and RTL8139

    24

		PCI ethernet chips.

    25

    26

		The author may be reached as becker@scyld.com, or C/O Scyld

    27

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    28

		MD 21403

    29

    30

		Support and updates available at

    31

		http://www.scyld.com/network/rtl8139.html

    32

    33

		Twister-tuning table provided by Kinston

    34

		<shangh@realtek.com.tw>.

    35

    36

	-----<snip>-----

    37

    38

	This software may be used and distributed according to the terms

    39

	of the GNU General Public License, incorporated herein by reference.

    40

    41

	Contributors:

    42

    43

		Donald Becker - he wrote the original driver, kudos to him!

    44

		(but please don't e-mail him for support, this isn't his driver)

    45

    46

		Tigran Aivazian - bug fixes, skbuff free cleanup

    47

    48

		Martin Mares - suggestions for PCI cleanup

    49

    50

		David S. Miller - PCI DMA and softnet updates

    51

    52

		Ernst Gill - fixes ported from BSD driver

    53

    54

		Daniel Kobras - identified specific locations of

    55

			posted MMIO write bugginess

    56

    57

		Gerard Sharp - bug fix, testing and feedback

    58

    59

		David Ford - Rx ring wrap fix

    60

    61

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    62

		to find and fix a crucial bug on older chipsets.

    63

    64

		Donald Becker/Chris Butterworth/Marcus Westergren -

    65

		Noticed various Rx packet size-related buglets.

    66

    67

		Santiago Garcia Mantinan - testing and feedback

    68

    69

		Jens David - 2.2.x kernel backports

    70

    71

		Martin Dennett - incredibly helpful insight on undocumented

    72

		features of the 8139 chips

    73

    74

		Jean-Jacques Michel - bug fix

    75

    76

		Tobias Ringström - Rx interrupt status checking suggestion

    77

    78

		Andrew Morton - Clear blocked signals, avoid

    79

		buffer overrun setting current->comm.

    80

    81

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

    82

    83

		Robert Kuebel - Save kernel thread from dying on any signal.

    84

    85

	Submitting bug reports:

    86

    87

		"rtl8139-diag -mmmaaavvveefN" output

    88

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

    89

    90

*/

    91

    92

#define DRV_NAME	"8139too"

    93

#define DRV_VERSION	"0.9.28"

    94

    95

    96

#include <linux/module.h>

    97

#include <linux/kernel.h>

    98

#include <linux/compiler.h>

    99

#include <linux/pci.h>

   100

#include <linux/init.h>

   101

#include <linux/netdevice.h>

   102

#include <linux/etherdevice.h>

   103

#include <linux/rtnetlink.h>

   104

#include <linux/delay.h>

   105

#include <linux/ethtool.h>

   106

#include <linux/mii.h>

   107

#include <linux/completion.h>

   108

#include <linux/crc32.h>

   109

#include <linux/io.h>

   110

#include <linux/uaccess.h>

   111

#include <asm/irq.h>

   112

   113

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   114

#define PFX DRV_NAME ": "

   115

   116

/* Default Message level */

   117

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   118

                                 NETIF_MSG_PROBE  | \

   119

                                 NETIF_MSG_LINK)

   120

   121

   122

/* define to 1, 2 or 3 to enable copious debugging info */

   123

#define RTL8139_DEBUG 0

   124

   125

/* define to 1 to disable lightweight runtime debugging checks */

   126

#undef RTL8139_NDEBUG

   127

   128

   129

#if RTL8139_DEBUG

   130

/* note: prints function name for you */

   131

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)

   132

#else

   133

#  define DPRINTK(fmt, args...)

   134

#endif

   135

   136

#ifdef RTL8139_NDEBUG

   137

#  define assert(expr) do {} while (0)

   138

#else

   139

#  define assert(expr) \

   140

        if(unlikely(!(expr))) {				        \

   141

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   142

	#expr, __FILE__, __func__, __LINE__);			\

   143

        }

   144

#endif

   145

   146

   147

/* A few user-configurable values. */

   148

/* media options */

   149

#define MAX_UNITS 8

   150

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   151

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   152

   153

/* Whether to use MMIO or PIO. Default to MMIO. */

   154

#ifdef CONFIG_8139TOO_PIO

   155

static int use_io = 1;

   156

#else

   157

static int use_io = 0;

   158

#endif

   159

   160

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   161

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   162

static int multicast_filter_limit = 32;

   163

   164

/* bitmapped message enable number */

   165

static int debug = -1;

   166

   167

/*

   168

 * Receive ring size

   169

 * Warning: 64K ring has hardware issues and may lock up.

   170

 */

   171

#if defined(CONFIG_SH_DREAMCAST)

   172

#define RX_BUF_IDX 0	/* 8K ring */

   173

#else

   174

#define RX_BUF_IDX	2	/* 32K ring */

   175

#endif

   176

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   177

#define RX_BUF_PAD	16

   178

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   179

   180

#if RX_BUF_LEN == 65536

   181

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   182

#else

   183

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   184

#endif

   185

   186

/* Number of Tx descriptor registers. */

   187

#define NUM_TX_DESC	4

   188

   189

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   190

#define MAX_ETH_FRAME_SIZE	1536

   191

   192

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   193

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   194

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   195

   196

/* PCI Tuning Parameters

   197

   Threshold is bytes transferred to chip before transmission starts. */

   198

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   199

   200

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   201

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   202

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   203

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   204

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   205

   206

/* Operational parameters that usually are not changed. */

   207

/* Time in jiffies before concluding the transmitter is hung. */

   208

#define TX_TIMEOUT  (6*HZ)

   209

   210

   211

enum {

   212

	HAS_MII_XCVR = 0x010000,

   213

	HAS_CHIP_XCVR = 0x020000,

   214

	HAS_LNK_CHNG = 0x040000,

   215

};

   216

   217

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   218

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   219

#define RTL_MIN_IO_SIZE 0x80

   220

#define RTL8139B_IO_SIZE 256

   221

   222

#define RTL8129_CAPS	HAS_MII_XCVR

   223

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   224

   225

typedef enum {

   226

	RTL8139 = 0,

   227

	RTL8129,

   228

} board_t;

   229

   230

   231

/* indexed by board_t, above */

   232

static const struct {

   233

	const char *name;

   234

	u32 hw_flags;

   235

} board_info[] __devinitdata = {

   236

	{ "RealTek RTL8139", RTL8139_CAPS },

   237

	{ "RealTek RTL8129", RTL8129_CAPS },

   238

};

   239

   240

   241

static struct pci_device_id rtl8139_pci_tbl[] = {

   242

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   243

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   244

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   245

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   246

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   247

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   248

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   249

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   250

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   251

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   252

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   253

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   254

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   255

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   256

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   257

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   258

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   259

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   260

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   261

   262

#ifdef CONFIG_SH_SECUREEDGE5410

   263

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   264

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   265

#endif

   266

#ifdef CONFIG_8139TOO_8129

   267

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   268

#endif

   269

   270

	/* some crazy cards report invalid vendor ids like

   271

	 * 0x0001 here.  The other ids are valid and constant,

   272

	 * so we simply don't match on the main vendor id.

   273

	 */

   274

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   275

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   276

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   277

   278

	{0,}

   279

};

   280

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   281

   282

static struct {

   283

	const char str[ETH_GSTRING_LEN];

   284

} ethtool_stats_keys[] = {

   285

	{ "early_rx" },

   286

	{ "tx_buf_mapped" },

   287

	{ "tx_timeouts" },

   288

	{ "rx_lost_in_ring" },

   289

};

   290

   291

/* The rest of these values should never change. */

   292

   293

/* Symbolic offsets to registers. */

   294

enum RTL8139_registers {

   295

	MAC0		= 0,	 /* Ethernet hardware address. */

   296

	MAR0		= 8,	 /* Multicast filter. */

   297

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   298

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   299

	RxBuf		= 0x30,

   300

	ChipCmd		= 0x37,

   301

	RxBufPtr	= 0x38,

   302

	RxBufAddr	= 0x3A,

   303

	IntrMask	= 0x3C,

   304

	IntrStatus	= 0x3E,

   305

	TxConfig	= 0x40,

   306

	RxConfig	= 0x44,

   307

	Timer		= 0x48,	 /* A general-purpose counter. */

   308

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   309

	Cfg9346		= 0x50,

   310

	Config0		= 0x51,

   311

	Config1		= 0x52,

   312

	TimerInt	= 0x54,

   313

	MediaStatus	= 0x58,

   314

	Config3		= 0x59,

   315

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   316

	HltClk		= 0x5B,

   317

	MultiIntr	= 0x5C,

   318

	TxSummary	= 0x60,

   319

	BasicModeCtrl	= 0x62,

   320

	BasicModeStatus	= 0x64,

   321

	NWayAdvert	= 0x66,

   322

	NWayLPAR	= 0x68,

   323

	NWayExpansion	= 0x6A,

   324

	/* Undocumented registers, but required for proper operation. */

   325

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   326

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   327

	PARA78		= 0x78,

   328

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   329

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   330

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   331

};

   332

   333

enum ClearBitMasks {

   334

	MultiIntrClear	= 0xF000,

   335

	ChipCmdClear	= 0xE2,

   336

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   337

};

   338

   339

enum ChipCmdBits {

   340

	CmdReset	= 0x10,

   341

	CmdRxEnb	= 0x08,

   342

	CmdTxEnb	= 0x04,

   343

	RxBufEmpty	= 0x01,

   344

};

   345

   346

/* Interrupt register bits, using my own meaningful names. */

   347

enum IntrStatusBits {

   348

	PCIErr		= 0x8000,

   349

	PCSTimeout	= 0x4000,

   350

	RxFIFOOver	= 0x40,

   351

	RxUnderrun	= 0x20,

   352

	RxOverflow	= 0x10,

   353

	TxErr		= 0x08,

   354

	TxOK		= 0x04,

   355

	RxErr		= 0x02,

   356

	RxOK		= 0x01,

   357

   358

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   359

};

   360

   361

enum TxStatusBits {

   362

	TxHostOwns	= 0x2000,

   363

	TxUnderrun	= 0x4000,

   364

	TxStatOK	= 0x8000,

   365

	TxOutOfWindow	= 0x20000000,

   366

	TxAborted	= 0x40000000,

   367

	TxCarrierLost	= 0x80000000,

   368

};

   369

enum RxStatusBits {

   370

	RxMulticast	= 0x8000,

   371

	RxPhysical	= 0x4000,

   372

	RxBroadcast	= 0x2000,

   373

	RxBadSymbol	= 0x0020,

   374

	RxRunt		= 0x0010,

   375

	RxTooLong	= 0x0008,

   376

	RxCRCErr	= 0x0004,

   377

	RxBadAlign	= 0x0002,

   378

	RxStatusOK	= 0x0001,

   379

};

   380

   381

/* Bits in RxConfig. */

   382

enum rx_mode_bits {

   383

	AcceptErr	= 0x20,

   384

	AcceptRunt	= 0x10,

   385

	AcceptBroadcast	= 0x08,

   386

	AcceptMulticast	= 0x04,

   387

	AcceptMyPhys	= 0x02,

   388

	AcceptAllPhys	= 0x01,

   389

};

   390

   391

/* Bits in TxConfig. */

   392

enum tx_config_bits {

   393

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   394

        TxIFGShift	= 24,

   395

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   396

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   397

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   398

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   399

   400

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   401

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   402

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   403

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   404

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   405

   406

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   407

};

   408

   409

/* Bits in Config1 */

   410

enum Config1Bits {

   411

	Cfg1_PM_Enable	= 0x01,

   412

	Cfg1_VPD_Enable	= 0x02,

   413

	Cfg1_PIO	= 0x04,

   414

	Cfg1_MMIO	= 0x08,

   415

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   416

	Cfg1_Driver_Load = 0x20,

   417

	Cfg1_LED0	= 0x40,

   418

	Cfg1_LED1	= 0x80,

   419

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   420

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   421

};

   422

   423

/* Bits in Config3 */

   424

enum Config3Bits {

   425

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   426

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   427

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   428

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   429

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   430

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   431

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   432

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   433

};

   434

   435

/* Bits in Config4 */

   436

enum Config4Bits {

   437

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   438

};

   439

   440

/* Bits in Config5 */

   441

enum Config5Bits {

   442

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   443

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   444

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   445

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   446

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   447

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   448

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   449

};

   450

   451

enum RxConfigBits {

   452

	/* rx fifo threshold */

   453

	RxCfgFIFOShift	= 13,

   454

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   455

   456

	/* Max DMA burst */

   457

	RxCfgDMAShift	= 8,

   458

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   459

   460

	/* rx ring buffer length */

   461

	RxCfgRcv8K	= 0,

   462

	RxCfgRcv16K	= (1 << 11),

   463

	RxCfgRcv32K	= (1 << 12),

   464

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   465

   466

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   467

	RxNoWrap	= (1 << 7),

   468

};

   469

   470

/* Twister tuning parameters from RealTek.

   471

   Completely undocumented, but required to tune bad links on some boards. */

   472

enum CSCRBits {

   473

	CSCR_LinkOKBit		= 0x0400,

   474

	CSCR_LinkChangeBit	= 0x0800,

   475

	CSCR_LinkStatusBits	= 0x0f000,

   476

	CSCR_LinkDownOffCmd	= 0x003c0,

   477

	CSCR_LinkDownCmd	= 0x0f3c0,

   478

};

   479

   480

enum Cfg9346Bits {

   481

	Cfg9346_Lock	= 0x00,

   482

	Cfg9346_Unlock	= 0xC0,

   483

};

   484

   485

typedef enum {

   486

	CH_8139	= 0,

   487

	CH_8139_K,

   488

	CH_8139A,

   489

	CH_8139A_G,

   490

	CH_8139B,

   491

	CH_8130,

   492

	CH_8139C,

   493

	CH_8100,

   494

	CH_8100B_8139D,

   495

	CH_8101,

   496

} chip_t;

   497

   498

enum chip_flags {

   499

	HasHltClk	= (1 << 0),

   500

	HasLWake	= (1 << 1),

   501

};

   502

   503

#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   504

	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   505

#define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   506

   507

/* directly indexed by chip_t, above */

   508

static const struct {

   509

	const char *name;

   510

	u32 version; /* from RTL8139C/RTL8139D docs */

   511

	u32 flags;

   512

} rtl_chip_info[] = {

   513

	{ "RTL-8139",

   514

	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   515

	  HasHltClk,

   516

	},

   517

   518

	{ "RTL-8139 rev K",

   519

	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   520

	  HasHltClk,

   521

	},

   522

   523

	{ "RTL-8139A",

   524

	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   525

	  HasHltClk, /* XXX undocumented? */

   526

	},

   527

   528

	{ "RTL-8139A rev G",

   529

	  HW_REVID(1, 1, 1, 0, 0, 1, 0),