1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 */

    10

    11

#include <linux/module.h>

    12

#include <linux/moduleparam.h>

    13

#include <linux/pci.h>

    14

#include <linux/netdevice.h>

    15

#include <linux/etherdevice.h>

    16

#include <linux/delay.h>

    17

#include <linux/ethtool.h>

    18

#include <linux/mii.h>

    19

#include <linux/if_vlan.h>

    20

#include <linux/crc32.h>

    21

#include <linux/in.h>

    22

#include <linux/ip.h>

    23

#include <linux/tcp.h>

    24

#include <linux/interrupt.h>

    25

#include <linux/dma-mapping.h>

    26

#include <linux/pm_runtime.h>

    27

#include <linux/firmware.h>

    28

#include <linux/pci-aspm.h>

    29

#include <linux/prefetch.h>

    30

    31

#include <asm/io.h>

    32

#include <asm/irq.h>

    33

    34

#define RTL8169_VERSION "2.3LK-NAPI"

    35

#define MODULENAME "r8169"

    36

#define PFX MODULENAME ": "

    37

    38

#define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"

    39

#define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"

    40

#define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"

    41

#define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"

    42

#define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"

    43

#define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"

    44

#define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"

    45

#define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"

    46

#define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"

    47

#define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"

    48

#define FIRMWARE_8411_2		"rtl_nic/rtl8411-2.fw"

    49

#define FIRMWARE_8106E_1	"rtl_nic/rtl8106e-1.fw"

    50

#define FIRMWARE_8106E_2	"rtl_nic/rtl8106e-2.fw"

    51

#define FIRMWARE_8168G_2	"rtl_nic/rtl8168g-2.fw"

    52

#define FIRMWARE_8168G_3	"rtl_nic/rtl8168g-3.fw"

    53

    54

#ifdef RTL8169_DEBUG

    55

#define assert(expr) \

    56

	if (!(expr)) {					\

    57

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    58

		#expr,__FILE__,__func__,__LINE__);		\

    59

	}

    60

#define dprintk(fmt, args...) \

    61

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    62

#else

    63

#define assert(expr) do {} while (0)

    64

#define dprintk(fmt, args...)	do {} while (0)

    65

#endif /* RTL8169_DEBUG */

    66

    67

#define R8169_MSG_DEFAULT \

    68

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    69

    70

#define TX_SLOTS_AVAIL(tp) \

    71

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)

    72

    73

/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */

    74

#define TX_FRAGS_READY_FOR(tp,nr_frags) \

    75

	(TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))

    76

    77

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    78

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    79

static const int multicast_filter_limit = 32;

    80

    81

#define MAX_READ_REQUEST_SHIFT	12

    82

#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */

    83

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    84

    85

#define R8169_REGS_SIZE		256

    86

#define R8169_NAPI_WEIGHT	64

    87

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    88

#define NUM_RX_DESC	256U	/* Number of Rx descriptor registers */

    89

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    90

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    91

    92

#define RTL8169_TX_TIMEOUT	(6*HZ)

    93

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    94

    95

/* write/read MMIO register */

    96

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

    97

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

    98

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

    99

#define RTL_R8(reg)		readb (ioaddr + (reg))

   100

#define RTL_R16(reg)		readw (ioaddr + (reg))

   101

#define RTL_R32(reg)		readl (ioaddr + (reg))

   102

   103

enum mac_version {

   104

	RTL_GIGA_MAC_VER_01 = 0,

   105

	RTL_GIGA_MAC_VER_02,

   106

	RTL_GIGA_MAC_VER_03,

   107

	RTL_GIGA_MAC_VER_04,

   108

	RTL_GIGA_MAC_VER_05,

   109

	RTL_GIGA_MAC_VER_06,

   110

	RTL_GIGA_MAC_VER_07,

   111

	RTL_GIGA_MAC_VER_08,

   112

	RTL_GIGA_MAC_VER_09,

   113

	RTL_GIGA_MAC_VER_10,

   114

	RTL_GIGA_MAC_VER_11,

   115

	RTL_GIGA_MAC_VER_12,

   116

	RTL_GIGA_MAC_VER_13,

   117

	RTL_GIGA_MAC_VER_14,

   118

	RTL_GIGA_MAC_VER_15,

   119

	RTL_GIGA_MAC_VER_16,

   120

	RTL_GIGA_MAC_VER_17,

   121

	RTL_GIGA_MAC_VER_18,

   122

	RTL_GIGA_MAC_VER_19,

   123

	RTL_GIGA_MAC_VER_20,

   124

	RTL_GIGA_MAC_VER_21,

   125

	RTL_GIGA_MAC_VER_22,

   126

	RTL_GIGA_MAC_VER_23,

   127

	RTL_GIGA_MAC_VER_24,

   128

	RTL_GIGA_MAC_VER_25,

   129

	RTL_GIGA_MAC_VER_26,

   130

	RTL_GIGA_MAC_VER_27,

   131

	RTL_GIGA_MAC_VER_28,

   132

	RTL_GIGA_MAC_VER_29,

   133

	RTL_GIGA_MAC_VER_30,

   134

	RTL_GIGA_MAC_VER_31,

   135

	RTL_GIGA_MAC_VER_32,

   136

	RTL_GIGA_MAC_VER_33,

   137

	RTL_GIGA_MAC_VER_34,

   138

	RTL_GIGA_MAC_VER_35,

   139

	RTL_GIGA_MAC_VER_36,

   140

	RTL_GIGA_MAC_VER_37,

   141

	RTL_GIGA_MAC_VER_38,

   142

	RTL_GIGA_MAC_VER_39,

   143

	RTL_GIGA_MAC_VER_40,

   144

	RTL_GIGA_MAC_VER_41,

   145

	RTL_GIGA_MAC_VER_42,

   146

	RTL_GIGA_MAC_VER_43,

   147

	RTL_GIGA_MAC_VER_44,

   148

	RTL_GIGA_MAC_NONE   = 0xff,

   149

};

   150

   151

enum rtl_tx_desc_version {

   152

	RTL_TD_0	= 0,

   153

	RTL_TD_1	= 1,

   154

};

   155

   156

#define JUMBO_1K	ETH_DATA_LEN

   157

#define JUMBO_4K	(4*1024 - ETH_HLEN - 2)

   158

#define JUMBO_6K	(6*1024 - ETH_HLEN - 2)

   159

#define JUMBO_7K	(7*1024 - ETH_HLEN - 2)

   160

#define JUMBO_9K	(9*1024 - ETH_HLEN - 2)

   161

   162

#define _R(NAME,TD,FW,SZ,B) {	\

   163

	.name = NAME,		\

   164

	.txd_version = TD,	\

   165

	.fw_name = FW,		\

   166

	.jumbo_max = SZ,	\

   167

	.jumbo_tx_csum = B	\

   168

}

   169

   170

static const struct {

   171

	const char *name;

   172

	enum rtl_tx_desc_version txd_version;

   173

	const char *fw_name;

   174

	u16 jumbo_max;

   175

	bool jumbo_tx_csum;

   176

} rtl_chip_infos[] = {

   177

	/* PCI devices. */

   178

	[RTL_GIGA_MAC_VER_01] =

   179

		_R("RTL8169",		RTL_TD_0, NULL, JUMBO_7K, true),

   180

	[RTL_GIGA_MAC_VER_02] =

   181

		_R("RTL8169s",		RTL_TD_0, NULL, JUMBO_7K, true),

   182

	[RTL_GIGA_MAC_VER_03] =

   183

		_R("RTL8110s",		RTL_TD_0, NULL, JUMBO_7K, true),

   184

	[RTL_GIGA_MAC_VER_04] =

   185

		_R("RTL8169sb/8110sb",	RTL_TD_0, NULL, JUMBO_7K, true),

   186

	[RTL_GIGA_MAC_VER_05] =

   187

		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),

   188

	[RTL_GIGA_MAC_VER_06] =

   189

		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),

   190

	/* PCI-E devices. */

   191

	[RTL_GIGA_MAC_VER_07] =

   192

		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),

   193

	[RTL_GIGA_MAC_VER_08] =

   194

		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),

   195

	[RTL_GIGA_MAC_VER_09] =

   196

		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),

   197

	[RTL_GIGA_MAC_VER_10] =

   198

		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),

   199

	[RTL_GIGA_MAC_VER_11] =

   200

		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),

   201

	[RTL_GIGA_MAC_VER_12] =

   202

		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),

   203

	[RTL_GIGA_MAC_VER_13] =

   204

		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),

   205

	[RTL_GIGA_MAC_VER_14] =

   206

		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),

   207

	[RTL_GIGA_MAC_VER_15] =

   208

		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),

   209

	[RTL_GIGA_MAC_VER_16] =

   210

		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),

   211

	[RTL_GIGA_MAC_VER_17] =

   212

		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),

   213

	[RTL_GIGA_MAC_VER_18] =

   214

		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),

   215

	[RTL_GIGA_MAC_VER_19] =

   216

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   217

	[RTL_GIGA_MAC_VER_20] =

   218

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   219

	[RTL_GIGA_MAC_VER_21] =

   220

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   221

	[RTL_GIGA_MAC_VER_22] =

   222

		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),

   223

	[RTL_GIGA_MAC_VER_23] =

   224

		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),

   225

	[RTL_GIGA_MAC_VER_24] =

   226

		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),

   227

	[RTL_GIGA_MAC_VER_25] =

   228

		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_1,

   229

							JUMBO_9K, false),

   230

	[RTL_GIGA_MAC_VER_26] =

   231

		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_2,

   232

							JUMBO_9K, false),

   233

	[RTL_GIGA_MAC_VER_27] =

   234

		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),

   235

	[RTL_GIGA_MAC_VER_28] =

   236

		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),

   237

	[RTL_GIGA_MAC_VER_29] =

   238

		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,

   239

							JUMBO_1K, true),

   240

	[RTL_GIGA_MAC_VER_30] =

   241

		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,

   242

							JUMBO_1K, true),

   243

	[RTL_GIGA_MAC_VER_31] =

   244

		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),

   245

	[RTL_GIGA_MAC_VER_32] =

   246

		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_1,

   247

							JUMBO_9K, false),

   248

	[RTL_GIGA_MAC_VER_33] =

   249

		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_2,

   250

							JUMBO_9K, false),

   251

	[RTL_GIGA_MAC_VER_34] =

   252

		_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,

   253

							JUMBO_9K, false),

   254

	[RTL_GIGA_MAC_VER_35] =

   255

		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_1,

   256

							JUMBO_9K, false),

   257

	[RTL_GIGA_MAC_VER_36] =

   258

		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_2,

   259

							JUMBO_9K, false),

   260

	[RTL_GIGA_MAC_VER_37] =

   261

		_R("RTL8402",		RTL_TD_1, FIRMWARE_8402_1,

   262

							JUMBO_1K, true),

   263

	[RTL_GIGA_MAC_VER_38] =

   264

		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_1,

   265

							JUMBO_9K, false),

   266

	[RTL_GIGA_MAC_VER_39] =

   267

		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_1,

   268

							JUMBO_1K, true),

   269

	[RTL_GIGA_MAC_VER_40] =

   270

		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_2,

   271

							JUMBO_9K, false),

   272

	[RTL_GIGA_MAC_VER_41] =

   273

		_R("RTL8168g/8111g",	RTL_TD_1, NULL, JUMBO_9K, false),

   274

	[RTL_GIGA_MAC_VER_42] =

   275

		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_3,

   276

							JUMBO_9K, false),

   277

	[RTL_GIGA_MAC_VER_43] =

   278

		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_2,

   279

							JUMBO_1K, true),

   280

	[RTL_GIGA_MAC_VER_44] =

   281

		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_2,

   282

							JUMBO_9K, false),

   283

};

   284

#undef _R

   285

   286

enum cfg_version {

   287

	RTL_CFG_0 = 0x00,

   288

	RTL_CFG_1,

   289

	RTL_CFG_2

   290

};

   291

   292

static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {

   293

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   294

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   295

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   296

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   297

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   298

	{ PCI_VENDOR_ID_DLINK,			0x4300,

   299

		PCI_VENDOR_ID_DLINK, 0x4b10,		 0, 0, RTL_CFG_1 },

   300

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   301

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4302), 0, 0, RTL_CFG_0 },

   302

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   303

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   304

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   305

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   306

	{ 0x0001,				0x8168,

   307

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   308

	{0,},

   309

};

   310

   311

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   312

   313

static int rx_buf_sz = 16383;

   314

static int use_dac;

   315

static struct {

   316

	u32 msg_enable;

   317

} debug = { -1 };

   318

   319

enum rtl_registers {

   320

	MAC0		= 0,	/* Ethernet hardware address. */

   321

	MAC4		= 4,

   322

	MAR0		= 8,	/* Multicast filter. */

   323

	CounterAddrLow		= 0x10,

   324

	CounterAddrHigh		= 0x14,

   325

	TxDescStartAddrLow	= 0x20,

   326

	TxDescStartAddrHigh	= 0x24,

   327

	TxHDescStartAddrLow	= 0x28,

   328

	TxHDescStartAddrHigh	= 0x2c,

   329

	FLASH		= 0x30,

   330

	ERSR		= 0x36,

   331

	ChipCmd		= 0x37,

   332

	TxPoll		= 0x38,

   333

	IntrMask	= 0x3c,

   334

	IntrStatus	= 0x3e,

   335

   336

	TxConfig	= 0x40,

   337

#define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */

   338

#define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */

   339

   340

	RxConfig	= 0x44,

   341

#define	RX128_INT_EN			(1 << 15)	/* 8111c and later */

   342

#define	RX_MULTI_EN			(1 << 14)	/* 8111c only */

   343

#define	RXCFG_FIFO_SHIFT		13

   344

					/* No threshold before first PCI xfer */

   345

#define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)

   346

#define	RX_EARLY_OFF			(1 << 11)

   347

#define	RXCFG_DMA_SHIFT			8

   348

					/* Unlimited maximum PCI burst. */

   349

#define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)

   350

   351

	RxMissed	= 0x4c,

   352

	Cfg9346		= 0x50,

   353

	Config0		= 0x51,

   354

	Config1		= 0x52,

   355

	Config2		= 0x53,

   356

#define PME_SIGNAL			(1 << 5)	/* 8168c and later */

   357

   358

	Config3		= 0x54,

   359

	Config4		= 0x55,

   360

	Config5		= 0x56,

   361

	MultiIntr	= 0x5c,

   362

	PHYAR		= 0x60,

   363

	PHYstatus	= 0x6c,

   364

	RxMaxSize	= 0xda,

   365

	CPlusCmd	= 0xe0,

   366

	IntrMitigate	= 0xe2,

   367

	RxDescAddrLow	= 0xe4,

   368

	RxDescAddrHigh	= 0xe8,

   369

	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */

   370

   371

#define NoEarlyTx	0x3f	/* Max value : no early transmit. */

   372

   373

	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */

   374

   375

#define TxPacketMax	(8064 >> 7)

   376

#define EarlySize	0x27

   377

   378

	FuncEvent	= 0xf0,

   379

	FuncEventMask	= 0xf4,

   380

	FuncPresetState	= 0xf8,

   381

	FuncForceEvent	= 0xfc,

   382

};

   383

   384

enum rtl8110_registers {

   385

	TBICSR			= 0x64,

   386

	TBI_ANAR		= 0x68,

   387

	TBI_LPAR		= 0x6a,

   388

};

   389

   390

enum rtl8168_8101_registers {

   391

	CSIDR			= 0x64,

   392

	CSIAR			= 0x68,

   393

#define	CSIAR_FLAG			0x80000000

   394

#define	CSIAR_WRITE_CMD			0x80000000

   395

#define	CSIAR_BYTE_ENABLE		0x0f

   396

#define	CSIAR_BYTE_ENABLE_SHIFT		12

   397

#define	CSIAR_ADDR_MASK			0x0fff

   398

#define CSIAR_FUNC_CARD			0x00000000

   399

#define CSIAR_FUNC_SDIO			0x00010000

   400

#define CSIAR_FUNC_NIC			0x00020000

   401

#define CSIAR_FUNC_NIC2			0x00010000

   402

	PMCH			= 0x6f,

   403

	EPHYAR			= 0x80,

   404

#define	EPHYAR_FLAG			0x80000000

   405

#define	EPHYAR_WRITE_CMD		0x80000000

   406

#define	EPHYAR_REG_MASK			0x1f

   407

#define	EPHYAR_REG_SHIFT		16

   408

#define	EPHYAR_DATA_MASK		0xffff

   409

	DLLPR			= 0xd0,

   410

#define	PFM_EN				(1 << 6)

   411

	DBG_REG			= 0xd1,

   412

#define	FIX_NAK_1			(1 << 4)

   413

#define	FIX_NAK_2			(1 << 3)

   414

	TWSI			= 0xd2,

   415

	MCU			= 0xd3,

   416

#define	NOW_IS_OOB			(1 << 7)

   417

#define	TX_EMPTY			(1 << 5)

   418

#define	RX_EMPTY			(1 << 4)

   419

#define	RXTX_EMPTY			(TX_EMPTY | RX_EMPTY)

   420

#define	EN_NDP				(1 << 3)

   421

#define	EN_OOB_RESET			(1 << 2)

   422

#define	LINK_LIST_RDY			(1 << 1)

   423

	EFUSEAR			= 0xdc,

   424

#define	EFUSEAR_FLAG			0x80000000

   425

#define	EFUSEAR_WRITE_CMD		0x80000000

   426

#define	EFUSEAR_READ_CMD		0x00000000

   427

#define	EFUSEAR_REG_MASK		0x03ff

   428

#define	EFUSEAR_REG_SHIFT		8

   429

#define	EFUSEAR_DATA_MASK		0xff

   430

};

   431

   432

enum rtl8168_registers {

   433

	LED_FREQ		= 0x1a,

   434

	EEE_LED			= 0x1b,

   435

	ERIDR			= 0x70,

   436

	ERIAR			= 0x74,

   437

#define ERIAR_FLAG			0x80000000

   438

#define ERIAR_WRITE_CMD			0x80000000

   439

#define ERIAR_READ_CMD			0x00000000

   440

#define ERIAR_ADDR_BYTE_ALIGN		4

   441

#define ERIAR_TYPE_SHIFT		16

   442

#define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)

   443

#define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)

   444

#define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)

   445

#define ERIAR_MASK_SHIFT		12

   446

#define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)

   447

#define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)

   448

#define ERIAR_MASK_0101			(0x5 << ERIAR_MASK_SHIFT)

   449

#define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)

   450

	EPHY_RXER_NUM		= 0x7c,

   451

	OCPDR			= 0xb0,	/* OCP GPHY access */

   452

#define OCPDR_WRITE_CMD			0x80000000

   453

#define OCPDR_READ_CMD			0x00000000

   454

#define OCPDR_REG_MASK			0x7f

   455

#define OCPDR_GPHY_REG_SHIFT		16

   456

#define OCPDR_DATA_MASK			0xffff

   457

	OCPAR			= 0xb4,

   458

#define OCPAR_FLAG			0x80000000

   459

#define OCPAR_GPHY_WRITE_CMD		0x8000f060

   460

#define OCPAR_GPHY_READ_CMD		0x0000f060

   461

	GPHY_OCP		= 0xb8,

   462

	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */

   463

	MISC			= 0xf0,	/* 8168e only. */

   464

#define TXPLA_RST			(1 << 29)

   465

#define DISABLE_LAN_EN			(1 << 23) /* Enable GPIO pin */

   466

#define PWM_EN				(1 << 22)

   467

#define RXDV_GATED_EN			(1 << 19)

   468

#define EARLY_TALLY_EN			(1 << 16)

   469

};

   470

   471

enum rtl_register_content {

   472

	/* InterruptStatusBits */

   473

	SYSErr		= 0x8000,

   474

	PCSTimeout	= 0x4000,

   475

	SWInt		= 0x0100,

   476

	TxDescUnavail	= 0x0080,

   477

	RxFIFOOver	= 0x0040,

   478

	LinkChg		= 0x0020,

   479

	RxOverflow	= 0x0010,

   480

	TxErr		= 0x0008,

   481

	TxOK		= 0x0004,

   482

	RxErr		= 0x0002,

   483

	RxOK		= 0x0001,

   484

   485

	/* RxStatusDesc */

   486

	RxBOVF	= (1 << 24),

   487

	RxFOVF	= (1 << 23),

   488

	RxRWT	= (1 << 22),

   489

	RxRES	= (1 << 21),

   490

	RxRUNT	= (1 << 20),

   491

	RxCRC	= (1 << 19),

   492

   493

	/* ChipCmdBits */

   494

	StopReq		= 0x80,

   495

	CmdReset	= 0x10,

   496

	CmdRxEnb	= 0x08,

   497

	CmdTxEnb	= 0x04,

   498

	RxBufEmpty	= 0x01,

   499

   500

	/* TXPoll register p.5 */

   501

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   502

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   503

	FSWInt		= 0x01,		/* Forced software interrupt */

   504

   505

	/* Cfg9346Bits */

   506

	Cfg9346_Lock	= 0x00,

   507

	Cfg9346_Unlock	= 0xc0,

   508

   509

	/* rx_mode_bits */

   510

	AcceptErr	= 0x20,

   511

	AcceptRunt	= 0x10,

   512

	AcceptBroadcast	= 0x08,

   513

	AcceptMulticast	= 0x04,

   514

	AcceptMyPhys	= 0x02,

   515

	AcceptAllPhys	= 0x01,

   516

#define RX_CONFIG_ACCEPT_MASK		0x3f

   517

   518

	/* TxConfigBits */

   519

	TxInterFrameGapShift = 24,

   520

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   521

   522

	/* Config1 register p.24 */

   523

	LEDS1		= (1 << 7),

   524

	LEDS0		= (1 << 6),

   525

	Speed_down	= (1 << 4),

   526

	MEMMAP		= (1 << 3),

   527

	IOMAP		= (1 << 2),

   528

	VPD		= (1 << 1),

   529

	PMEnable	= (1 << 0),	/* Power Management Enable */