1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2012 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

#include "e1000-3.8-ethercat.h"

    30

    31

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    32

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    33

static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);

    34

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    35

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);

    36

static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,

    37

					  u16 *data, bool read, bool page_set);

    38

static u32 e1000_get_phy_addr_for_hv_page(u32 page);

    39

static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,

    40

                                          u16 *data, bool read);

    41

    42

/* Cable length tables */

    43

static const u16 e1000_m88_cable_length_table[] = {

    44

	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };

    45

#define M88E1000_CABLE_LENGTH_TABLE_SIZE \

    46

		ARRAY_SIZE(e1000_m88_cable_length_table)

    47

    48

static const u16 e1000_igp_2_cable_length_table[] = {

    49

	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,

    50

	6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,

    51

	26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,

    52

	44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,

    53

	66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,

    54

	87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,

    55

	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,

    56

	124};

    57

#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \

    58

		ARRAY_SIZE(e1000_igp_2_cable_length_table)

    59

    60

#define BM_PHY_REG_PAGE(offset) \

    61

	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))

    62

#define BM_PHY_REG_NUM(offset) \

    63

	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\

    64

	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\

    65

		~MAX_PHY_REG_ADDRESS)))

    66

    67

#define HV_INTC_FC_PAGE_START             768

    68

#define I82578_ADDR_REG                   29

    69

#define I82577_ADDR_REG                   16

    70

#define I82577_CFG_REG                    22

    71

#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)

    72

#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */

    73

#define I82577_CTRL_REG                   23

    74

    75

/* 82577 specific PHY registers */

    76

#define I82577_PHY_CTRL_2            18

    77

#define I82577_PHY_STATUS_2          26

    78

#define I82577_PHY_DIAG_STATUS       31

    79

    80

/* I82577 PHY Status 2 */

    81

#define I82577_PHY_STATUS2_REV_POLARITY   0x0400

    82

#define I82577_PHY_STATUS2_MDIX           0x0800

    83

#define I82577_PHY_STATUS2_SPEED_MASK     0x0300

    84

#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200

    85

    86

/* I82577 PHY Control 2 */

    87

#define I82577_PHY_CTRL2_MANUAL_MDIX      0x0200

    88

#define I82577_PHY_CTRL2_AUTO_MDI_MDIX    0x0400

    89

#define I82577_PHY_CTRL2_MDIX_CFG_MASK    0x0600

    90

    91

/* I82577 PHY Diagnostics Status */

    92

#define I82577_DSTATUS_CABLE_LENGTH       0x03FC

    93

#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2

    94

    95

/* BM PHY Copper Specific Control 1 */

    96

#define BM_CS_CTRL1                       16

    97

    98

#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)

    99

#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400

   100

#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004

   101

   102

/**

   103

 *  e1000e_check_reset_block_generic - Check if PHY reset is blocked

   104

 *  @hw: pointer to the HW structure

   105

 *

   106

 *  Read the PHY management control register and check whether a PHY reset

   107

 *  is blocked.  If a reset is not blocked return 0, otherwise

   108

 *  return E1000_BLK_PHY_RESET (12).

   109

 **/

   110

s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)

   111

{

   112

	u32 manc;

   113

   114

	manc = er32(MANC);

   115

   116

	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?

   117

	       E1000_BLK_PHY_RESET : 0;

   118

}

   119

   120

/**

   121

 *  e1000e_get_phy_id - Retrieve the PHY ID and revision

   122

 *  @hw: pointer to the HW structure

   123

 *

   124

 *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   125

 *  revision in the hardware structure.

   126

 **/

   127

s32 e1000e_get_phy_id(struct e1000_hw *hw)

   128

{

   129

	struct e1000_phy_info *phy = &hw->phy;

   130

	s32 ret_val = 0;

   131

	u16 phy_id;

   132

	u16 retry_count = 0;

   133

   134

	if (!phy->ops.read_reg)

   135

		return 0;

   136

   137

	while (retry_count < 2) {

   138

		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   139

		if (ret_val)

   140

			return ret_val;

   141

   142

		phy->id = (u32)(phy_id << 16);

   143

		udelay(20);

   144

		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   145

		if (ret_val)

   146

			return ret_val;

   147

   148

		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

   149

		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   150

   151

		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)

   152

			return 0;

   153

   154

		retry_count++;

   155

	}

   156

   157

	return 0;

   158

}

   159

   160

/**

   161

 *  e1000e_phy_reset_dsp - Reset PHY DSP

   162

 *  @hw: pointer to the HW structure

   163

 *

   164

 *  Reset the digital signal processor.

   165

 **/

   166

s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)

   167

{

   168

	s32 ret_val;

   169

   170

	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

   171

	if (ret_val)

   172

		return ret_val;

   173

   174

	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);

   175

}

   176

   177

/**

   178

 *  e1000e_read_phy_reg_mdic - Read MDI control register

   179

 *  @hw: pointer to the HW structure

   180

 *  @offset: register offset to be read

   181

 *  @data: pointer to the read data

   182

 *

   183

 *  Reads the MDI control register in the PHY at offset and stores the

   184

 *  information read to data.

   185

 **/

   186

s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)

   187

{

   188

	struct e1000_phy_info *phy = &hw->phy;

   189

	u32 i, mdic = 0;

   190

   191

	if (offset > MAX_PHY_REG_ADDRESS) {

   192

		e_dbg("PHY Address %d is out of range\n", offset);

   193

		return -E1000_ERR_PARAM;

   194

	}

   195

   196

	/* Set up Op-code, Phy Address, and register offset in the MDI

   197

	 * Control register.  The MAC will take care of interfacing with the

   198

	 * PHY to retrieve the desired data.

   199

	 */

   200

	mdic = ((offset << E1000_MDIC_REG_SHIFT) |

   201

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   202

		(E1000_MDIC_OP_READ));

   203

   204

	ew32(MDIC, mdic);

   205

   206

	/* Poll the ready bit to see if the MDI read completed

   207

	 * Increasing the time out as testing showed failures with

   208

	 * the lower time out

   209

	 */

   210

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   211

		udelay(50);

   212

		mdic = er32(MDIC);

   213

		if (mdic & E1000_MDIC_READY)

   214

			break;

   215

	}

   216

	if (!(mdic & E1000_MDIC_READY)) {

   217

		e_dbg("MDI Read did not complete\n");

   218

		return -E1000_ERR_PHY;

   219

	}

   220

	if (mdic & E1000_MDIC_ERROR) {

   221

		e_dbg("MDI Error\n");

   222

		return -E1000_ERR_PHY;

   223

	}

   224

	*data = (u16) mdic;

   225

   226

	/* Allow some time after each MDIC transaction to avoid

   227

	 * reading duplicate data in the next MDIC transaction.

   228

	 */

   229

	if (hw->mac.type == e1000_pch2lan)

   230

		udelay(100);

   231

   232

	return 0;

   233

}

   234

   235

/**

   236

 *  e1000e_write_phy_reg_mdic - Write MDI control register

   237

 *  @hw: pointer to the HW structure

   238

 *  @offset: register offset to write to

   239

 *  @data: data to write to register at offset

   240

 *

   241

 *  Writes data to MDI control register in the PHY at offset.

   242

 **/

   243

s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)

   244

{

   245

	struct e1000_phy_info *phy = &hw->phy;

   246

	u32 i, mdic = 0;

   247

   248

	if (offset > MAX_PHY_REG_ADDRESS) {

   249

		e_dbg("PHY Address %d is out of range\n", offset);

   250

		return -E1000_ERR_PARAM;

   251

	}

   252

   253

	/* Set up Op-code, Phy Address, and register offset in the MDI

   254

	 * Control register.  The MAC will take care of interfacing with the

   255

	 * PHY to retrieve the desired data.

   256

	 */

   257

	mdic = (((u32)data) |

   258

		(offset << E1000_MDIC_REG_SHIFT) |

   259

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   260

		(E1000_MDIC_OP_WRITE));

   261

   262

	ew32(MDIC, mdic);

   263

   264

	/* Poll the ready bit to see if the MDI read completed

   265

	 * Increasing the time out as testing showed failures with

   266

	 * the lower time out

   267

	 */

   268

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   269

		udelay(50);

   270

		mdic = er32(MDIC);

   271

		if (mdic & E1000_MDIC_READY)

   272

			break;

   273

	}

   274

	if (!(mdic & E1000_MDIC_READY)) {

   275

		e_dbg("MDI Write did not complete\n");

   276

		return -E1000_ERR_PHY;

   277

	}

   278

	if (mdic & E1000_MDIC_ERROR) {

   279

		e_dbg("MDI Error\n");

   280

		return -E1000_ERR_PHY;

   281

	}

   282

   283

	/* Allow some time after each MDIC transaction to avoid

   284

	 * reading duplicate data in the next MDIC transaction.

   285

	 */

   286

	if (hw->mac.type == e1000_pch2lan)

   287

		udelay(100);

   288

   289

	return 0;

   290

}

   291

   292

/**

   293

 *  e1000e_read_phy_reg_m88 - Read m88 PHY register

   294

 *  @hw: pointer to the HW structure

   295

 *  @offset: register offset to be read

   296

 *  @data: pointer to the read data

   297

 *

   298

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   299

 *  and storing the retrieved information in data.  Release any acquired

   300

 *  semaphores before exiting.

   301

 **/

   302

s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)

   303

{

   304

	s32 ret_val;

   305

   306

	ret_val = hw->phy.ops.acquire(hw);

   307

	if (ret_val)

   308

		return ret_val;

   309

   310

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   311

					   data);

   312

   313

	hw->phy.ops.release(hw);

   314

   315

	return ret_val;

   316

}

   317

   318

/**

   319

 *  e1000e_write_phy_reg_m88 - Write m88 PHY register

   320

 *  @hw: pointer to the HW structure

   321

 *  @offset: register offset to write to

   322

 *  @data: data to write at register offset

   323

 *

   324

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   325

 *  at the offset.  Release any acquired semaphores before exiting.

   326

 **/

   327

s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)

   328

{

   329

	s32 ret_val;

   330

   331

	ret_val = hw->phy.ops.acquire(hw);

   332

	if (ret_val)

   333

		return ret_val;

   334

   335

	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   336

					    data);

   337

   338

	hw->phy.ops.release(hw);

   339

   340

	return ret_val;

   341

}

   342

   343

/**

   344

 *  e1000_set_page_igp - Set page as on IGP-like PHY(s)

   345

 *  @hw: pointer to the HW structure

   346

 *  @page: page to set (shifted left when necessary)

   347

 *

   348

 *  Sets PHY page required for PHY register access.  Assumes semaphore is

   349

 *  already acquired.  Note, this function sets phy.addr to 1 so the caller

   350

 *  must set it appropriately (if necessary) after this function returns.

   351

 **/

   352

s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)

   353

{

   354

	e_dbg("Setting page 0x%x\n", page);

   355

   356

	hw->phy.addr = 1;

   357

   358

	return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);

   359

}

   360

   361

/**

   362

 *  __e1000e_read_phy_reg_igp - Read igp PHY register

   363

 *  @hw: pointer to the HW structure

   364

 *  @offset: register offset to be read

   365

 *  @data: pointer to the read data

   366

 *  @locked: semaphore has already been acquired or not

   367

 *

   368

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   369

 *  and stores the retrieved information in data.  Release any acquired

   370

 *  semaphores before exiting.

   371

 **/

   372

static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,

   373

                                    bool locked)

   374

{

   375

	s32 ret_val = 0;

   376

   377

	if (!locked) {

   378

		if (!hw->phy.ops.acquire)

   379

			return 0;

   380

   381

		ret_val = hw->phy.ops.acquire(hw);

   382

		if (ret_val)

   383

			return ret_val;

   384

	}

   385

   386

	if (offset > MAX_PHY_MULTI_PAGE_REG)

   387

		ret_val = e1000e_write_phy_reg_mdic(hw,

   388

						    IGP01E1000_PHY_PAGE_SELECT,

   389

						    (u16)offset);

   390

	if (!ret_val)

   391

		ret_val = e1000e_read_phy_reg_mdic(hw,

   392

						   MAX_PHY_REG_ADDRESS & offset,

   393

						   data);

   394

	if (!locked)

   395

		hw->phy.ops.release(hw);

   396

   397

	return ret_val;

   398

}

   399

   400

/**

   401

 *  e1000e_read_phy_reg_igp - Read igp PHY register

   402

 *  @hw: pointer to the HW structure

   403

 *  @offset: register offset to be read

   404

 *  @data: pointer to the read data

   405

 *

   406

 *  Acquires semaphore then reads the PHY register at offset and stores the

   407

 *  retrieved information in data.

   408

 *  Release the acquired semaphore before exiting.

   409

 **/

   410

s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)

   411

{

   412

	return __e1000e_read_phy_reg_igp(hw, offset, data, false);

   413

}

   414

   415

/**

   416

 *  e1000e_read_phy_reg_igp_locked - Read igp PHY register

   417

 *  @hw: pointer to the HW structure

   418

 *  @offset: register offset to be read

   419

 *  @data: pointer to the read data

   420

 *

   421

 *  Reads the PHY register at offset and stores the retrieved information

   422

 *  in data.  Assumes semaphore already acquired.

   423

 **/

   424

s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)

   425

{

   426

	return __e1000e_read_phy_reg_igp(hw, offset, data, true);

   427

}

   428

   429

/**

   430

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   431

 *  @hw: pointer to the HW structure

   432

 *  @offset: register offset to write to

   433

 *  @data: data to write at register offset

   434

 *  @locked: semaphore has already been acquired or not

   435

 *

   436

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   437

 *  at the offset.  Release any acquired semaphores before exiting.

   438

 **/

   439

static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,

   440

                                     bool locked)

   441

{

   442

	s32 ret_val = 0;

   443

   444

	if (!locked) {

   445

		if (!hw->phy.ops.acquire)

   446

			return 0;

   447

   448

		ret_val = hw->phy.ops.acquire(hw);

   449

		if (ret_val)

   450

			return ret_val;

   451

	}

   452

   453

	if (offset > MAX_PHY_MULTI_PAGE_REG)

   454

		ret_val = e1000e_write_phy_reg_mdic(hw,

   455

						    IGP01E1000_PHY_PAGE_SELECT,

   456

						    (u16)offset);

   457

	if (!ret_val)

   458

		ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &

   459

							offset,

   460

						    data);

   461

	if (!locked)

   462

		hw->phy.ops.release(hw);

   463

   464

	return ret_val;

   465

}

   466

   467

/**

   468

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   469

 *  @hw: pointer to the HW structure

   470

 *  @offset: register offset to write to

   471

 *  @data: data to write at register offset

   472

 *

   473

 *  Acquires semaphore then writes the data to PHY register

   474

 *  at the offset.  Release any acquired semaphores before exiting.

   475

 **/

   476

s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)

   477

{

   478

	return __e1000e_write_phy_reg_igp(hw, offset, data, false);

   479

}

   480

   481

/**

   482

 *  e1000e_write_phy_reg_igp_locked - Write igp PHY register

   483

 *  @hw: pointer to the HW structure

   484

 *  @offset: register offset to write to

   485

 *  @data: data to write at register offset

   486

 *

   487

 *  Writes the data to PHY register at the offset.

   488

 *  Assumes semaphore already acquired.

   489

 **/

   490

s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)

   491

{

   492

	return __e1000e_write_phy_reg_igp(hw, offset, data, true);

   493

}

   494

   495

/**

   496

 *  __e1000_read_kmrn_reg - Read kumeran register

   497

 *  @hw: pointer to the HW structure

   498

 *  @offset: register offset to be read

   499

 *  @data: pointer to the read data

   500

 *  @locked: semaphore has already been acquired or not

   501

 *

   502

 *  Acquires semaphore, if necessary.  Then reads the PHY register at offset

   503

 *  using the kumeran interface.  The information retrieved is stored in data.

   504

 *  Release any acquired semaphores before exiting.

   505

 **/

   506

static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,

   507

                                 bool locked)

   508

{

   509

	u32 kmrnctrlsta;

   510

   511

	if (!locked) {

   512

		s32 ret_val = 0;

   513

   514

		if (!hw->phy.ops.acquire)

   515

			return 0;

   516

   517

		ret_val = hw->phy.ops.acquire(hw);

   518

		if (ret_val)

   519

			return ret_val;

   520

	}

   521

   522

	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &

   523

		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;

   524

	ew32(KMRNCTRLSTA, kmrnctrlsta);

   525

	e1e_flush();

   526

   527

	udelay(2);

   528

   529

	kmrnctrlsta = er32(KMRNCTRLSTA);

   530