1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2009 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

/*

    30

 * 82562G 10/100 Network Connection

    31

 * 82562G-2 10/100 Network Connection

    32

 * 82562GT 10/100 Network Connection

    33

 * 82562GT-2 10/100 Network Connection

    34

 * 82562V 10/100 Network Connection

    35

 * 82562V-2 10/100 Network Connection

    36

 * 82566DC-2 Gigabit Network Connection

    37

 * 82566DC Gigabit Network Connection

    38

 * 82566DM-2 Gigabit Network Connection

    39

 * 82566DM Gigabit Network Connection

    40

 * 82566MC Gigabit Network Connection

    41

 * 82566MM Gigabit Network Connection

    42

 * 82567LM Gigabit Network Connection

    43

 * 82567LF Gigabit Network Connection

    44

 * 82567V Gigabit Network Connection

    45

 * 82567LM-2 Gigabit Network Connection

    46

 * 82567LF-2 Gigabit Network Connection

    47

 * 82567V-2 Gigabit Network Connection

    48

 * 82567LF-3 Gigabit Network Connection

    49

 * 82567LM-3 Gigabit Network Connection

    50

 * 82567LM-4 Gigabit Network Connection

    51

 * 82577LM Gigabit Network Connection

    52

 * 82577LC Gigabit Network Connection

    53

 * 82578DM Gigabit Network Connection

    54

 * 82578DC Gigabit Network Connection

    55

 */

    56

    57

#include "e1000.h"

    58

    59

#define ICH_FLASH_GFPREG		0x0000

    60

#define ICH_FLASH_HSFSTS		0x0004

    61

#define ICH_FLASH_HSFCTL		0x0006

    62

#define ICH_FLASH_FADDR			0x0008

    63

#define ICH_FLASH_FDATA0		0x0010

    64

#define ICH_FLASH_PR0			0x0074

    65

    66

#define ICH_FLASH_READ_COMMAND_TIMEOUT	500

    67

#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500

    68

#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000

    69

#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

    70

#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

    71

    72

#define ICH_CYCLE_READ			0

    73

#define ICH_CYCLE_WRITE			2

    74

#define ICH_CYCLE_ERASE			3

    75

    76

#define FLASH_GFPREG_BASE_MASK		0x1FFF

    77

#define FLASH_SECTOR_ADDR_SHIFT		12

    78

    79

#define ICH_FLASH_SEG_SIZE_256		256

    80

#define ICH_FLASH_SEG_SIZE_4K		4096

    81

#define ICH_FLASH_SEG_SIZE_8K		8192

    82

#define ICH_FLASH_SEG_SIZE_64K		65536

    83

    84

    85

#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */

    86

/* FW established a valid mode */

    87

#define E1000_ICH_FWSM_FW_VALID		0x00008000

    88

    89

#define E1000_ICH_MNG_IAMT_MODE		0x2

    90

    91

#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \

    92

				 (ID_LED_DEF1_OFF2 <<  8) | \

    93

				 (ID_LED_DEF1_ON2  <<  4) | \

    94

				 (ID_LED_DEF1_DEF2))

    95

    96

#define E1000_ICH_NVM_SIG_WORD		0x13

    97

#define E1000_ICH_NVM_SIG_MASK		0xC000

    98

#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0

    99

#define E1000_ICH_NVM_SIG_VALUE         0x80

   100

   101

#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

   102

   103

#define E1000_FEXTNVM_SW_CONFIG		1

   104

#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

   105

   106

#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL

   107

   108

#define E1000_ICH_RAR_ENTRIES		7

   109

   110

#define PHY_PAGE_SHIFT 5

   111

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

   112

			   ((reg) & MAX_PHY_REG_ADDRESS))

   113

#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */

   114

#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */

   115

   116

#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002

   117

#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

   118

#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200

   119

   120

#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */

   121

   122

#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */

   123

   124

/* SMBus Address Phy Register */

   125

#define HV_SMB_ADDR            PHY_REG(768, 26)

   126

#define HV_SMB_ADDR_PEC_EN     0x0200

   127

#define HV_SMB_ADDR_VALID      0x0080

   128

   129

/* Strapping Option Register - RO */

   130

#define E1000_STRAP                     0x0000C

   131

#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

   132

#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

   133

   134

/* OEM Bits Phy Register */

   135

#define HV_OEM_BITS            PHY_REG(768, 25)

   136

#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */

   137

#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */

   138

#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */

   139

   140

#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */

   141

#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */

   142

   143

/* KMRN Mode Control */

   144

#define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)

   145

#define HV_KMRN_MDIO_SLOW      0x0400

   146

   147

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

   148

/* Offset 04h HSFSTS */

   149

union ich8_hws_flash_status {

   150

	struct ich8_hsfsts {

   151

		u16 flcdone    :1; /* bit 0 Flash Cycle Done */

   152

		u16 flcerr     :1; /* bit 1 Flash Cycle Error */

   153

		u16 dael       :1; /* bit 2 Direct Access error Log */

   154

		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */

   155

		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */

   156

		u16 reserved1  :2; /* bit 13:6 Reserved */

   157

		u16 reserved2  :6; /* bit 13:6 Reserved */

   158

		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */

   159

		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */

   160

	} hsf_status;

   161

	u16 regval;

   162

};

   163

   164

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

   165

/* Offset 06h FLCTL */

   166

union ich8_hws_flash_ctrl {

   167

	struct ich8_hsflctl {

   168

		u16 flcgo      :1;   /* 0 Flash Cycle Go */

   169

		u16 flcycle    :2;   /* 2:1 Flash Cycle */

   170

		u16 reserved   :5;   /* 7:3 Reserved  */

   171

		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */

   172

		u16 flockdn    :6;   /* 15:10 Reserved */

   173

	} hsf_ctrl;

   174

	u16 regval;

   175

};

   176

   177

/* ICH Flash Region Access Permissions */

   178

union ich8_hws_flash_regacc {

   179

	struct ich8_flracc {

   180

		u32 grra      :8; /* 0:7 GbE region Read Access */

   181

		u32 grwa      :8; /* 8:15 GbE region Write Access */

   182

		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */

   183

		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */

   184

	} hsf_flregacc;

   185

	u16 regval;

   186

};

   187

   188

/* ICH Flash Protected Region */

   189

union ich8_flash_protected_range {

   190

	struct ich8_pr {

   191

		u32 base:13;     /* 0:12 Protected Range Base */

   192

		u32 reserved1:2; /* 13:14 Reserved */

   193

		u32 rpe:1;       /* 15 Read Protection Enable */

   194

		u32 limit:13;    /* 16:28 Protected Range Limit */

   195

		u32 reserved2:2; /* 29:30 Reserved */

   196

		u32 wpe:1;       /* 31 Write Protection Enable */

   197

	} range;

   198

	u32 regval;

   199

};

   200

   201

static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);

   202

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   203

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   204

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   205

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   206

						u32 offset, u8 byte);

   207

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   208

					 u8 *data);

   209

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   210

					 u16 *data);

   211

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   212

					 u8 size, u16 *data);

   213

static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

   214

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   215

static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);

   216

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   217

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   218

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   219

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   220

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   221

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   222

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   223

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   224

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   225

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   226

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   227

static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   228

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   229

   230

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   231

{

   232

	return readw(hw->flash_address + reg);

   233

}

   234

   235

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   236

{

   237

	return readl(hw->flash_address + reg);

   238

}

   239

   240

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   241

{

   242

	writew(val, hw->flash_address + reg);

   243

}

   244

   245

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   246

{

   247

	writel(val, hw->flash_address + reg);

   248

}

   249

   250

#define er16flash(reg)		__er16flash(hw, (reg))

   251

#define er32flash(reg)		__er32flash(hw, (reg))

   252

#define ew16flash(reg,val)	__ew16flash(hw, (reg), (val))

   253

#define ew32flash(reg,val)	__ew32flash(hw, (reg), (val))

   254

   255

/**

   256

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   257

 *  @hw: pointer to the HW structure

   258

 *

   259

 *  Initialize family-specific PHY parameters and function pointers.

   260

 **/

   261

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   262

{

   263

	struct e1000_phy_info *phy = &hw->phy;

   264

	u32 ctrl;

   265

	s32 ret_val = 0;

   266

   267

	phy->addr                     = 1;

   268

	phy->reset_delay_us           = 100;

   269

   270

	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   271

	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   272

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   273

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   274

	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   275

	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   276

	phy->ops.power_up             = e1000_power_up_phy_copper;

   277

	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   278

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   279

   280

	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {

   281

		/*

   282

		 * The MAC-PHY interconnect may still be in SMBus mode

   283

		 * after Sx->S0.  Toggle the LANPHYPC Value bit to force

   284

		 * the interconnect to PCIe mode, but only if there is no

   285

		 * firmware present otherwise firmware will have done it.

   286

		 */

   287

		ctrl = er32(CTRL);

   288

		ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;

   289

		ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;

   290

		ew32(CTRL, ctrl);

   291

		udelay(10);

   292

		ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   293

		ew32(CTRL, ctrl);

   294

		msleep(50);

   295

	}

   296

   297

	/*

   298

	 * Reset the PHY before any acccess to it.  Doing so, ensures that

   299

	 * the PHY is in a known good state before we read/write PHY registers.

   300

	 * The generic reset is sufficient here, because we haven't determined

   301

	 * the PHY type yet.

   302

	 */

   303

	ret_val = e1000e_phy_hw_reset_generic(hw);

   304

	if (ret_val)

   305

		goto out;

   306

   307

	phy->id = e1000_phy_unknown;

   308

	ret_val = e1000e_get_phy_id(hw);

   309

	if (ret_val)

   310

		goto out;

   311

	if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {

   312

		/*

   313

		 * In case the PHY needs to be in mdio slow mode (eg. 82577),

   314

		 * set slow mode and try to get the PHY id again.

   315

		 */

   316

		ret_val = e1000_set_mdio_slow_mode_hv(hw);

   317

		if (ret_val)

   318

			goto out;

   319

		ret_val = e1000e_get_phy_id(hw);

   320

		if (ret_val)

   321

			goto out;

   322

	}

   323

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   324

   325

	switch (phy->type) {

   326

	case e1000_phy_82577:

   327

		phy->ops.check_polarity = e1000_check_polarity_82577;

   328

		phy->ops.force_speed_duplex =

   329

			e1000_phy_force_speed_duplex_82577;

   330

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   331

		phy->ops.get_info = e1000_get_phy_info_82577;

   332

		phy->ops.commit = e1000e_phy_sw_reset;

   333

		break;

   334

	case e1000_phy_82578:

   335

		phy->ops.check_polarity = e1000_check_polarity_m88;

   336

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   337

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   338

		phy->ops.get_info = e1000e_get_phy_info_m88;

   339

		break;

   340

	default:

   341

		ret_val = -E1000_ERR_PHY;

   342

		break;

   343

	}

   344

   345

out:

   346

	return ret_val;

   347

}

   348

   349

/**

   350

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   351

 *  @hw: pointer to the HW structure

   352

 *

   353

 *  Initialize family-specific PHY parameters and function pointers.

   354

 **/

   355

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   356

{

   357

	struct e1000_phy_info *phy = &hw->phy;

   358

	s32 ret_val;

   359

	u16 i = 0;

   360

   361

	phy->addr			= 1;

   362

	phy->reset_delay_us		= 100;

   363

   364

	phy->ops.power_up               = e1000_power_up_phy_copper;

   365

	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

   366

   367

	/*

   368

	 * We may need to do this twice - once for IGP and if that fails,

   369

	 * we'll set BM func pointers and try again

   370

	 */

   371

	ret_val = e1000e_determine_phy_address(hw);

   372

	if (ret_val) {

   373

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   374

		phy->ops.read_reg  = e1000e_read_phy_reg_bm;

   375

		ret_val = e1000e_determine_phy_address(hw);

   376

		if (ret_val) {

   377

			e_dbg("Cannot determine PHY addr. Erroring out\n");

   378

			return ret_val;

   379

		}

   380

	}

   381

   382

	phy->id = 0;

   383

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   384

	       (i++ < 100)) {

   385

		msleep(1);

   386

		ret_val = e1000e_get_phy_id(hw);

   387

		if (ret_val)

   388

			return ret_val;

   389

	}

   390

   391

	/* Verify phy id */

   392

	switch (phy->id) {

   393

	case IGP03E1000_E_PHY_ID:

   394

		phy->type = e1000_phy_igp_3;

   395

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   396

		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   397

		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   398

		phy->ops.get_info = e1000e_get_phy_info_igp;

   399

		phy->ops.check_polarity = e1000_check_polarity_igp;

   400

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   401

		break;

   402

	case IFE_E_PHY_ID:

   403

	case IFE_PLUS_E_PHY_ID:

   404

	case IFE_C_E_PHY_ID:

   405

		phy->type = e1000_phy_ife;

   406

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   407

		phy->ops.get_info = e1000_get_phy_info_ife;

   408

		phy->ops.check_polarity = e1000_check_polarity_ife;

   409

		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   410

		break;

   411

	case BME1000_E_PHY_ID:

   412

		phy->type = e1000_phy_bm;

   413

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   414

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   415

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   416

		phy->ops.commit = e1000e_phy_sw_reset;

   417

		phy->ops.get_info = e1000e_get_phy_info_m88;

   418

		phy->ops.check_polarity = e1000_check_polarity_m88;

   419

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   420

		break;

   421

	default:

   422

		return -E1000_ERR_PHY;

   423

		break;

   424

	}

   425

   426

	return 0;

   427

}

   428

   429

/**

   430

 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   431

 *  @hw: pointer to the HW structure

   432

 *

   433

 *  Initialize family-specific NVM parameters and function

   434

 *  pointers.

   435

 **/

   436

static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   437

{

   438

	struct e1000_nvm_info *nvm = &hw->nvm;

   439

	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   440

	u32 gfpreg, sector_base_addr, sector_end_addr;

   441

	u16 i;

   442

   443

	/* Can't read flash registers if the register set isn't mapped. */

   444

	if (!hw->flash_address) {

   445

		e_dbg("ERROR: Flash registers not mapped\n");

   446

		return -E1000_ERR_CONFIG;

   447

	}

   448

   449

	nvm->type = e1000_nvm_flash_sw;

   450

   451

	gfpreg = er32flash(ICH_FLASH_GFPREG);

   452

   453

	/*

   454

	 * sector_X_addr is a "sector"-aligned address (4096 bytes)

   455

	 * Add 1 to sector_end_addr since this sector is included in

   456

	 * the overall size.

   457

	 */

   458

	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   459

	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   460

   461

	/* flash_base_addr is byte-aligned */

   462

	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   463

   464

	/*

   465

	 * find total size of the NVM, then cut in half since the total

   466

	 * size represents two separate NVM banks.

   467

	 */

   468

	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)

   469

				<< FLASH_SECTOR_ADDR_SHIFT;

   470

	nvm->flash_bank_size /= 2;

   471

	/* Adjust to word count */

   472

	nvm->flash_bank_size /= sizeof(u16);

   473

   474

	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;

   475

   476

	/* Clear shadow ram */

   477

	for (i = 0; i < nvm->word_size; i++) {

   478

		dev_spec->shadow_ram[i].modified = false;

   479

		dev_spec->shadow_ram[i].value    = 0xFFFF;

   480

	}

   481

   482

	return 0;

   483

}

   484

   485

/**

   486

 *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers

   487

 *  @hw: pointer to the HW structure

   488

 *

   489

 *  Initialize family-specific MAC parameters and function

   490

 *  pointers.

   491

 **/

   492

static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)

   493

{

   494

	struct e1000_hw *hw = &adapter->hw;

   495

	struct e1000_mac_info *mac = &hw->mac;

   496

   497

	/* Set media type function pointer */

   498

	hw->phy.media_type = e1000_media_type_copper;

   499

   500

	/* Set mta register count */

   501

	mac->mta_reg_count = 32;

   502

	/* Set rar entry count */

   503

	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;

   504

	if (mac->type == e1000_ich8lan)

   505

		mac->rar_entry_count--;

   506

	/* FWSM register */

   507

	mac->has_fwsm = true;

   508

	/* ARC subsystem not supported */

   509

	mac->arc_subsystem_valid = false;

   510

	/* Adaptive IFS supported */

   511

	mac->adaptive_ifs = true;

   512

   513

	/* LED operations */

   514

	switch (mac->type) {

   515

	case e1000_ich8lan:

   516

	case e1000_ich9lan:

   517

	case e1000_ich10lan:

   518

		/* ID LED init */

   519

		mac->ops.id_led_init = e1000e_id_led_init;

   520

		/* setup LED */

   521

		mac->ops.setup_led = e1000e_setup_led_generic;

   522

		/* cleanup LED */

   523

		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;

   524

		/* turn on/off LED */

   525

		mac->ops.led_on = e1000_led_on_ich8lan;

   526

		mac->ops.led_off = e1000_led_off_ich8lan;

   527

		break;

   528

	case e1000_pchlan:

   529

		/* ID LED init */

   530