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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2013 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

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  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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*******************************************************************************/

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#ifndef _E1000E_80003ES2LAN_H_

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#define _E1000E_80003ES2LAN_H_

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#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	0x00

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#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	0x02

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#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	0x10

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#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	0x1F

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#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008

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#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800

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#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	0x0010

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#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004

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#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000

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#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		0x2000

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#define E1000_KMRNCTRLSTA_OPMODE_MASK		0x000C

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#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	0x0004

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#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00	/* Gig Carry Extend Padding */

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#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	0x00010000

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#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	0x8

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#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	0x9

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/* GG82563 PHY Specific Status Register (Page 0, Register 16 */

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#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	0x0002	/* 1=Reversal Dis */

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#define GG82563_PSCR_CROSSOVER_MODE_MASK	0x0060

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#define GG82563_PSCR_CROSSOVER_MODE_MDI		0x0000	/* 00=Manual MDI */

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#define GG82563_PSCR_CROSSOVER_MODE_MDIX	0x0020	/* 01=Manual MDIX */

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#define GG82563_PSCR_CROSSOVER_MODE_AUTO	0x0060	/* 11=Auto crossover */

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/* PHY Specific Control Register 2 (Page 0, Register 26) */

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#define GG82563_PSCR2_REVERSE_AUTO_NEG		0x2000	/* 1=Reverse Auto-Neg */

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/* MAC Specific Control Register (Page 2, Register 21) */

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/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

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#define GG82563_MSCR_TX_CLK_MASK		0x0007

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#define GG82563_MSCR_TX_CLK_10MBPS_2_5		0x0004

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#define GG82563_MSCR_TX_CLK_100MBPS_25		0x0005

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#define GG82563_MSCR_TX_CLK_1000MBPS_25		0x0007

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#define GG82563_MSCR_ASSERT_CRS_ON_TX		0x0010	/* 1=Assert */

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/* DSP Distance Register (Page 5, Register 26)

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 * 0 = <50M

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 * 1 = 50-80M

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 * 2 = 80-100M

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 * 3 = 110-140M

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 * 4 = >140M

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 */

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#define GG82563_DSPD_CABLE_LENGTH		0x0007

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/* Kumeran Mode Control Register (Page 193, Register 16) */

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#define GG82563_KMCR_PASS_FALSE_CARRIER		0x0800

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/* Max number of times Kumeran read/write should be validated */

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#define GG82563_MAX_KMRN_RETRY			0x5

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/* Power Management Control Register (Page 193, Register 20) */

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/* 1=Enable SERDES Electrical Idle */

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#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	0x0001

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/* In-Band Control Register (Page 194, Register 18) */

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#define GG82563_ICR_DIS_PADDING			0x0010	/* Disable Padding */

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#endif