1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2006 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

 */

    28

    29

/* e1000_hw.c

    30

 * Shared functions for accessing and configuring the MAC

    31

 */

    32

    33

#include "e1000-3.10-ethercat.h"

    34

    35

static s32 e1000_check_downshift(struct e1000_hw *hw);

    36

static s32 e1000_check_polarity(struct e1000_hw *hw,

    37

				e1000_rev_polarity *polarity);

    38

static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39

static void e1000_clear_vfta(struct e1000_hw *hw);

    40

static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41

					      bool link_up);

    42

static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43

static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44

static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45

static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46

				  u16 *max_length);

    47

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48

static s32 e1000_id_led_init(struct e1000_hw *hw);

    49

static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50

static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51

				  struct e1000_phy_info *phy_info);

    52

static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53

				  struct e1000_phy_info *phy_info);

    54

static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56

static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57

static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58

static void e1000_phy_init_script(struct e1000_hw *hw);

    59

static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60

static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61

static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63

static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64

static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65

static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66

static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67

static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68

static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69

static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70

				  u16 words, u16 *data);

    71

static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72

					u16 words, u16 *data);

    73

static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74

static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75

static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76

static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77

static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78

				  u16 phy_data);

    79

static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80

				 u16 *phy_data);

    81

static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82

static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83

static void e1000_release_eeprom(struct e1000_hw *hw);

    84

static void e1000_standby_eeprom(struct e1000_hw *hw);

    85

static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86

static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87

static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88

static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89

				u16 *data);

    90

static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91

				 u16 *data);

    92

    93

/* IGP cable length table */

    94

static const

    95

u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96

	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97

	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98

	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99

	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100

	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101

	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102

	    100,

   103

	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104

	    110, 110,

   105

	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106

	    120, 120

   107

};

   108

   109

static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110

static DEFINE_SPINLOCK(e1000_phy_lock);

   111

   112

/**

   113

 * e1000_set_phy_type - Set the phy type member in the hw struct.

   114

 * @hw: Struct containing variables accessed by shared code

   115

 */

   116

static s32 e1000_set_phy_type(struct e1000_hw *hw)

   117

{

   118

	e_dbg("e1000_set_phy_type");

   119

   120

	if (hw->mac_type == e1000_undefined)

   121

		return -E1000_ERR_PHY_TYPE;

   122

   123

	switch (hw->phy_id) {

   124

	case M88E1000_E_PHY_ID:

   125

	case M88E1000_I_PHY_ID:

   126

	case M88E1011_I_PHY_ID:

   127

	case M88E1111_I_PHY_ID:

   128

	case M88E1118_E_PHY_ID:

   129

		hw->phy_type = e1000_phy_m88;

   130

		break;

   131

	case IGP01E1000_I_PHY_ID:

   132

		if (hw->mac_type == e1000_82541 ||

   133

		    hw->mac_type == e1000_82541_rev_2 ||

   134

		    hw->mac_type == e1000_82547 ||

   135

		    hw->mac_type == e1000_82547_rev_2)

   136

			hw->phy_type = e1000_phy_igp;

   137

		break;

   138

	case RTL8211B_PHY_ID:

   139

		hw->phy_type = e1000_phy_8211;

   140

		break;

   141

	case RTL8201N_PHY_ID:

   142

		hw->phy_type = e1000_phy_8201;

   143

		break;

   144

	default:

   145

		/* Should never have loaded on this device */

   146

		hw->phy_type = e1000_phy_undefined;

   147

		return -E1000_ERR_PHY_TYPE;

   148

	}

   149

   150

	return E1000_SUCCESS;

   151

}

   152

   153

/**

   154

 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   155

 * @hw: Struct containing variables accessed by shared code

   156

 */

   157

static void e1000_phy_init_script(struct e1000_hw *hw)

   158

{

   159

	u32 ret_val __attribute__ ((unused));

   160

	u16 phy_saved_data;

   161

   162

	e_dbg("e1000_phy_init_script");

   163

   164

	if (hw->phy_init_script) {

   165

		msleep(20);

   166

   167

		/* Save off the current value of register 0x2F5B to be restored

   168

		 * at the end of this routine.

   169

		 */

   170

		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   171

   172

		/* Disabled the PHY transmitter */

   173

		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   174

		msleep(20);

   175

   176

		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   177

		msleep(5);

   178

   179

		switch (hw->mac_type) {

   180

		case e1000_82541:

   181

		case e1000_82547:

   182

			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   183

			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   184

			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   185

			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   186

			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   187

			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   188

			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   189

			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   190

			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   191

			break;

   192

   193

		case e1000_82541_rev_2:

   194

		case e1000_82547_rev_2:

   195

			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   196

			break;

   197

		default:

   198

			break;

   199

		}

   200

   201

		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   202

		msleep(20);

   203

   204

		/* Now enable the transmitter */

   205

		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   206

   207

		if (hw->mac_type == e1000_82547) {

   208

			u16 fused, fine, coarse;

   209

   210

			/* Move to analog registers page */

   211

			e1000_read_phy_reg(hw,

   212

					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   213

					   &fused);

   214

   215

			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   216

				e1000_read_phy_reg(hw,

   217

						   IGP01E1000_ANALOG_FUSE_STATUS,

   218

						   &fused);

   219

   220

				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   221

				coarse =

   222

				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   223

   224

				if (coarse >

   225

				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   226

					coarse -=

   227

					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   228

					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   229

				} else if (coarse ==

   230

					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   231

					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   232

   233

				fused =

   234

				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   235

				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   236

				    (coarse &

   237

				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   238

   239

				e1000_write_phy_reg(hw,

   240

						    IGP01E1000_ANALOG_FUSE_CONTROL,

   241

						    fused);

   242

				e1000_write_phy_reg(hw,

   243

						    IGP01E1000_ANALOG_FUSE_BYPASS,

   244

						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   245

			}

   246

		}

   247

	}

   248

}

   249

   250

/**

   251

 * e1000_set_mac_type - Set the mac type member in the hw struct.

   252

 * @hw: Struct containing variables accessed by shared code

   253

 */

   254

s32 e1000_set_mac_type(struct e1000_hw *hw)

   255

{

   256

	e_dbg("e1000_set_mac_type");

   257

   258

	switch (hw->device_id) {

   259

	case E1000_DEV_ID_82542:

   260

		switch (hw->revision_id) {

   261

		case E1000_82542_2_0_REV_ID:

   262

			hw->mac_type = e1000_82542_rev2_0;

   263

			break;

   264

		case E1000_82542_2_1_REV_ID:

   265

			hw->mac_type = e1000_82542_rev2_1;

   266

			break;

   267

		default:

   268

			/* Invalid 82542 revision ID */

   269

			return -E1000_ERR_MAC_TYPE;

   270

		}

   271

		break;

   272

	case E1000_DEV_ID_82543GC_FIBER:

   273

	case E1000_DEV_ID_82543GC_COPPER:

   274

		hw->mac_type = e1000_82543;

   275

		break;

   276

	case E1000_DEV_ID_82544EI_COPPER:

   277

	case E1000_DEV_ID_82544EI_FIBER:

   278

	case E1000_DEV_ID_82544GC_COPPER:

   279

	case E1000_DEV_ID_82544GC_LOM:

   280

		hw->mac_type = e1000_82544;

   281

		break;

   282

	case E1000_DEV_ID_82540EM:

   283

	case E1000_DEV_ID_82540EM_LOM:

   284

	case E1000_DEV_ID_82540EP:

   285

	case E1000_DEV_ID_82540EP_LOM:

   286

	case E1000_DEV_ID_82540EP_LP:

   287

		hw->mac_type = e1000_82540;

   288

		break;

   289

	case E1000_DEV_ID_82545EM_COPPER:

   290

	case E1000_DEV_ID_82545EM_FIBER:

   291

		hw->mac_type = e1000_82545;

   292

		break;

   293

	case E1000_DEV_ID_82545GM_COPPER:

   294

	case E1000_DEV_ID_82545GM_FIBER:

   295

	case E1000_DEV_ID_82545GM_SERDES:

   296

		hw->mac_type = e1000_82545_rev_3;

   297

		break;

   298

	case E1000_DEV_ID_82546EB_COPPER:

   299

	case E1000_DEV_ID_82546EB_FIBER:

   300

	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   301

		hw->mac_type = e1000_82546;

   302

		break;

   303

	case E1000_DEV_ID_82546GB_COPPER:

   304

	case E1000_DEV_ID_82546GB_FIBER:

   305

	case E1000_DEV_ID_82546GB_SERDES:

   306

	case E1000_DEV_ID_82546GB_PCIE:

   307

	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   308

	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   309

		hw->mac_type = e1000_82546_rev_3;

   310

		break;

   311

	case E1000_DEV_ID_82541EI:

   312

	case E1000_DEV_ID_82541EI_MOBILE:

   313

	case E1000_DEV_ID_82541ER_LOM:

   314

		hw->mac_type = e1000_82541;

   315

		break;

   316

	case E1000_DEV_ID_82541ER:

   317

	case E1000_DEV_ID_82541GI:

   318

	case E1000_DEV_ID_82541GI_LF:

   319

	case E1000_DEV_ID_82541GI_MOBILE:

   320

		hw->mac_type = e1000_82541_rev_2;

   321

		break;

   322

	case E1000_DEV_ID_82547EI:

   323

	case E1000_DEV_ID_82547EI_MOBILE:

   324

		hw->mac_type = e1000_82547;

   325

		break;

   326

	case E1000_DEV_ID_82547GI:

   327

		hw->mac_type = e1000_82547_rev_2;

   328

		break;

   329

	case E1000_DEV_ID_INTEL_CE4100_GBE:

   330

		hw->mac_type = e1000_ce4100;

   331

		break;

   332

	default:

   333

		/* Should never have loaded on this device */

   334

		return -E1000_ERR_MAC_TYPE;

   335

	}

   336

   337

	switch (hw->mac_type) {

   338

	case e1000_82541:

   339

	case e1000_82547:

   340

	case e1000_82541_rev_2:

   341

	case e1000_82547_rev_2:

   342

		hw->asf_firmware_present = true;

   343

		break;

   344

	default:

   345

		break;

   346

	}

   347

   348

	/* The 82543 chip does not count tx_carrier_errors properly in

   349

	 * FD mode

   350

	 */

   351

	if (hw->mac_type == e1000_82543)

   352

		hw->bad_tx_carr_stats_fd = true;

   353

   354

	if (hw->mac_type > e1000_82544)

   355

		hw->has_smbus = true;

   356

   357

	return E1000_SUCCESS;

   358

}

   359

   360

/**

   361

 * e1000_set_media_type - Set media type and TBI compatibility.

   362

 * @hw: Struct containing variables accessed by shared code

   363

 */

   364

void e1000_set_media_type(struct e1000_hw *hw)

   365

{

   366

	u32 status;

   367

   368

	e_dbg("e1000_set_media_type");

   369

   370

	if (hw->mac_type != e1000_82543) {

   371

		/* tbi_compatibility is only valid on 82543 */

   372

		hw->tbi_compatibility_en = false;

   373

	}

   374

   375

	switch (hw->device_id) {

   376

	case E1000_DEV_ID_82545GM_SERDES:

   377

	case E1000_DEV_ID_82546GB_SERDES:

   378

		hw->media_type = e1000_media_type_internal_serdes;

   379

		break;

   380

	default:

   381

		switch (hw->mac_type) {

   382

		case e1000_82542_rev2_0:

   383

		case e1000_82542_rev2_1:

   384

			hw->media_type = e1000_media_type_fiber;

   385

			break;

   386

		case e1000_ce4100:

   387

			hw->media_type = e1000_media_type_copper;

   388

			break;

   389

		default:

   390

			status = er32(STATUS);

   391

			if (status & E1000_STATUS_TBIMODE) {

   392

				hw->media_type = e1000_media_type_fiber;

   393

				/* tbi_compatibility not valid on fiber */

   394

				hw->tbi_compatibility_en = false;

   395

			} else {

   396

				hw->media_type = e1000_media_type_copper;

   397

			}

   398

			break;

   399

		}

   400

	}

   401

}

   402

   403

/**

   404

 * e1000_reset_hw - reset the hardware completely

   405

 * @hw: Struct containing variables accessed by shared code

   406

 *

   407

 * Reset the transmit and receive units; mask and clear all interrupts.

   408

 */

   409

s32 e1000_reset_hw(struct e1000_hw *hw)

   410

{

   411

	u32 ctrl;

   412

	u32 ctrl_ext;

   413

	u32 icr __attribute__ ((unused));

   414

	u32 manc;

   415

	u32 led_ctrl;

   416

	s32 ret_val;

   417

   418

	e_dbg("e1000_reset_hw");

   419

   420

	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   421

	if (hw->mac_type == e1000_82542_rev2_0) {

   422

		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   423

		e1000_pci_clear_mwi(hw);

   424

	}

   425

   426

	/* Clear interrupt mask to stop board from generating interrupts */

   427

	e_dbg("Masking off all interrupts\n");

   428

	ew32(IMC, 0xffffffff);

   429

   430

	/* Disable the Transmit and Receive units.  Then delay to allow

   431

	 * any pending transactions to complete before we hit the MAC with

   432

	 * the global reset.

   433

	 */

   434

	ew32(RCTL, 0);

   435

	ew32(TCTL, E1000_TCTL_PSP);

   436

	E1000_WRITE_FLUSH();

   437

   438

	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   439

	hw->tbi_compatibility_on = false;

   440

   441

	/* Delay to allow any outstanding PCI transactions to complete before

   442

	 * resetting the device

   443

	 */

   444

	msleep(10);

   445

   446

	ctrl = er32(CTRL);

   447

   448

	/* Must reset the PHY before resetting the MAC */

   449

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   450

		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   451

		E1000_WRITE_FLUSH();

   452

		msleep(5);

   453

	}

   454

   455

	/* Issue a global reset to the MAC.  This will reset the chip's

   456

	 * transmit, receive, DMA, and link units.  It will not effect

   457

	 * the current PCI configuration.  The global reset bit is self-

   458

	 * clearing, and should clear within a microsecond.

   459

	 */

   460

	e_dbg("Issuing a global reset to MAC\n");

   461

   462

	switch (hw->mac_type) {

   463

	case e1000_82544:

   464

	case e1000_82540:

   465

	case e1000_82545:

   466

	case e1000_82546:

   467

	case e1000_82541:

   468

	case e1000_82541_rev_2:

   469

		/* These controllers can't ack the 64-bit write when issuing the

   470

		 * reset, so use IO-mapping as a workaround to issue the reset

   471

		 */

   472

		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   473

		break;

   474

	case e1000_82545_rev_3:

   475

	case e1000_82546_rev_3:

   476

		/* Reset is performed on a shadow of the control register */

   477

		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   478

		break;

   479

	case e1000_ce4100:

   480

	default:

   481

		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   482

		break;

   483

	}

   484

   485

	/* After MAC reset, force reload of EEPROM to restore power-on settings

   486

	 * to device.  Later controllers reload the EEPROM automatically, so

   487

	 * just wait for reload to complete.

   488

	 */

   489

	switch (hw->mac_type) {

   490

	case e1000_82542_rev2_0:

   491

	case e1000_82542_rev2_1:

   492

	case e1000_82543:

   493

	case e1000_82544:

   494

		/* Wait for reset to complete */

   495

		udelay(10);

   496

		ctrl_ext = er32(CTRL_EXT);

   497

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   498

		ew32(CTRL_EXT, ctrl_ext);

   499

		E1000_WRITE_FLUSH();

   500

		/* Wait for EEPROM reload */

   501

		msleep(2);

   502

		break;

   503

	case e1000_82541:

   504

	case e1000_82541_rev_2:

   505

	case e1000_82547:

   506

	case e1000_82547_rev_2:

   507

		/* Wait for EEPROM reload */

   508

		msleep(20);

   509

		break;

   510

	default:

   511

		/* Auto read done will delay 5ms or poll based on mac type */

   512

		ret_val = e1000_get_auto_rd_done(hw);

   513

		if (ret_val)

   514

			return ret_val;

   515

		break;

   516

	}

   517

   518

	/* Disable HW ARPs on ASF enabled adapters */

   519

	if (hw->mac_type >= e1000_82540) {

   520

		manc = er32(MANC);

   521

		manc &= ~(E1000_MANC_ARP_EN);

   522

		ew32(MANC, manc);

   523

	}

   524

   525

	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   526

		e1000_phy_init_script(hw);

   527

   528

		/* Configure activity LED after PHY reset */

   529

		led_ctrl = er32(LEDCTL);

   530