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/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2013 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

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    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

/* 82562G 10/100 Network Connection

    30

 * 82562G-2 10/100 Network Connection

    31

 * 82562GT 10/100 Network Connection

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 * 82562GT-2 10/100 Network Connection

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 * 82562V 10/100 Network Connection

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 * 82562V-2 10/100 Network Connection

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 * 82566DC-2 Gigabit Network Connection

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 * 82566DC Gigabit Network Connection

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 * 82566DM-2 Gigabit Network Connection

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 * 82566DM Gigabit Network Connection

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 * 82566MC Gigabit Network Connection

    40

 * 82566MM Gigabit Network Connection

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 * 82567LM Gigabit Network Connection

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 * 82567LF Gigabit Network Connection

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 * 82567V Gigabit Network Connection

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 * 82567LM-2 Gigabit Network Connection

    45

 * 82567LF-2 Gigabit Network Connection

    46

 * 82567V-2 Gigabit Network Connection

    47

 * 82567LF-3 Gigabit Network Connection

    48

 * 82567LM-3 Gigabit Network Connection

    49

 * 82567LM-4 Gigabit Network Connection

    50

 * 82577LM Gigabit Network Connection

    51

 * 82577LC Gigabit Network Connection

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 * 82578DM Gigabit Network Connection

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 * 82578DC Gigabit Network Connection

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 * 82579LM Gigabit Network Connection

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 * 82579V Gigabit Network Connection

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 */

    57

    58

#include "e1000.h"

    59

    60

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

    61

/* Offset 04h HSFSTS */

    62

union ich8_hws_flash_status {

    63

	struct ich8_hsfsts {

    64

		u16 flcdone:1;	/* bit 0 Flash Cycle Done */

    65

		u16 flcerr:1;	/* bit 1 Flash Cycle Error */

    66

		u16 dael:1;	/* bit 2 Direct Access error Log */

    67

		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */

    68

		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */

    69

		u16 reserved1:2;	/* bit 13:6 Reserved */

    70

		u16 reserved2:6;	/* bit 13:6 Reserved */

    71

		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */

    72

		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */

    73

	} hsf_status;

    74

	u16 regval;

    75

};

    76

    77

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

    78

/* Offset 06h FLCTL */

    79

union ich8_hws_flash_ctrl {

    80

	struct ich8_hsflctl {

    81

		u16 flcgo:1;	/* 0 Flash Cycle Go */

    82

		u16 flcycle:2;	/* 2:1 Flash Cycle */

    83

		u16 reserved:5;	/* 7:3 Reserved  */

    84

		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */

    85

		u16 flockdn:6;	/* 15:10 Reserved */

    86

	} hsf_ctrl;

    87

	u16 regval;

    88

};

    89

    90

/* ICH Flash Region Access Permissions */

    91

union ich8_hws_flash_regacc {

    92

	struct ich8_flracc {

    93

		u32 grra:8;	/* 0:7 GbE region Read Access */

    94

		u32 grwa:8;	/* 8:15 GbE region Write Access */

    95

		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */

    96

		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */

    97

	} hsf_flregacc;

    98

	u16 regval;

    99

};

   100

   101

/* ICH Flash Protected Region */

   102

union ich8_flash_protected_range {

   103

	struct ich8_pr {

   104

		u32 base:13;     /* 0:12 Protected Range Base */

   105

		u32 reserved1:2; /* 13:14 Reserved */

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		u32 rpe:1;       /* 15 Read Protection Enable */

   107

		u32 limit:13;    /* 16:28 Protected Range Limit */

   108

		u32 reserved2:2; /* 29:30 Reserved */

   109

		u32 wpe:1;       /* 31 Write Protection Enable */

   110

	} range;

   111

	u32 regval;

   112

};

   113

   114

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   115

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   116

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   117

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   118

						u32 offset, u8 byte);

   119

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   120

					 u8 *data);

   121

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   122

					 u16 *data);

   123

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   124

					 u8 size, u16 *data);

   125

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   126

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   127

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   128

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   129

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   130

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   131

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   132

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   133

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   134

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   135

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   136

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   137

static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   138

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   139

static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   140

static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   141

static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

   142

static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

   143

static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   144

static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   145

static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);

   146

   147

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   148

{

   149

	return readw(hw->flash_address + reg);

   150

}

   151

   152

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   153

{

   154

	return readl(hw->flash_address + reg);

   155

}

   156

   157

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   158

{

   159

	writew(val, hw->flash_address + reg);

   160

}

   161

   162

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   163

{

   164

	writel(val, hw->flash_address + reg);

   165

}

   166

   167

#define er16flash(reg)		__er16flash(hw, (reg))

   168

#define er32flash(reg)		__er32flash(hw, (reg))

   169

#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

   170

#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   171

   172

/**

   173

 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers

   174

 *  @hw: pointer to the HW structure

   175

 *

   176

 *  Test access to the PHY registers by reading the PHY ID registers.  If

   177

 *  the PHY ID is already known (e.g. resume path) compare it with known ID,

   178

 *  otherwise assume the read PHY ID is correct if it is valid.

   179

 *

   180

 *  Assumes the sw/fw/hw semaphore is already acquired.

   181

 **/

   182

static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)

   183

{

   184

	u16 phy_reg = 0;

   185

	u32 phy_id = 0;

   186

	s32 ret_val;

   187

	u16 retry_count;

   188

   189

	for (retry_count = 0; retry_count < 2; retry_count++) {

   190

		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);

   191

		if (ret_val || (phy_reg == 0xFFFF))

   192

			continue;

   193

		phy_id = (u32)(phy_reg << 16);

   194

   195

		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);

   196

		if (ret_val || (phy_reg == 0xFFFF)) {

   197

			phy_id = 0;

   198

			continue;

   199

		}

   200

		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

   201

		break;

   202

	}

   203

   204

	if (hw->phy.id) {

   205

		if (hw->phy.id == phy_id)

   206

			return true;

   207

	} else if (phy_id) {

   208

		hw->phy.id = phy_id;

   209

		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

   210

		return true;

   211

	}

   212

   213

	/* In case the PHY needs to be in mdio slow mode,

   214

	 * set slow mode and try to get the PHY id again.

   215

	 */

   216

	hw->phy.ops.release(hw);

   217

	ret_val = e1000_set_mdio_slow_mode_hv(hw);

   218

	if (!ret_val)

   219

		ret_val = e1000e_get_phy_id(hw);

   220

	hw->phy.ops.acquire(hw);

   221

   222

	return !ret_val;

   223

}

   224

   225

/**

   226

 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds

   227

 *  @hw: pointer to the HW structure

   228

 *

   229

 *  Workarounds/flow necessary for PHY initialization during driver load

   230

 *  and resume paths.

   231

 **/

   232

static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

   233

{

   234

	u32 mac_reg, fwsm = er32(FWSM);

   235

	s32 ret_val;

   236

	u16 phy_reg;

   237

   238

	/* Gate automatic PHY configuration by hardware on managed and

   239

	 * non-managed 82579 and newer adapters.

   240

	 */

   241

	e1000_gate_hw_phy_config_ich8lan(hw, true);

   242

   243

	ret_val = hw->phy.ops.acquire(hw);

   244

	if (ret_val) {

   245

		e_dbg("Failed to initialize PHY flow\n");

   246

		goto out;

   247

	}

   248

   249

	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is

   250

	 * inaccessible and resetting the PHY is not blocked, toggle the

   251

	 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   252

	 */

   253

	switch (hw->mac.type) {

   254

	case e1000_pch_lpt:

   255

		if (e1000_phy_is_accessible_pchlan(hw))

   256

			break;

   257

   258

		/* Before toggling LANPHYPC, see if PHY is accessible by

   259

		 * forcing MAC to SMBus mode first.

   260

		 */

   261

		mac_reg = er32(CTRL_EXT);

   262

		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

   263

		ew32(CTRL_EXT, mac_reg);

   264

   265

		/* fall-through */

   266

	case e1000_pch2lan:

   267

		if (e1000_phy_is_accessible_pchlan(hw)) {

   268

			if (hw->mac.type == e1000_pch_lpt) {

   269

				/* Unforce SMBus mode in PHY */

   270

				e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);

   271

				phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;

   272

				e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

   273

   274

				/* Unforce SMBus mode in MAC */

   275

				mac_reg = er32(CTRL_EXT);

   276

				mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   277

				ew32(CTRL_EXT, mac_reg);

   278

			}

   279

			break;

   280

		}

   281

   282

		/* fall-through */

   283

	case e1000_pchlan:

   284

		if ((hw->mac.type == e1000_pchlan) &&

   285

		    (fwsm & E1000_ICH_FWSM_FW_VALID))

   286

			break;

   287

   288

		if (hw->phy.ops.check_reset_block(hw)) {

   289

			e_dbg("Required LANPHYPC toggle blocked by ME\n");

   290

			break;

   291

		}

   292

   293

		e_dbg("Toggling LANPHYPC\n");

   294

   295

		/* Set Phy Config Counter to 50msec */

   296

		mac_reg = er32(FEXTNVM3);

   297

		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

   298

		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

   299

		ew32(FEXTNVM3, mac_reg);

   300

   301

		if (hw->mac.type == e1000_pch_lpt) {

   302

			/* Toggling LANPHYPC brings the PHY out of SMBus mode

   303

			 * So ensure that the MAC is also out of SMBus mode

   304

			 */

   305

			mac_reg = er32(CTRL_EXT);

   306

			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   307

			ew32(CTRL_EXT, mac_reg);

   308

		}

   309

   310

		/* Toggle LANPHYPC Value bit */

   311

		mac_reg = er32(CTRL);

   312

		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;

   313

		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

   314

		ew32(CTRL, mac_reg);

   315

		e1e_flush();

   316

		usleep_range(10, 20);

   317

		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   318

		ew32(CTRL, mac_reg);

   319

		e1e_flush();

   320

		if (hw->mac.type < e1000_pch_lpt) {

   321

			msleep(50);

   322

		} else {

   323

			u16 count = 20;

   324

			do {

   325

				usleep_range(5000, 10000);

   326

			} while (!(er32(CTRL_EXT) &

   327

				   E1000_CTRL_EXT_LPCD) && count--);

   328

		}

   329

		break;

   330

	default:

   331

		break;

   332

	}

   333

   334

	hw->phy.ops.release(hw);

   335

   336

	/* Reset the PHY before any access to it.  Doing so, ensures

   337

	 * that the PHY is in a known good state before we read/write

   338

	 * PHY registers.  The generic reset is sufficient here,

   339

	 * because we haven't determined the PHY type yet.

   340

	 */

   341

	ret_val = e1000e_phy_hw_reset_generic(hw);

   342

   343

out:

   344

	/* Ungate automatic PHY configuration on non-managed 82579 */

   345

	if ((hw->mac.type == e1000_pch2lan) &&

   346

	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   347

		usleep_range(10000, 20000);

   348

		e1000_gate_hw_phy_config_ich8lan(hw, false);

   349

	}

   350

   351

	return ret_val;

   352

}

   353

   354

/**

   355

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   356

 *  @hw: pointer to the HW structure

   357

 *

   358

 *  Initialize family-specific PHY parameters and function pointers.

   359

 **/

   360

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   361

{

   362

	struct e1000_phy_info *phy = &hw->phy;

   363

	s32 ret_val;

   364

   365

	phy->addr                     = 1;

   366

	phy->reset_delay_us           = 100;

   367

   368

	phy->ops.set_page             = e1000_set_page_igp;

   369

	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   370

	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   371

	phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;

   372

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   373

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   374

	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   375

	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   376

	phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;

   377

	phy->ops.power_up             = e1000_power_up_phy_copper;

   378

	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   379

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   380

   381

	phy->id = e1000_phy_unknown;

   382

   383

	ret_val = e1000_init_phy_workarounds_pchlan(hw);

   384

	if (ret_val)

   385

		return ret_val;

   386

   387

	if (phy->id == e1000_phy_unknown)

   388

		switch (hw->mac.type) {

   389

		default:

   390

			ret_val = e1000e_get_phy_id(hw);

   391

			if (ret_val)

   392

				return ret_val;

   393

			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   394

				break;

   395

			/* fall-through */

   396

		case e1000_pch2lan:

   397

		case e1000_pch_lpt:

   398

			/* In case the PHY needs to be in mdio slow mode,

   399

			 * set slow mode and try to get the PHY id again.

   400

			 */

   401

			ret_val = e1000_set_mdio_slow_mode_hv(hw);

   402

			if (ret_val)

   403

				return ret_val;

   404

			ret_val = e1000e_get_phy_id(hw);

   405

			if (ret_val)

   406

				return ret_val;

   407

			break;

   408

		}

   409

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   410

   411

	switch (phy->type) {

   412

	case e1000_phy_82577:

   413

	case e1000_phy_82579:

   414

	case e1000_phy_i217:

   415

		phy->ops.check_polarity = e1000_check_polarity_82577;

   416

		phy->ops.force_speed_duplex =

   417

		    e1000_phy_force_speed_duplex_82577;

   418

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   419

		phy->ops.get_info = e1000_get_phy_info_82577;

   420

		phy->ops.commit = e1000e_phy_sw_reset;

   421

		break;

   422

	case e1000_phy_82578:

   423

		phy->ops.check_polarity = e1000_check_polarity_m88;

   424

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   425

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   426

		phy->ops.get_info = e1000e_get_phy_info_m88;

   427

		break;

   428

	default:

   429

		ret_val = -E1000_ERR_PHY;

   430

		break;

   431

	}

   432

   433

	return ret_val;

   434

}

   435

   436

/**

   437

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   438

 *  @hw: pointer to the HW structure

   439

 *

   440

 *  Initialize family-specific PHY parameters and function pointers.

   441

 **/

   442

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   443

{

   444

	struct e1000_phy_info *phy = &hw->phy;

   445

	s32 ret_val;

   446

	u16 i = 0;

   447

   448

	phy->addr			= 1;

   449

	phy->reset_delay_us		= 100;

   450

   451

	phy->ops.power_up               = e1000_power_up_phy_copper;

   452

	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

   453

   454

	/* We may need to do this twice - once for IGP and if that fails,

   455

	 * we'll set BM func pointers and try again

   456

	 */

   457

	ret_val = e1000e_determine_phy_address(hw);

   458

	if (ret_val) {

   459

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   460

		phy->ops.read_reg  = e1000e_read_phy_reg_bm;

   461

		ret_val = e1000e_determine_phy_address(hw);

   462

		if (ret_val) {

   463

			e_dbg("Cannot determine PHY addr. Erroring out\n");

   464

			return ret_val;

   465

		}

   466

	}

   467

   468

	phy->id = 0;

   469

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   470

	       (i++ < 100)) {

   471

		usleep_range(1000, 2000);

   472

		ret_val = e1000e_get_phy_id(hw);

   473

		if (ret_val)

   474

			return ret_val;

   475

	}

   476

   477

	/* Verify phy id */

   478

	switch (phy->id) {

   479

	case IGP03E1000_E_PHY_ID:

   480

		phy->type = e1000_phy_igp_3;

   481

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   482

		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   483

		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   484

		phy->ops.get_info = e1000e_get_phy_info_igp;

   485

		phy->ops.check_polarity = e1000_check_polarity_igp;

   486

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   487

		break;

   488

	case IFE_E_PHY_ID:

   489

	case IFE_PLUS_E_PHY_ID:

   490

	case IFE_C_E_PHY_ID:

   491

		phy->type = e1000_phy_ife;

   492

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   493

		phy->ops.get_info = e1000_get_phy_info_ife;

   494

		phy->ops.check_polarity = e1000_check_polarity_ife;

   495

		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   496

		break;

   497

	case BME1000_E_PHY_ID:

   498

		phy->type = e1000_phy_bm;

   499

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   500

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   501

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   502

		phy->ops.commit = e1000e_phy_sw_reset;

   503

		phy->ops.get_info = e1000e_get_phy_info_m88;

   504

		phy->ops.check_polarity = e1000_check_polarity_m88;

   505

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   506

		break;

   507

	default:

   508

		return -E1000_ERR_PHY;

   509

		break;

   510

	}

   511

   512

	return 0;

   513

}

   514

   515

/**

   516

 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   517

 *  @hw: pointer to the HW structure

   518

 *

   519

 *  Initialize family-specific NVM parameters and function

   520

 *  pointers.

   521

 **/

   522

static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   523

{

   524

	struct e1000_nvm_info *nvm = &hw->nvm;

   525

	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   526

	u32 gfpreg, sector_base_addr, sector_end_addr;

   527

	u16 i;

   528

   529

	/* Can't read flash registers if the register set isn't mapped. */

   530