1

/*

     2

 * r8169.c: RealTek 8169/8168/8101 ethernet driver.

     3

 *

     4

 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>

     5

 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>

     6

 * Copyright (c) a lot of people too. Please respect their work.

     7

 *

     8

 * See MAINTAINERS file for support contact information.

     9

 */

    10

    11

#include <linux/module.h>

    12

#include <linux/moduleparam.h>

    13

#include <linux/pci.h>

    14

#include <linux/netdevice.h>

    15

#include <linux/etherdevice.h>

    16

#include <linux/delay.h>

    17

#include <linux/ethtool.h>

    18

#include <linux/mii.h>

    19

#include <linux/if_vlan.h>

    20

#include <linux/crc32.h>

    21

#include <linux/in.h>

    22

#include <linux/ip.h>

    23

#include <linux/tcp.h>

    24

#include <linux/init.h>

    25

#include <linux/dma-mapping.h>

    26

#include <linux/pm_runtime.h>

    27

    28

#include <asm/system.h>

    29

#include <asm/io.h>

    30

#include <asm/irq.h>

    31

#include "../globals.h"

    32

#include "ecdev.h"

    33

    34

#define RTL8169_VERSION "2.3LK-NAPI"

    35

#define MODULENAME "ec_r8169"

    36

#define PFX MODULENAME ": "

    37

    38

#ifdef RTL8169_DEBUG

    39

#define assert(expr) \

    40

	if (!(expr)) {					\

    41

		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\

    42

		#expr,__FILE__,__func__,__LINE__);		\

    43

	}

    44

#define dprintk(fmt, args...) \

    45

	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)

    46

#else

    47

#define assert(expr) do {} while (0)

    48

#define dprintk(fmt, args...)	do {} while (0)

    49

#endif /* RTL8169_DEBUG */

    50

    51

#define R8169_MSG_DEFAULT \

    52

	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

    53

    54

#define TX_BUFFS_AVAIL(tp) \

    55

	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

    56

    57

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

    58

   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

    59

static const int multicast_filter_limit = 32;

    60

    61

/* MAC address length */

    62

#define MAC_ADDR_LEN	6

    63

    64

#define MAX_READ_REQUEST_SHIFT	12

    65

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */

    66

#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    67

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

    68

#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */

    69

#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */

    70

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

    71

    72

#define R8169_REGS_SIZE		256

    73

#define R8169_NAPI_WEIGHT	64

    74

#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */

    75

#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */

    76

#define RX_BUF_SIZE	1536	/* Rx Buffer size */

    77

#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))

    78

#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

    79

    80

#define RTL8169_TX_TIMEOUT	(6*HZ)

    81

#define RTL8169_PHY_TIMEOUT	(10*HZ)

    82

    83

#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)

    84

#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)

    85

#define RTL_EEPROM_SIG_ADDR	0x0000

    86

    87

/* write/read MMIO register */

    88

#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))

    89

#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))

    90

#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))

    91

#define RTL_R8(reg)		readb (ioaddr + (reg))

    92

#define RTL_R16(reg)		readw (ioaddr + (reg))

    93

#define RTL_R32(reg)		readl (ioaddr + (reg))

    94

    95

enum mac_version {

    96

	RTL_GIGA_MAC_NONE   = 0x00,

    97

	RTL_GIGA_MAC_VER_01 = 0x01, // 8169

    98

	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S

    99

	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S

   100

	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB

   101

	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd

   102

	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe

   103

	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e

   104

	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e

   105

	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e

   106

	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e

   107

	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb

   108

	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be

   109

	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb

   110

	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?

   111

	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?

   112

	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec

   113

	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf

   114

	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP

   115

	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C

   116

	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C

   117

	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C

   118

	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C

   119

	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP

   120

	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP

   121

	RTL_GIGA_MAC_VER_25 = 0x19, // 8168D

   122

	RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D

   123

	RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP

   124

};

   125

   126

#define _R(NAME,MAC,MASK) \

   127

	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

   128

   129

static const struct {

   130

	const char *name;

   131

	u8 mac_version;

   132

	u32 RxConfigMask;	/* Clears the bits supported by this chip */

   133

} rtl_chip_info[] = {

   134

	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169

   135

	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S

   136

	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S

   137

	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB

   138

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd

   139

	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe

   140

	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E

   141

	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E

   142

	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E

   143

	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E

   144

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E

   145

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E

   146

	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139

   147

	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139

   148

	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139

   149

	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E

   150

	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E

   151

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E

   152

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E

   153

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E

   154

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E

   155

	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E

   156

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E

   157

	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E

   158

	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E

   159

	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E

   160

	_R("RTL8168dp/8111dp",	RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E

   161

};

   162

#undef _R

   163

   164

enum cfg_version {

   165

	RTL_CFG_0 = 0x00,

   166

	RTL_CFG_1,

   167

	RTL_CFG_2

   168

};

   169

   170

static void rtl_hw_start_8169(struct net_device *);

   171

static void rtl_hw_start_8168(struct net_device *);

   172

static void rtl_hw_start_8101(struct net_device *);

   173

   174

static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {

   175

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },

   176

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },

   177

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },

   178

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },

   179

	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },

   180

	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },

   181

	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },

   182

	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },

   183

	{ PCI_VENDOR_ID_LINKSYS,		0x1032,

   184

		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },

   185

	{ 0x0001,				0x8168,

   186

		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },

   187

	{0,},

   188

};

   189

   190

/* prevent driver from being loaded automatically */

   191

//MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

   192

   193

/*

   194

 * we set our copybreak very high so that we don't have

   195

 * to allocate 16k frames all the time (see note in

   196

 * rtl8169_open()

   197

 */

   198

static int rx_copybreak = 16383;

   199

static int use_dac;

   200

static struct {

   201

	u32 msg_enable;

   202

} debug = { -1 };

   203

   204

enum rtl_registers {

   205

	MAC0		= 0,	/* Ethernet hardware address. */

   206

	MAC4		= 4,

   207

	MAR0		= 8,	/* Multicast filter. */

   208

	CounterAddrLow		= 0x10,

   209

	CounterAddrHigh		= 0x14,

   210

	TxDescStartAddrLow	= 0x20,

   211

	TxDescStartAddrHigh	= 0x24,

   212

	TxHDescStartAddrLow	= 0x28,

   213

	TxHDescStartAddrHigh	= 0x2c,

   214

	FLASH		= 0x30,

   215

	ERSR		= 0x36,

   216

	ChipCmd		= 0x37,

   217

	TxPoll		= 0x38,

   218

	IntrMask	= 0x3c,

   219

	IntrStatus	= 0x3e,

   220

	TxConfig	= 0x40,

   221

	RxConfig	= 0x44,

   222

	RxMissed	= 0x4c,

   223

	Cfg9346		= 0x50,

   224

	Config0		= 0x51,

   225

	Config1		= 0x52,

   226

	Config2		= 0x53,

   227

	Config3		= 0x54,

   228

	Config4		= 0x55,

   229

	Config5		= 0x56,

   230

	MultiIntr	= 0x5c,

   231

	PHYAR		= 0x60,

   232

	PHYstatus	= 0x6c,

   233

	RxMaxSize	= 0xda,

   234

	CPlusCmd	= 0xe0,

   235

	IntrMitigate	= 0xe2,

   236

	RxDescAddrLow	= 0xe4,

   237

	RxDescAddrHigh	= 0xe8,

   238

	EarlyTxThres	= 0xec,

   239

	FuncEvent	= 0xf0,

   240

	FuncEventMask	= 0xf4,

   241

	FuncPresetState	= 0xf8,

   242

	FuncForceEvent	= 0xfc,

   243

};

   244

   245

enum rtl8110_registers {

   246

	TBICSR			= 0x64,

   247

	TBI_ANAR		= 0x68,

   248

	TBI_LPAR		= 0x6a,

   249

};

   250

   251

enum rtl8168_8101_registers {

   252

	CSIDR			= 0x64,

   253

	CSIAR			= 0x68,

   254

#define	CSIAR_FLAG			0x80000000

   255

#define	CSIAR_WRITE_CMD			0x80000000

   256

#define	CSIAR_BYTE_ENABLE		0x0f

   257

#define	CSIAR_BYTE_ENABLE_SHIFT		12

   258

#define	CSIAR_ADDR_MASK			0x0fff

   259

   260

	EPHYAR			= 0x80,

   261

#define	EPHYAR_FLAG			0x80000000

   262

#define	EPHYAR_WRITE_CMD		0x80000000

   263

#define	EPHYAR_REG_MASK			0x1f

   264

#define	EPHYAR_REG_SHIFT		16

   265

#define	EPHYAR_DATA_MASK		0xffff

   266

	DBG_REG			= 0xd1,

   267

#define	FIX_NAK_1			(1 << 4)

   268

#define	FIX_NAK_2			(1 << 3)

   269

	EFUSEAR			= 0xdc,

   270

#define	EFUSEAR_FLAG			0x80000000

   271

#define	EFUSEAR_WRITE_CMD		0x80000000

   272

#define	EFUSEAR_READ_CMD		0x00000000

   273

#define	EFUSEAR_REG_MASK		0x03ff

   274

#define	EFUSEAR_REG_SHIFT		8

   275

#define	EFUSEAR_DATA_MASK		0xff

   276

};

   277

   278

enum rtl_register_content {

   279

	/* InterruptStatusBits */

   280

	SYSErr		= 0x8000,

   281

	PCSTimeout	= 0x4000,

   282

	SWInt		= 0x0100,

   283

	TxDescUnavail	= 0x0080,

   284

	RxFIFOOver	= 0x0040,

   285

	LinkChg		= 0x0020,

   286

	RxOverflow	= 0x0010,

   287

	TxErr		= 0x0008,

   288

	TxOK		= 0x0004,

   289

	RxErr		= 0x0002,

   290

	RxOK		= 0x0001,

   291

   292

	/* RxStatusDesc */

   293

	RxFOVF	= (1 << 23),

   294

	RxRWT	= (1 << 22),

   295

	RxRES	= (1 << 21),

   296

	RxRUNT	= (1 << 20),

   297

	RxCRC	= (1 << 19),

   298

   299

	/* ChipCmdBits */

   300

	CmdReset	= 0x10,

   301

	CmdRxEnb	= 0x08,

   302

	CmdTxEnb	= 0x04,

   303

	RxBufEmpty	= 0x01,

   304

   305

	/* TXPoll register p.5 */

   306

	HPQ		= 0x80,		/* Poll cmd on the high prio queue */

   307

	NPQ		= 0x40,		/* Poll cmd on the low prio queue */

   308

	FSWInt		= 0x01,		/* Forced software interrupt */

   309

   310

	/* Cfg9346Bits */

   311

	Cfg9346_Lock	= 0x00,

   312

	Cfg9346_Unlock	= 0xc0,

   313

   314

	/* rx_mode_bits */

   315

	AcceptErr	= 0x20,

   316

	AcceptRunt	= 0x10,

   317

	AcceptBroadcast	= 0x08,

   318

	AcceptMulticast	= 0x04,

   319

	AcceptMyPhys	= 0x02,

   320

	AcceptAllPhys	= 0x01,

   321

   322

	/* RxConfigBits */

   323

	RxCfgFIFOShift	= 13,

   324

	RxCfgDMAShift	=  8,

   325

   326

	/* TxConfigBits */

   327

	TxInterFrameGapShift = 24,

   328

	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

   329

   330

	/* Config1 register p.24 */

   331

	LEDS1		= (1 << 7),

   332

	LEDS0		= (1 << 6),

   333

	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */

   334

	Speed_down	= (1 << 4),

   335

	MEMMAP		= (1 << 3),

   336

	IOMAP		= (1 << 2),

   337

	VPD		= (1 << 1),

   338

	PMEnable	= (1 << 0),	/* Power Management Enable */

   339

   340

	/* Config2 register p. 25 */

   341

	PCI_Clock_66MHz = 0x01,

   342

	PCI_Clock_33MHz = 0x00,

   343

   344

	/* Config3 register p.25 */

   345

	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */

   346

	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */

   347

	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */

   348

   349

	/* Config5 register p.27 */

   350

	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */

   351

	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */

   352

	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */

   353

	LanWake		= (1 << 1),	/* LanWake enable/disable */

   354

	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

   355

   356

	/* TBICSR p.28 */

   357

	TBIReset	= 0x80000000,

   358

	TBILoopback	= 0x40000000,

   359

	TBINwEnable	= 0x20000000,

   360

	TBINwRestart	= 0x10000000,

   361

	TBILinkOk	= 0x02000000,

   362

	TBINwComplete	= 0x01000000,

   363

   364

	/* CPlusCmd p.31 */

   365

	EnableBist	= (1 << 15),	// 8168 8101

   366

	Mac_dbgo_oe	= (1 << 14),	// 8168 8101

   367

	Normal_mode	= (1 << 13),	// unused

   368

	Force_half_dup	= (1 << 12),	// 8168 8101

   369

	Force_rxflow_en	= (1 << 11),	// 8168 8101

   370

	Force_txflow_en	= (1 << 10),	// 8168 8101

   371

	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101

   372

	ASF		= (1 << 8),	// 8168 8101

   373

	PktCntrDisable	= (1 << 7),	// 8168 8101

   374

	Mac_dbgo_sel	= 0x001c,	// 8168

   375

	RxVlan		= (1 << 6),

   376

	RxChkSum	= (1 << 5),

   377

	PCIDAC		= (1 << 4),

   378

	PCIMulRW	= (1 << 3),

   379

	INTT_0		= 0x0000,	// 8168

   380

	INTT_1		= 0x0001,	// 8168

   381

	INTT_2		= 0x0002,	// 8168

   382

	INTT_3		= 0x0003,	// 8168

   383

   384

	/* rtl8169_PHYstatus */

   385

	TBI_Enable	= 0x80,

   386

	TxFlowCtrl	= 0x40,

   387

	RxFlowCtrl	= 0x20,

   388

	_1000bpsF	= 0x10,

   389

	_100bps		= 0x08,

   390

	_10bps		= 0x04,

   391

	LinkStatus	= 0x02,

   392

	FullDup		= 0x01,

   393

   394

	/* _TBICSRBit */

   395

	TBILinkOK	= 0x02000000,

   396

   397

	/* DumpCounterCommand */

   398

	CounterDump	= 0x8,

   399

};

   400

   401

enum desc_status_bit {

   402

	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */

   403

	RingEnd		= (1 << 30), /* End of descriptor ring */

   404

	FirstFrag	= (1 << 29), /* First segment of a packet */

   405

	LastFrag	= (1 << 28), /* Final segment of a packet */

   406

   407

	/* Tx private */

   408

	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */

   409

	MSSShift	= 16,        /* MSS value position */

   410

	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */

   411

	IPCS		= (1 << 18), /* Calculate IP checksum */

   412

	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */

   413

	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */

   414

	TxVlanTag	= (1 << 17), /* Add VLAN tag */

   415

   416

	/* Rx private */

   417

	PID1		= (1 << 18), /* Protocol ID bit 1/2 */

   418

	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

   419

   420

#define RxProtoUDP	(PID1)

   421

#define RxProtoTCP	(PID0)

   422

#define RxProtoIP	(PID1 | PID0)

   423

#define RxProtoMask	RxProtoIP

   424

   425

	IPFail		= (1 << 16), /* IP checksum failed */

   426

	UDPFail		= (1 << 15), /* UDP/IP checksum failed */

   427

	TCPFail		= (1 << 14), /* TCP/IP checksum failed */

   428

	RxVlanTag	= (1 << 16), /* VLAN tag available */

   429

};

   430

   431

#define RsvdMask	0x3fffc000

   432

   433

struct TxDesc {

   434

	__le32 opts1;

   435

	__le32 opts2;

   436

	__le64 addr;

   437

};

   438

   439

struct RxDesc {

   440

	__le32 opts1;

   441

	__le32 opts2;

   442

	__le64 addr;

   443

};

   444

   445

struct ring_info {

   446

	struct sk_buff	*skb;

   447

	u32		len;

   448

	u8		__pad[sizeof(void *) - sizeof(u32)];

   449

};

   450

   451

enum features {

   452

	RTL_FEATURE_WOL		= (1 << 0),

   453

	RTL_FEATURE_MSI		= (1 << 1),

   454

	RTL_FEATURE_GMII	= (1 << 2),

   455

};

   456

   457

struct rtl8169_counters {

   458

	__le64	tx_packets;

   459

	__le64	rx_packets;

   460

	__le64	tx_errors;

   461

	__le32	rx_errors;

   462

	__le16	rx_missed;

   463

	__le16	align_errors;

   464

	__le32	tx_one_collision;

   465

	__le32	tx_multi_collision;

   466

	__le64	rx_unicast;

   467

	__le64	rx_broadcast;

   468

	__le32	rx_multicast;

   469

	__le16	tx_aborted;

   470

	__le16	tx_underun;

   471

};

   472

   473

struct rtl8169_private {

   474

	void __iomem *mmio_addr;	/* memory map physical address */

   475

	struct pci_dev *pci_dev;	/* Index of PCI device */

   476

	struct net_device *dev;

   477

	struct napi_struct napi;

   478

	spinlock_t lock;		/* spin lock flag */

   479

	u32 msg_enable;

   480

	int chipset;

   481

	int mac_version;

   482

	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */

   483

	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */

   484

	u32 dirty_rx;

   485

	u32 dirty_tx;

   486

	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */

   487

	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */

   488

	dma_addr_t TxPhyAddr;

   489

	dma_addr_t RxPhyAddr;

   490

	struct sk_buff *Rx_skbuff[NUM_RX_DESC];	/* Rx data buffers */

   491

	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */

   492

	unsigned align;

   493

	unsigned rx_buf_sz;

   494

	struct timer_list timer;

   495

	u16 cp_cmd;

   496

	u16 intr_event;

   497

	u16 napi_event;

   498

	u16 intr_mask;

   499

	int phy_1000_ctrl_reg;

   500

#ifdef CONFIG_R8169_VLAN

   501

	struct vlan_group *vlgrp;

   502

#endif

   503

	int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);

   504

	int (*get_settings)(struct net_device *, struct ethtool_cmd *);

   505

	void (*phy_reset_enable)(void __iomem *);

   506

	void (*hw_start)(struct net_device *);

   507

	unsigned int (*phy_reset_pending)(void __iomem *);

   508

	unsigned int (*link_ok)(void __iomem *);

   509

	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);

   510

	int pcie_cap;

   511

	struct delayed_work task;

   512

	unsigned features;

   513

   514

	struct mii_if_info mii;

   515

	struct rtl8169_counters counters;

   516

	u32 saved_wolopts;

   517

   518

	ec_device_t *ecdev;

   519

	unsigned long ec_watchdog_jiffies;

   520

};

   521

   522

MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   523

MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver");

   524

module_param(rx_copybreak, int, 0);

   525

MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");

   526

module_param(use_dac, int, 0);

   527

MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");

   528

module_param_named(debug, debug.msg_enable, int, 0);

   529

MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");

   530

MODULE_LICENSE("GPL");