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/******************************************************************************

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 *

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 *  $Id$

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 *

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 *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

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 *

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 *  This file is part of the IgH EtherCAT Master.

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 *

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 *  The IgH EtherCAT Master is free software; you can redistribute it and/or

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 *  modify it under the terms of the GNU General Public License version 2, as

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 *  published by the Free Software Foundation.

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 *

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 *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

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 *  Public License for more details.

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 *

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 *  You should have received a copy of the GNU General Public License along

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 *  with the IgH EtherCAT Master; if not, write to the Free Software

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 *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

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 *

    22

 *  ---

    23

 *

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 *  The license mentioned above concerns the source code only. Using the

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 *  EtherCAT technology and brand is only permitted in compliance with the

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 *  industrial property and similar rights of Beckhoff Automation GmbH.

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 *

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 *****************************************************************************/

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/**

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   \file

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   EtherCAT driver for RTL8139-compatible NICs.

    33

*/

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/*****************************************************************************/

    36

    37

/*

    38

  Former documentation:

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    40

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41

    42

	Maintained by Jeff Garzik <jgarzik@pobox.com>

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	Copyright 2000-2002 Jeff Garzik

    44

    45

	Much code comes from Donald Becker's rtl8139.c driver,

    46

	versions 1.13 and older.  This driver was originally based

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	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48

    49

	-----<snip>-----

    50

    51

        	Written 1997-2001 by Donald Becker.

    52

		This software may be used and distributed according to the

    53

		terms of the GNU General Public License (GPL), incorporated

    54

		herein by reference.  Drivers based on or derived from this

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		code fall under the GPL and must retain the authorship,

    56

		copyright and license notice.  This file is not a complete

    57

		program and may only be used when the entire operating

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		system is licensed under the GPL.

    59

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		This driver is for boards based on the RTL8129 and RTL8139

    61

		PCI ethernet chips.

    62

    63

		The author may be reached as becker@scyld.com, or C/O Scyld

    64

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65

		MD 21403

    66

    67

		Support and updates available at

    68

		http://www.scyld.com/network/rtl8139.html

    69

    70

		Twister-tuning table provided by Kinston

    71

		<shangh@realtek.com.tw>.

    72

    73

	-----<snip>-----

    74

    75

	This software may be used and distributed according to the terms

    76

	of the GNU General Public License, incorporated herein by reference.

    77

    78

	Contributors:

    79

    80

		Donald Becker - he wrote the original driver, kudos to him!

    81

		(but please don't e-mail him for support, this isn't his driver)

    82

    83

		Tigran Aivazian - bug fixes, skbuff free cleanup

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		Martin Mares - suggestions for PCI cleanup

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		David S. Miller - PCI DMA and softnet updates

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		Ernst Gill - fixes ported from BSD driver

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    91

		Daniel Kobras - identified specific locations of

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			posted MMIO write bugginess

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    94

		Gerard Sharp - bug fix, testing and feedback

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    96

		David Ford - Rx ring wrap fix

    97

    98

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

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		to find and fix a crucial bug on older chipsets.

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		Donald Becker/Chris Butterworth/Marcus Westergren -

   102

		Noticed various Rx packet size-related buglets.

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   104

		Santiago Garcia Mantinan - testing and feedback

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		Jens David - 2.2.x kernel backports

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   108

		Martin Dennett - incredibly helpful insight on undocumented

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		features of the 8139 chips

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   111

		Jean-Jacques Michel - bug fix

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		Tobias Ringström - Rx interrupt status checking suggestion

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		Andrew Morton - Clear blocked signals, avoid

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		buffer overrun setting current->comm.

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		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

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		Robert Kuebel - Save kernel thread from dying on any signal.

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	Submitting bug reports:

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   124

		"rtl8139-diag -mmmaaavvveefN" output

   125

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

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   127

*/

   128

   129

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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   131

#define DRV_NAME	"ec_8139too"

   132

#define DRV_VERSION	"0.9.28"

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#include <linux/module.h>

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#include <linux/kernel.h>

   137

#include <linux/compiler.h>

   138

#include <linux/pci.h>

   139

#include <linux/init.h>

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#include <linux/interrupt.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

   143

#include <linux/rtnetlink.h>

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#include <linux/delay.h>

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#include <linux/ethtool.h>

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#include <linux/mii.h>

   147

#include <linux/completion.h>

   148

#include <linux/crc32.h>

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#include <linux/io.h>

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#include <linux/uaccess.h>

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#include <linux/gfp.h>

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#include <asm/irq.h>

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#include "../globals.h"

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#include "ecdev.h"

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   157

#define RTL8139_DRIVER_NAME DRV_NAME \

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                            " EtherCAT-capable Fast Ethernet driver " \

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                            DRV_VERSION ", master " EC_MASTER_VERSION

   160

   161

#define PFX DRV_NAME ": "

   162

   163

/* Default Message level */

   164

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

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                                 NETIF_MSG_PROBE  | \

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                                 NETIF_MSG_LINK)

   167

   168

   169

/* define to 1, 2 or 3 to enable copious debugging info */

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#define RTL8139_DEBUG 0

   171

   172

/* define to 1 to disable lightweight runtime debugging checks */

   173

#undef RTL8139_NDEBUG

   174

   175

   176

#ifdef RTL8139_NDEBUG

   177

#  define assert(expr) do {} while (0)

   178

#else

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#  define assert(expr) \

   180

        if (unlikely(!(expr))) {				\

   181

		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   182

		       #expr, __FILE__, __func__, __LINE__);	\

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        }

   184

#endif

   185

   186

   187

/* A few user-configurable values. */

   188

/* media options */

   189

#define MAX_UNITS 8

   190

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   191

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   192

   193

/* Whether to use MMIO or PIO. Default to MMIO. */

   194

#ifdef CONFIG_8139TOO_PIO

   195

static int use_io = 1;

   196

#else

   197

static int use_io = 0;

   198

#endif

   199

   200

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   201

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   202

static int multicast_filter_limit = 32;

   203

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/* bitmapped message enable number */

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static int debug = -1;

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   207

/*

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 * Receive ring size

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 * Warning: 64K ring has hardware issues and may lock up.

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 */

   211

#if defined(CONFIG_SH_DREAMCAST)

   212

#define RX_BUF_IDX 0	/* 8K ring */

   213

#else

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#define RX_BUF_IDX	2	/* 32K ring */

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#endif

   216

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   217

#define RX_BUF_PAD	16

   218

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

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   220

#if RX_BUF_LEN == 65536

   221

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   222

#else

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#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   224

#endif

   225

   226

/* Number of Tx descriptor registers. */

   227

#define NUM_TX_DESC	4

   228

   229

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   230

#define MAX_ETH_FRAME_SIZE	1536

   231

   232

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   233

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   234

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   235

   236

/* PCI Tuning Parameters

   237

   Threshold is bytes transferred to chip before transmission starts. */

   238

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   239

   240

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   241

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   242

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   243

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   244

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   245

   246

/* Operational parameters that usually are not changed. */

   247

/* Time in jiffies before concluding the transmitter is hung. */

   248

#define TX_TIMEOUT  (6*HZ)

   249

   250

   251

enum {

   252

	HAS_MII_XCVR = 0x010000,

   253

	HAS_CHIP_XCVR = 0x020000,

   254

	HAS_LNK_CHNG = 0x040000,

   255

};

   256

   257

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   258

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

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#define RTL_MIN_IO_SIZE 0x80

   260

#define RTL8139B_IO_SIZE 256

   261

   262

#define RTL8129_CAPS	HAS_MII_XCVR

   263

#define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   264

   265

typedef enum {

   266

	RTL8139 = 0,

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	RTL8129,

   268

} board_t;

   269

   270

   271

/* indexed by board_t, above */

   272

static const struct {

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	const char *name;

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	u32 hw_flags;

   275

} board_info[] __devinitdata = {

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	{ "RealTek RTL8139", RTL8139_CAPS },

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	{ "RealTek RTL8129", RTL8129_CAPS },

   278

};

   279

   280

   281

static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

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	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301

   302

#ifdef CONFIG_SH_SECUREEDGE5410

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	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

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#endif

   306

#ifdef CONFIG_8139TOO_8129

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	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   308

#endif

   309

   310

	/* some crazy cards report invalid vendor ids like

   311

	 * 0x0001 here.  The other ids are valid and constant,

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	 * so we simply don't match on the main vendor id.

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	 */

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	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

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	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   317

   318

	{0,}

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};

   320

   321

/* prevent driver from being loaded automatically */

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//MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   323

   324

static struct {

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	const char str[ETH_GSTRING_LEN];

   326

} ethtool_stats_keys[] = {

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	{ "early_rx" },

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	{ "tx_buf_mapped" },

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	{ "tx_timeouts" },

   330

	{ "rx_lost_in_ring" },

   331

};

   332

   333

/* The rest of these values should never change. */

   334

   335

/* Symbolic offsets to registers. */

   336

enum RTL8139_registers {

   337

	MAC0		= 0,	 /* Ethernet hardware address. */

   338

	MAR0		= 8,	 /* Multicast filter. */

   339

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   340

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   341

	RxBuf		= 0x30,

   342

	ChipCmd		= 0x37,

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	RxBufPtr	= 0x38,

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	RxBufAddr	= 0x3A,

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	IntrMask	= 0x3C,

   346

	IntrStatus	= 0x3E,

   347

	TxConfig	= 0x40,

   348

	RxConfig	= 0x44,

   349

	Timer		= 0x48,	 /* A general-purpose counter. */

   350

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   351

	Cfg9346		= 0x50,

   352

	Config0		= 0x51,

   353

	Config1		= 0x52,

   354

	TimerInt	= 0x54,

   355

	MediaStatus	= 0x58,

   356

	Config3		= 0x59,

   357

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   358

	HltClk		= 0x5B,

   359

	MultiIntr	= 0x5C,

   360

	TxSummary	= 0x60,

   361

	BasicModeCtrl	= 0x62,

   362

	BasicModeStatus	= 0x64,

   363

	NWayAdvert	= 0x66,

   364

	NWayLPAR	= 0x68,

   365

	NWayExpansion	= 0x6A,

   366

	/* Undocumented registers, but required for proper operation. */

   367

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

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	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   369

	PARA78		= 0x78,

   370

	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   371

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   372

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   373

};

   374

   375

enum ClearBitMasks {

   376

	MultiIntrClear	= 0xF000,

   377

	ChipCmdClear	= 0xE2,

   378

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   379

};

   380

   381

enum ChipCmdBits {

   382

	CmdReset	= 0x10,

   383

	CmdRxEnb	= 0x08,

   384

	CmdTxEnb	= 0x04,

   385

	RxBufEmpty	= 0x01,

   386

};

   387

   388

/* Interrupt register bits, using my own meaningful names. */

   389

enum IntrStatusBits {

   390

	PCIErr		= 0x8000,

   391

	PCSTimeout	= 0x4000,

   392

	RxFIFOOver	= 0x40,

   393

	RxUnderrun	= 0x20,

   394

	RxOverflow	= 0x10,

   395

	TxErr		= 0x08,

   396

	TxOK		= 0x04,

   397

	RxErr		= 0x02,

   398

	RxOK		= 0x01,

   399

   400

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   401

};

   402

   403

enum TxStatusBits {

   404

	TxHostOwns	= 0x2000,

   405

	TxUnderrun	= 0x4000,

   406

	TxStatOK	= 0x8000,

   407

	TxOutOfWindow	= 0x20000000,

   408

	TxAborted	= 0x40000000,

   409

	TxCarrierLost	= 0x80000000,

   410

};

   411

enum RxStatusBits {

   412

	RxMulticast	= 0x8000,

   413

	RxPhysical	= 0x4000,

   414

	RxBroadcast	= 0x2000,

   415

	RxBadSymbol	= 0x0020,

   416

	RxRunt		= 0x0010,

   417

	RxTooLong	= 0x0008,

   418

	RxCRCErr	= 0x0004,

   419

	RxBadAlign	= 0x0002,

   420

	RxStatusOK	= 0x0001,

   421

};

   422

   423

/* Bits in RxConfig. */

   424

enum rx_mode_bits {

   425

	AcceptErr	= 0x20,

   426

	AcceptRunt	= 0x10,

   427

	AcceptBroadcast	= 0x08,

   428

	AcceptMulticast	= 0x04,

   429

	AcceptMyPhys	= 0x02,

   430

	AcceptAllPhys	= 0x01,

   431

};

   432

   433

/* Bits in TxConfig. */

   434

enum tx_config_bits {

   435

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   436

        TxIFGShift	= 24,

   437

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   438

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   439

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   440

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   441

   442

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   443

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   444

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   445

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   446

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   447

   448

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   449

};

   450

   451

/* Bits in Config1 */

   452

enum Config1Bits {

   453

	Cfg1_PM_Enable	= 0x01,

   454

	Cfg1_VPD_Enable	= 0x02,

   455

	Cfg1_PIO	= 0x04,

   456

	Cfg1_MMIO	= 0x08,

   457

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   458

	Cfg1_Driver_Load = 0x20,

   459

	Cfg1_LED0	= 0x40,

   460

	Cfg1_LED1	= 0x80,

   461

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   462

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   463

};

   464

   465

/* Bits in Config3 */

   466

enum Config3Bits {

   467

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   468

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   469

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   470

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   471

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   472

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   473

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   474

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   475

};

   476

   477

/* Bits in Config4 */

   478

enum Config4Bits {

   479

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   480

};

   481

   482

/* Bits in Config5 */

   483

enum Config5Bits {

   484

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   485

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   486

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   487

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   488

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   489

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   490

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   491

};

   492

   493

enum RxConfigBits {

   494

	/* rx fifo threshold */

   495

	RxCfgFIFOShift	= 13,

   496

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   497

   498

	/* Max DMA burst */

   499

	RxCfgDMAShift	= 8,

   500

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   501

   502

	/* rx ring buffer length */

   503

	RxCfgRcv8K	= 0,

   504

	RxCfgRcv16K	= (1 << 11),

   505

	RxCfgRcv32K	= (1 << 12),

   506

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   507

   508

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   509

	RxNoWrap	= (1 << 7),

   510

};

   511

   512

/* Twister tuning parameters from RealTek.

   513

   Completely undocumented, but required to tune bad links on some boards. */

   514

enum CSCRBits {

   515

	CSCR_LinkOKBit		= 0x0400,

   516

	CSCR_LinkChangeBit	= 0x0800,

   517

	CSCR_LinkStatusBits	= 0x0f000,

   518

	CSCR_LinkDownOffCmd	= 0x003c0,

   519

	CSCR_LinkDownCmd	= 0x0f3c0,

   520

};

   521

   522

enum Cfg9346Bits {

   523

	Cfg9346_Lock	= 0x00,

   524

	Cfg9346_Unlock	= 0xC0,

   525

};

   526

   527

typedef enum {

   528

	CH_8139	= 0,

   529

	CH_8139_K,

   530

	CH_8139A,