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/* Intel(R) Gigabit Ethernet Linux driver

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 * Copyright(c) 2007-2014 Intel Corporation.

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

    12

 *

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 * You should have received a copy of the GNU General Public License along with

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 * this program; if not, see <http://www.gnu.org/licenses/>.

    15

 *

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 * The full GNU General Public License is included in this distribution in

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 * the file called "COPYING".

    18

 *

    19

 * Contact Information:

    20

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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 *

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 * vim: noexpandtab

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 */

    25

    26

/* Linux PRO/1000 Ethernet Driver main header file */

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    28

#ifndef _IGB_H_

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#define _IGB_H_

    30

    31

/* EtherCAT header file */

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#include "../ecdev.h"

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    34

#include "e1000_mac-3.18-ethercat.h"

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#include "e1000_82575-3.18-ethercat.h"

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    37

#include <linux/clocksource.h>

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#include <linux/net_tstamp.h>

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#include <linux/ptp_clock_kernel.h>

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#include <linux/bitops.h>

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#include <linux/if_vlan.h>

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#include <linux/i2c.h>

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#include <linux/i2c-algo-bit.h>

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#include <linux/pci.h>

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#include <linux/mdio.h>

    46

    47

struct igb_adapter;

    48

    49

#define E1000_PCS_CFG_IGN_SD	1

    50

    51

/* Interrupt defines */

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#define IGB_START_ITR		648 /* ~6000 ints/sec */

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#define IGB_4K_ITR		980

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#define IGB_20K_ITR		196

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#define IGB_70K_ITR		56

    56

    57

/* TX/RX descriptor defines */

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#define IGB_DEFAULT_TXD		256

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#define IGB_DEFAULT_TX_WORK	128

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#define IGB_MIN_TXD		80

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#define IGB_MAX_TXD		4096

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    63

#define IGB_DEFAULT_RXD		256

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#define IGB_MIN_RXD		80

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#define IGB_MAX_RXD		4096

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    67

#define IGB_DEFAULT_ITR		3 /* dynamic */

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#define IGB_MAX_ITR_USECS	10000

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#define IGB_MIN_ITR_USECS	10

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#define NON_Q_VECTORS		1

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#define MAX_Q_VECTORS		8

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#define MAX_MSIX_ENTRIES	10

    73

    74

/* Transmit and receive queues */

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#define IGB_MAX_RX_QUEUES	8

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#define IGB_MAX_RX_QUEUES_82575	4

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#define IGB_MAX_RX_QUEUES_I211	2

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#define IGB_MAX_TX_QUEUES	8

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#define IGB_MAX_VF_MC_ENTRIES	30

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#define IGB_MAX_VF_FUNCTIONS	8

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#define IGB_MAX_VFTA_ENTRIES	128

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#define IGB_82576_VF_DEV_ID	0x10CA

    83

#define IGB_I350_VF_DEV_ID	0x1520

    84

    85

/* NVM version defines */

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#define IGB_MAJOR_MASK		0xF000

    87

#define IGB_MINOR_MASK		0x0FF0

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#define IGB_BUILD_MASK		0x000F

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#define IGB_COMB_VER_MASK	0x00FF

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#define IGB_MAJOR_SHIFT		12

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#define IGB_MINOR_SHIFT		4

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#define IGB_COMB_VER_SHFT	8

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#define IGB_NVM_VER_INVALID	0xFFFF

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#define IGB_ETRACK_SHIFT	16

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#define NVM_ETRACK_WORD		0x0042

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#define NVM_COMB_VER_OFF	0x0083

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#define NVM_COMB_VER_PTR	0x003d

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    99

struct vf_data_storage {

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	unsigned char vf_mac_addresses[ETH_ALEN];

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	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];

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	u16 num_vf_mc_hashes;

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	u16 vlans_enabled;

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	u32 flags;

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	unsigned long last_nack;

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	u16 pf_vlan; /* When set, guest VLAN config not allowed. */

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	u16 pf_qos;

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	u16 tx_rate;

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	bool spoofchk_enabled;

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};

   111

   112

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */

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#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */

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#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */

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#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

   116

   117

/* RX descriptor control thresholds.

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 * PTHRESH - MAC will consider prefetch if it has fewer than this number of

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 *           descriptors available in its onboard memory.

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 *           Setting this to 0 disables RX descriptor prefetch.

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 * HTHRESH - MAC will only prefetch if there are at least this many descriptors

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 *           available in host memory.

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 *           If PTHRESH is 0, this should also be 0.

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 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back

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 *           descriptors until either it has this many to write back, or the

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 *           ITR timer expires.

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 */

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#define IGB_RX_PTHRESH	((hw->mac.type == e1000_i354) ? 12 : 8)

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#define IGB_RX_HTHRESH	8

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#define IGB_TX_PTHRESH	((hw->mac.type == e1000_i354) ? 20 : 8)

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#define IGB_TX_HTHRESH	1

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#define IGB_RX_WTHRESH	((hw->mac.type == e1000_82576 && \

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			  (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)

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#define IGB_TX_WTHRESH	((hw->mac.type == e1000_82576 && \

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			  (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)

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   137

/* this is the size past which hardware will drop packets when setting LPE=0 */

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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

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   140

/* Supported Rx Buffer Sizes */

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#define IGB_RXBUFFER_256	256

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#define IGB_RXBUFFER_2048	2048

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#define IGB_RX_HDR_LEN		IGB_RXBUFFER_256

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#define IGB_RX_BUFSZ		IGB_RXBUFFER_2048

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   146

/* How many Rx Buffers do we bundle into one write to the hardware ? */

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#define IGB_RX_BUFFER_WRITE	16 /* Must be power of 2 */

   148

   149

#define AUTO_ALL_MODES		0

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#define IGB_EEPROM_APME		0x0400

   151

   152

#ifndef IGB_MASTER_SLAVE

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/* Switch to override PHY master/slave setting */

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#define IGB_MASTER_SLAVE	e1000_ms_hw_default

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#endif

   156

   157

#define IGB_MNG_VLAN_NONE	-1

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   159

enum igb_tx_flags {

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	/* cmd_type flags */

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	IGB_TX_FLAGS_VLAN	= 0x01,

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	IGB_TX_FLAGS_TSO	= 0x02,

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	IGB_TX_FLAGS_TSTAMP	= 0x04,

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   165

	/* olinfo flags */

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	IGB_TX_FLAGS_IPV4	= 0x10,

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	IGB_TX_FLAGS_CSUM	= 0x20,

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};

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   170

/* VLAN info */

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#define IGB_TX_FLAGS_VLAN_MASK	0xffff0000

   172

#define IGB_TX_FLAGS_VLAN_SHIFT	16

   173

   174

/* The largest size we can write to the descriptor is 65535.  In order to

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 * maintain a power of two alignment we have to limit ourselves to 32K.

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 */

   177

#define IGB_MAX_TXD_PWR	15

   178

#define IGB_MAX_DATA_PER_TXD	(1 << IGB_MAX_TXD_PWR)

   179

   180

/* Tx Descriptors needed, worst case */

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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)

   182

#define DESC_NEEDED (MAX_SKB_FRAGS + 4)

   183

   184

/* EEPROM byte offsets */

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#define IGB_SFF_8472_SWAP		0x5C

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#define IGB_SFF_8472_COMP		0x5E

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   188

/* Bitmasks */

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#define IGB_SFF_ADDRESSING_MODE		0x4

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#define IGB_SFF_8472_UNSUP		0x00

   191

   192

/* wrapper around a pointer to a socket buffer,

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 * so a DMA handle can be stored along with the buffer

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 */

   195

struct igb_tx_buffer {

   196

	union e1000_adv_tx_desc *next_to_watch;

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	unsigned long time_stamp;

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	struct sk_buff *skb;

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	unsigned int bytecount;

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	u16 gso_segs;

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	__be16 protocol;

   202

   203

	DEFINE_DMA_UNMAP_ADDR(dma);

   204

	DEFINE_DMA_UNMAP_LEN(len);

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	u32 tx_flags;

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};

   207

   208

struct igb_rx_buffer {

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	dma_addr_t dma;

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	struct page *page;

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	unsigned int page_offset;

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};

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struct igb_tx_queue_stats {

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	u64 packets;

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	u64 bytes;

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	u64 restart_queue;

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	u64 restart_queue2;

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};

   220

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struct igb_rx_queue_stats {

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	u64 packets;

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	u64 bytes;

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	u64 drops;

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	u64 csum_err;

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	u64 alloc_failed;

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};

   228

   229

struct igb_ring_container {

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	struct igb_ring *ring;		/* pointer to linked list of rings */

   231

	unsigned int total_bytes;	/* total bytes processed this int */

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	unsigned int total_packets;	/* total packets processed this int */

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	u16 work_limit;			/* total work allowed per interrupt */

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	u8 count;			/* total number of rings in vector */

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	u8 itr;				/* current ITR setting for ring */

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};

   237

   238

struct igb_ring {

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	struct igb_q_vector *q_vector;	/* backlink to q_vector */

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	struct net_device *netdev;	/* back pointer to net_device */

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	struct device *dev;		/* device pointer for dma mapping */

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	union {				/* array of buffer info structs */

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		struct igb_tx_buffer *tx_buffer_info;

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		struct igb_rx_buffer *rx_buffer_info;

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	};

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	void *desc;			/* descriptor ring memory */

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	unsigned long flags;		/* ring specific flags */

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	void __iomem *tail;		/* pointer to ring tail register */

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	dma_addr_t dma;			/* phys address of the ring */

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	unsigned int  size;		/* length of desc. ring in bytes */

   251

   252

	u16 count;			/* number of desc. in the ring */

   253

	u8 queue_index;			/* logical index of the ring*/

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	u8 reg_idx;			/* physical index of the ring */

   255

   256

	/* everything past this point are written often */

   257

	u16 next_to_clean;

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	u16 next_to_use;

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	u16 next_to_alloc;

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   261

	union {

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		/* TX */

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		struct {

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			struct igb_tx_queue_stats tx_stats;

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			struct u64_stats_sync tx_syncp;

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			struct u64_stats_sync tx_syncp2;

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		};

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		/* RX */

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		struct {

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			struct sk_buff *skb;

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			struct igb_rx_queue_stats rx_stats;

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			struct u64_stats_sync rx_syncp;

   273

		};

   274

	};

   275

} ____cacheline_internodealigned_in_smp;

   276

   277

struct igb_q_vector {

   278

	struct igb_adapter *adapter;	/* backlink */

   279

	int cpu;			/* CPU for DCA */

   280

	u32 eims_value;			/* EIMS mask value */

   281

   282

	u16 itr_val;

   283

	u8 set_itr;

   284

	void __iomem *itr_register;

   285

   286

	struct igb_ring_container rx, tx;

   287

   288

	struct napi_struct napi;

   289

	struct rcu_head rcu;	/* to avoid race with update stats on free */

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	char name[IFNAMSIZ + 9];

   291

   292

	/* for dynamic allocation of rings associated with this q_vector */

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	struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;

   294

};

   295

   296

enum e1000_ring_flags_t {

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	IGB_RING_FLAG_RX_SCTP_CSUM,

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	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,

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	IGB_RING_FLAG_TX_CTX_IDX,

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	IGB_RING_FLAG_TX_DETECT_HANG

   301

};

   302

   303

#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)

   304

   305

#define IGB_RX_DESC(R, i)	\

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	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))

   307

#define IGB_TX_DESC(R, i)	\

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	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))

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#define IGB_TX_CTXTDESC(R, i)	\

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	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

   311

   312

/* igb_test_staterr - tests bits within Rx descriptor status and error fields */

   313

static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,

   314

				      const u32 stat_err_bits)

   315

{

   316

	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);

   317

}

   318

   319

/* igb_desc_unused - calculate if we have unused descriptors */

   320

static inline int igb_desc_unused(struct igb_ring *ring)

   321

{

   322

	if (ring->next_to_clean > ring->next_to_use)

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		return ring->next_to_clean - ring->next_to_use - 1;

   324

   325

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;

   326

}

   327

   328

#ifdef CONFIG_IGB_HWMON

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   330

#define IGB_HWMON_TYPE_LOC	0

   331

#define IGB_HWMON_TYPE_TEMP	1

   332

#define IGB_HWMON_TYPE_CAUTION	2

   333

#define IGB_HWMON_TYPE_MAX	3

   334

   335

struct hwmon_attr {

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	struct device_attribute dev_attr;

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	struct e1000_hw *hw;

   338

	struct e1000_thermal_diode_data *sensor;

   339

	char name[12];

   340

	};

   341

   342

struct hwmon_buff {

   343

	struct attribute_group group;

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	const struct attribute_group *groups[2];

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	struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];

   346

	struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];

   347

	unsigned int n_hwmon;

   348

	};

   349

#endif

   350

   351

#define IGB_RETA_SIZE	128

   352

   353

/* board specific private data structure */

   354

struct igb_adapter {

   355

	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

   356

   357

	struct net_device *netdev;

   358

   359

	unsigned long state;

   360

	unsigned int flags;

   361

   362

	unsigned int num_q_vectors;

   363

	struct msix_entry msix_entries[MAX_MSIX_ENTRIES];

   364

   365

	/* Interrupt Throttle Rate */

   366

	u32 rx_itr_setting;

   367

	u32 tx_itr_setting;

   368

	u16 tx_itr;

   369

	u16 rx_itr;

   370

   371

	/* TX */

   372

	u16 tx_work_limit;

   373

	u32 tx_timeout_count;

   374

	int num_tx_queues;

   375

	struct igb_ring *tx_ring[16];

   376

   377

	/* RX */

   378

	int num_rx_queues;

   379

	struct igb_ring *rx_ring[16];

   380

   381

	u32 max_frame_size;

   382

	u32 min_frame_size;

   383

   384

	struct timer_list watchdog_timer;

   385

	struct timer_list phy_info_timer;

   386

   387

	u16 mng_vlan_id;

   388

	u32 bd_number;

   389

	u32 wol;

   390

	u32 en_mng_pt;

   391

	u16 link_speed;

   392

	u16 link_duplex;

   393

   394

	struct work_struct reset_task;

   395

	struct work_struct watchdog_task;

   396

	bool fc_autoneg;

   397

	u8  tx_timeout_factor;

   398

	struct timer_list blink_timer;

   399

	unsigned long led_status;

   400

   401

	/* OS defined structs */

   402

	struct pci_dev *pdev;

   403

   404

	spinlock_t stats64_lock;

   405

	struct rtnl_link_stats64 stats64;

   406

   407

	/* structs defined in e1000_hw.h */

   408

	struct e1000_hw hw;

   409

	struct e1000_hw_stats stats;

   410

	struct e1000_phy_info phy_info;

   411

   412

	u32 test_icr;

   413

	struct igb_ring test_tx_ring;

   414

	struct igb_ring test_rx_ring;

   415

   416

	int msg_enable;

   417

   418

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];

   419

	u32 eims_enable_mask;

   420

	u32 eims_other;

   421

   422

	/* to not mess up cache alignment, always add to the bottom */

   423

	u16 tx_ring_count;

   424

	u16 rx_ring_count;

   425

	unsigned int vfs_allocated_count;

   426

	struct vf_data_storage *vf_data;

   427

	int vf_rate_link_speed;

   428

	u32 rss_queues;

   429

	u32 wvbr;

   430

	u32 *shadow_vfta;

   431

   432

	struct ptp_clock *ptp_clock;

   433

	struct ptp_clock_info ptp_caps;

   434

	struct delayed_work ptp_overflow_work;

   435

	struct work_struct ptp_tx_work;

   436

	struct sk_buff *ptp_tx_skb;

   437

	struct hwtstamp_config tstamp_config;

   438

	unsigned long ptp_tx_start;

   439

	unsigned long last_rx_ptp_check;

   440

	unsigned long last_rx_timestamp;

   441

	spinlock_t tmreg_lock;

   442

	struct cyclecounter cc;

   443

	struct timecounter tc;

   444

	u32 tx_hwtstamp_timeouts;

   445

	u32 rx_hwtstamp_cleared;

   446

   447

	char fw_version[32];

   448

#ifdef CONFIG_IGB_HWMON

   449

	struct hwmon_buff *igb_hwmon_buff;

   450

	bool ets;

   451

#endif

   452

	struct i2c_algo_bit_data i2c_algo;

   453

	struct i2c_adapter i2c_adap;

   454

	struct i2c_client *i2c_client;

   455

	u32 rss_indir_tbl_init;

   456

	u8 rss_indir_tbl[IGB_RETA_SIZE];

   457

   458

	unsigned long link_check_timeout;

   459

	int copper_tries;

   460

	struct e1000_info ei;

   461

	u16 eee_advert;

   462

   463

	/* EtherCAT device variables */

   464

	ec_device_t *ecdev;

   465

	unsigned long ec_watchdog_jiffies;

   466

};

   467

   468

#define IGB_FLAG_HAS_MSI		(1 << 0)

   469

#define IGB_FLAG_DCA_ENABLED		(1 << 1)

   470

#define IGB_FLAG_QUAD_PORT_A		(1 << 2)

   471

#define IGB_FLAG_QUEUE_PAIRS		(1 << 3)

   472

#define IGB_FLAG_DMAC			(1 << 4)

   473

#define IGB_FLAG_PTP			(1 << 5)

   474

#define IGB_FLAG_RSS_FIELD_IPV4_UDP	(1 << 6)

   475

#define IGB_FLAG_RSS_FIELD_IPV6_UDP	(1 << 7)

   476

#define IGB_FLAG_WOL_SUPPORTED		(1 << 8)

   477

#define IGB_FLAG_NEED_LINK_UPDATE	(1 << 9)

   478

#define IGB_FLAG_MEDIA_RESET		(1 << 10)

   479

#define IGB_FLAG_MAS_CAPABLE		(1 << 11)

   480

#define IGB_FLAG_MAS_ENABLE		(1 << 12)

   481

#define IGB_FLAG_HAS_MSIX		(1 << 13)

   482

#define IGB_FLAG_EEE			(1 << 14)

   483

   484

/* Media Auto Sense */

   485

#define IGB_MAS_ENABLE_0		0X0001

   486

#define IGB_MAS_ENABLE_1		0X0002

   487

#define IGB_MAS_ENABLE_2		0X0004

   488

#define IGB_MAS_ENABLE_3		0X0008

   489

   490

/* DMA Coalescing defines */

   491

#define IGB_MIN_TXPBSIZE	20408

   492

#define IGB_TX_BUF_4096		4096

   493

#define IGB_DMCTLX_DCFLUSH_DIS	0x80000000  /* Disable DMA Coal Flush */

   494

   495

#define IGB_82576_TSYNC_SHIFT	19

   496

#define IGB_TS_HDR_LEN		16

   497

enum e1000_state_t {

   498

	__IGB_TESTING,

   499

	__IGB_RESETTING,

   500

	__IGB_DOWN,

   501

	__IGB_PTP_TX_IN_PROGRESS,

   502

};

   503

   504

enum igb_boards {

   505

	board_82575,

   506

};

   507

   508

extern char igb_driver_name[];

   509

extern char igb_driver_version[];

   510

   511

int igb_up(struct igb_adapter *);

   512

void igb_down(struct igb_adapter *);

   513

void igb_reinit_locked(struct igb_adapter *);

   514

void igb_reset(struct igb_adapter *);

   515

int igb_reinit_queues(struct igb_adapter *);

   516

void igb_write_rss_indir_tbl(struct igb_adapter *);

   517

int igb_set_spd_dplx(struct igb_adapter *, u32, u8);

   518

int igb_setup_tx_resources(struct igb_ring *);

   519

int igb_setup_rx_resources(struct igb_ring *);

   520

void igb_free_tx_resources(struct igb_ring *);

   521

void igb_free_rx_resources(struct igb_ring *);

   522

void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);

   523

void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);

   524

void igb_setup_tctl(struct igb_adapter *);

   525

void igb_setup_rctl(struct igb_adapter *);

   526

netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);

   527

void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);

   528

void igb_alloc_rx_buffers(struct igb_ring *, u16);

   529