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/* Intel(R) Gigabit Ethernet Linux driver

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 * Copyright(c) 2007-2014 Intel Corporation.

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms and conditions of the GNU General Public License,

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 * version 2, as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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 * more details.

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 *

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 * You should have received a copy of the GNU General Public License along with

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 * this program; if not, see <http://www.gnu.org/licenses/>.

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 *

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 * The full GNU General Public License is included in this distribution in

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 * the file called "COPYING".

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 *

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 * Contact Information:

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 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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 */

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#ifndef _E1000_PHY_H_

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#define _E1000_PHY_H_

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enum e1000_ms_type {

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	e1000_ms_hw_default = 0,

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	e1000_ms_force_master,

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	e1000_ms_force_slave,

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	e1000_ms_auto

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};

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enum e1000_smart_speed {

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	e1000_smart_speed_default = 0,

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	e1000_smart_speed_on,

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	e1000_smart_speed_off

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};

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s32  igb_check_downshift(struct e1000_hw *hw);

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s32  igb_check_reset_block(struct e1000_hw *hw);

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s32  igb_copper_link_setup_igp(struct e1000_hw *hw);

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s32  igb_copper_link_setup_m88(struct e1000_hw *hw);

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s32  igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);

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s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);

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s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);

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s32  igb_get_cable_length_m88(struct e1000_hw *hw);

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s32  igb_get_cable_length_m88_gen2(struct e1000_hw *hw);

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s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);

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s32  igb_get_phy_id(struct e1000_hw *hw);

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s32  igb_get_phy_info_igp(struct e1000_hw *hw);

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s32  igb_get_phy_info_m88(struct e1000_hw *hw);

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s32  igb_phy_sw_reset(struct e1000_hw *hw);

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s32  igb_phy_hw_reset(struct e1000_hw *hw);

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s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);

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s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);

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s32  igb_setup_copper_link(struct e1000_hw *hw);

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s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);

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s32  igb_phy_has_link(struct e1000_hw *hw, u32 iterations,

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				u32 usec_interval, bool *success);

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void igb_power_up_phy_copper(struct e1000_hw *hw);

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void igb_power_down_phy_copper(struct e1000_hw *hw);

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s32  igb_phy_init_script_igp3(struct e1000_hw *hw);

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s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);

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s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);

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s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);

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s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);

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s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);

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s32  igb_copper_link_setup_82580(struct e1000_hw *hw);

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s32  igb_get_phy_info_82580(struct e1000_hw *hw);

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s32  igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);

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s32  igb_get_cable_length_82580(struct e1000_hw *hw);

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s32  igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);

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s32  igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);

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s32  igb_check_polarity_m88(struct e1000_hw *hw);

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/* IGP01E1000 Specific Registers */

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#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */

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#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */

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#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */

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#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */

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#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */

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#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */

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#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4

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#define IGP01E1000_PHY_POLARITY_MASK      0x0078

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#define IGP01E1000_PSCR_AUTO_MDIX         0x1000

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#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */

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#define IGP01E1000_PSCFR_SMART_SPEED      0x0080

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#define I82580_ADDR_REG                   16

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#define I82580_CFG_REG                    22

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#define I82580_CFG_ASSERT_CRS_ON_TX       (1 << 15)

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#define I82580_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */

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#define I82580_CTRL_REG                   23

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#define I82580_CTRL_DOWNSHIFT_MASK        (7 << 10)

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/* 82580 specific PHY registers */

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#define I82580_PHY_CTRL_2            18

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#define I82580_PHY_LBK_CTRL          19

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#define I82580_PHY_STATUS_2          26

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#define I82580_PHY_DIAG_STATUS       31

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/* I82580 PHY Status 2 */

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#define I82580_PHY_STATUS2_REV_POLARITY   0x0400

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#define I82580_PHY_STATUS2_MDIX           0x0800

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#define I82580_PHY_STATUS2_SPEED_MASK     0x0300

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#define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200

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#define I82580_PHY_STATUS2_SPEED_100MBPS  0x0100

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/* I82580 PHY Control 2 */

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#define I82580_PHY_CTRL2_MANUAL_MDIX      0x0200

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#define I82580_PHY_CTRL2_AUTO_MDI_MDIX    0x0400

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#define I82580_PHY_CTRL2_MDIX_CFG_MASK    0x0600

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/* I82580 PHY Diagnostics Status */

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#define I82580_DSTATUS_CABLE_LENGTH       0x03FC

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#define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2

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/* 82580 PHY Power Management */

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#define E1000_82580_PHY_POWER_MGMT	0xE14

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#define E1000_82580_PM_SPD		0x0001 /* Smart Power Down */

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#define E1000_82580_PM_D0_LPLU		0x0002 /* For D0a states */

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#define E1000_82580_PM_D3_LPLU		0x0004 /* For all other states */

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#define E1000_82580_PM_GO_LINKD		0x0020 /* Go Link Disconnect */

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/* Enable flexible speed on link-up */

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#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */

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#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */

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#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000

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#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002

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#define IGP01E1000_PSSR_MDIX              0x0800

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#define IGP01E1000_PSSR_SPEED_MASK        0xC000

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#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000

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#define IGP02E1000_PHY_CHANNEL_NUM        4

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#define IGP02E1000_PHY_AGC_A              0x11B1

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#define IGP02E1000_PHY_AGC_B              0x12B1

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#define IGP02E1000_PHY_AGC_C              0x14B1

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#define IGP02E1000_PHY_AGC_D              0x18B1

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#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */

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#define IGP02E1000_AGC_LENGTH_MASK        0x7F

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#define IGP02E1000_AGC_RANGE              15

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#define E1000_CABLE_LENGTH_UNDEFINED      0xFF

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/* GS40G - I210 PHY defines */

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#define GS40G_PAGE_SELECT		0x16

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#define GS40G_PAGE_SHIFT		16

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#define GS40G_OFFSET_MASK		0xFFFF

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#define GS40G_PAGE_2			0x20000

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#define GS40G_MAC_REG2			0x15

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#define GS40G_MAC_LB			0x4140

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#define GS40G_MAC_SPEED_1G		0X0006

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#define GS40G_COPPER_SPEC		0x0010

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#define GS40G_LINE_LB			0x4000

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/* SFP modules ID memory locations */

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#define E1000_SFF_IDENTIFIER_OFFSET	0x00

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#define E1000_SFF_IDENTIFIER_SFF	0x02

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#define E1000_SFF_IDENTIFIER_SFP	0x03

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#define E1000_SFF_ETH_FLAGS_OFFSET	0x06

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/* Flags for SFP modules compatible with ETH up to 1Gb */

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struct e1000_sfp_flags {

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	u8 e1000_base_sx:1;

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	u8 e1000_base_lx:1;

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	u8 e1000_base_cx:1;

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	u8 e1000_base_t:1;

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	u8 e100_base_lx:1;

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	u8 e100_base_fx:1;

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	u8 e10_base_bx10:1;

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	u8 e10_base_px:1;

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};

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#endif