1

/* Intel PRO/1000 Linux driver

     2

 * Copyright(c) 1999 - 2014 Intel Corporation.

     3

 *

     4

 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

     8

 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

    13

 * The full GNU General Public License is included in this distribution in

    14

 * the file called "COPYING".

    15

 *

    16

 * Contact Information:

    17

 * Linux NICS <linux.nics@intel.com>

    18

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    19

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    20

 */

    21

    22

#include "e1000-3.16-ethercat.h"

    23

    24

/**

    25

 *  e1000e_get_bus_info_pcie - Get PCIe bus information

    26

 *  @hw: pointer to the HW structure

    27

 *

    28

 *  Determines and stores the system bus information for a particular

    29

 *  network interface.  The following bus information is determined and stored:

    30

 *  bus speed, bus width, type (PCIe), and PCIe function.

    31

 **/

    32

s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)

    33

{

    34

	struct e1000_mac_info *mac = &hw->mac;

    35

	struct e1000_bus_info *bus = &hw->bus;

    36

	struct e1000_adapter *adapter = hw->adapter;

    37

	u16 pcie_link_status, cap_offset;

    38

    39

	cap_offset = adapter->pdev->pcie_cap;

    40

	if (!cap_offset) {

    41

		bus->width = e1000_bus_width_unknown;

    42

	} else {

    43

		pci_read_config_word(adapter->pdev,

    44

				     cap_offset + PCIE_LINK_STATUS,

    45

				     &pcie_link_status);

    46

		bus->width = (enum e1000_bus_width)((pcie_link_status &

    47

						     PCIE_LINK_WIDTH_MASK) >>

    48

						    PCIE_LINK_WIDTH_SHIFT);

    49

	}

    50

    51

	mac->ops.set_lan_id(hw);

    52

    53

	return 0;

    54

}

    55

    56

/**

    57

 *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices

    58

 *

    59

 *  @hw: pointer to the HW structure

    60

 *

    61

 *  Determines the LAN function id by reading memory-mapped registers

    62

 *  and swaps the port value if requested.

    63

 **/

    64

void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)

    65

{

    66

	struct e1000_bus_info *bus = &hw->bus;

    67

	u32 reg;

    68

    69

	/* The status register reports the correct function number

    70

	 * for the device regardless of function swap state.

    71

	 */

    72

	reg = er32(STATUS);

    73

	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

    74

}

    75

    76

/**

    77

 *  e1000_set_lan_id_single_port - Set LAN id for a single port device

    78

 *  @hw: pointer to the HW structure

    79

 *

    80

 *  Sets the LAN function id to zero for a single port device.

    81

 **/

    82

void e1000_set_lan_id_single_port(struct e1000_hw *hw)

    83

{

    84

	struct e1000_bus_info *bus = &hw->bus;

    85

    86

	bus->func = 0;

    87

}

    88

    89

/**

    90

 *  e1000_clear_vfta_generic - Clear VLAN filter table

    91

 *  @hw: pointer to the HW structure

    92

 *

    93

 *  Clears the register array which contains the VLAN filter table by

    94

 *  setting all the values to 0.

    95

 **/

    96

void e1000_clear_vfta_generic(struct e1000_hw *hw)

    97

{

    98

	u32 offset;

    99

   100

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

   101

		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);

   102

		e1e_flush();

   103

	}

   104

}

   105

   106

/**

   107

 *  e1000_write_vfta_generic - Write value to VLAN filter table

   108

 *  @hw: pointer to the HW structure

   109

 *  @offset: register offset in VLAN filter table

   110

 *  @value: register value written to VLAN filter table

   111

 *

   112

 *  Writes value at the given offset in the register array which stores

   113

 *  the VLAN filter table.

   114

 **/

   115

void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)

   116

{

   117

	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);

   118

	e1e_flush();

   119

}

   120

   121

/**

   122

 *  e1000e_init_rx_addrs - Initialize receive address's

   123

 *  @hw: pointer to the HW structure

   124

 *  @rar_count: receive address registers

   125

 *

   126

 *  Setup the receive address registers by setting the base receive address

   127

 *  register to the devices MAC address and clearing all the other receive

   128

 *  address registers to 0.

   129

 **/

   130

void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   131

{

   132

	u32 i;

   133

	u8 mac_addr[ETH_ALEN] = { 0 };

   134

   135

	/* Setup the receive address */

   136

	e_dbg("Programming MAC Address into RAR[0]\n");

   137

   138

	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);

   139

   140

	/* Zero out the other (rar_entry_count - 1) receive addresses */

   141

	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);

   142

	for (i = 1; i < rar_count; i++)

   143

		hw->mac.ops.rar_set(hw, mac_addr, i);

   144

}

   145

   146

/**

   147

 *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr

   148

 *  @hw: pointer to the HW structure

   149

 *

   150

 *  Checks the nvm for an alternate MAC address.  An alternate MAC address

   151

 *  can be setup by pre-boot software and must be treated like a permanent

   152

 *  address and must override the actual permanent MAC address. If an

   153

 *  alternate MAC address is found it is programmed into RAR0, replacing

   154

 *  the permanent address that was installed into RAR0 by the Si on reset.

   155

 *  This function will return SUCCESS unless it encounters an error while

   156

 *  reading the EEPROM.

   157

 **/

   158

s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)

   159

{

   160

	u32 i;

   161

	s32 ret_val;

   162

	u16 offset, nvm_alt_mac_addr_offset, nvm_data;

   163

	u8 alt_mac_addr[ETH_ALEN];

   164

   165

	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);

   166

	if (ret_val)

   167

		return ret_val;

   168

   169

	/* not supported on 82573 */

   170

	if (hw->mac.type == e1000_82573)

   171

		return 0;

   172

   173

	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,

   174

				 &nvm_alt_mac_addr_offset);

   175

	if (ret_val) {

   176

		e_dbg("NVM Read Error\n");

   177

		return ret_val;

   178

	}

   179

   180

	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||

   181

	    (nvm_alt_mac_addr_offset == 0x0000))

   182

		/* There is no Alternate MAC Address */

   183

		return 0;

   184

   185

	if (hw->bus.func == E1000_FUNC_1)

   186

		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;

   187

	for (i = 0; i < ETH_ALEN; i += 2) {

   188

		offset = nvm_alt_mac_addr_offset + (i >> 1);

   189

		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);

   190

		if (ret_val) {

   191

			e_dbg("NVM Read Error\n");

   192

			return ret_val;

   193

		}

   194

   195

		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);

   196

		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);

   197

	}

   198

   199

	/* if multicast bit is set, the alternate address will not be used */

   200

	if (is_multicast_ether_addr(alt_mac_addr)) {

   201

		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");

   202

		return 0;

   203

	}

   204

   205

	/* We have a valid alternate MAC address, and we want to treat it the

   206

	 * same as the normal permanent MAC address stored by the HW into the

   207

	 * RAR. Do this by mapping this address into RAR0.

   208

	 */

   209

	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);

   210

   211

	return 0;

   212

}

   213

   214

u32 e1000e_rar_get_count_generic(struct e1000_hw *hw)

   215

{

   216

	return hw->mac.rar_entry_count;

   217

}

   218

   219

/**

   220

 *  e1000e_rar_set_generic - Set receive address register

   221

 *  @hw: pointer to the HW structure

   222

 *  @addr: pointer to the receive address

   223

 *  @index: receive address array register

   224

 *

   225

 *  Sets the receive address array register at index to the address passed

   226

 *  in by addr.

   227

 **/

   228

int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)

   229

{

   230

	u32 rar_low, rar_high;

   231

   232

	/* HW expects these in little endian so we reverse the byte order

   233

	 * from network order (big endian) to little endian

   234

	 */

   235

	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |

   236

		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));

   237

   238

	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));

   239

   240

	/* If MAC address zero, no need to set the AV bit */

   241

	if (rar_low || rar_high)

   242

		rar_high |= E1000_RAH_AV;

   243

   244

	/* Some bridges will combine consecutive 32-bit writes into

   245

	 * a single burst write, which will malfunction on some parts.

   246

	 * The flushes avoid this.

   247

	 */

   248

	ew32(RAL(index), rar_low);

   249

	e1e_flush();

   250

	ew32(RAH(index), rar_high);

   251

	e1e_flush();

   252

   253

	return 0;

   254

}

   255

   256

/**

   257

 *  e1000_hash_mc_addr - Generate a multicast hash value

   258

 *  @hw: pointer to the HW structure

   259

 *  @mc_addr: pointer to a multicast address

   260

 *

   261

 *  Generates a multicast address hash value which is used to determine

   262

 *  the multicast filter table array address and new table value.

   263

 **/

   264

static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   265

{

   266

	u32 hash_value, hash_mask;

   267

	u8 bit_shift = 0;

   268

   269

	/* Register count multiplied by bits per register */

   270

	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   271

   272

	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts

   273

	 * where 0xFF would still fall within the hash mask.

   274

	 */

   275

	while (hash_mask >> bit_shift != 0xFF)

   276

		bit_shift++;

   277

   278

	/* The portion of the address that is used for the hash table

   279

	 * is determined by the mc_filter_type setting.

   280

	 * The algorithm is such that there is a total of 8 bits of shifting.

   281

	 * The bit_shift for a mc_filter_type of 0 represents the number of

   282

	 * left-shifts where the MSB of mc_addr[5] would still fall within

   283

	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   284

	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   285

	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   286

	 * cases are a variation of this algorithm...essentially raising the

   287

	 * number of bits to shift mc_addr[5] left, while still keeping the

   288

	 * 8-bit shifting total.

   289

	 *

   290

	 * For example, given the following Destination MAC Address and an

   291

	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   292

	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   293

	 * values resulting from each mc_filter_type...

   294

	 * [0] [1] [2] [3] [4] [5]

   295

	 * 01  AA  00  12  34  56

   296

	 * LSB           MSB

   297

	 *

   298

	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   299

	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   300

	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   301

	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   302

	 */

   303

	switch (hw->mac.mc_filter_type) {

   304

	default:

   305

	case 0:

   306

		break;

   307

	case 1:

   308

		bit_shift += 1;

   309

		break;

   310

	case 2:

   311

		bit_shift += 2;

   312

		break;

   313

	case 3:

   314

		bit_shift += 4;

   315

		break;

   316

	}

   317

   318

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   319

				   (((u16)mc_addr[5]) << bit_shift)));

   320

   321

	return hash_value;

   322

}

   323

   324

/**

   325

 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses

   326

 *  @hw: pointer to the HW structure

   327

 *  @mc_addr_list: array of multicast addresses to program

   328

 *  @mc_addr_count: number of multicast addresses to program

   329

 *

   330

 *  Updates entire Multicast Table Array.

   331

 *  The caller must have a packed mc_addr_list of multicast addresses.

   332

 **/

   333

void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,

   334

					u8 *mc_addr_list, u32 mc_addr_count)

   335

{

   336

	u32 hash_value, hash_bit, hash_reg;

   337

	int i;

   338

   339

	/* clear mta_shadow */

   340

	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

   341

   342

	/* update mta_shadow from mc_addr_list */

   343

	for (i = 0; (u32)i < mc_addr_count; i++) {

   344

		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);

   345

   346

		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   347

		hash_bit = hash_value & 0x1F;

   348

   349

		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);

   350

		mc_addr_list += (ETH_ALEN);

   351

	}

   352

   353

	/* replace the entire MTA table */

   354

	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)

   355

		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);

   356

	e1e_flush();

   357

}

   358

   359

/**

   360

 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters

   361

 *  @hw: pointer to the HW structure

   362

 *

   363

 *  Clears the base hardware counters by reading the counter registers.

   364

 **/

   365

void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)

   366

{

   367

	er32(CRCERRS);

   368

	er32(SYMERRS);

   369

	er32(MPC);

   370

	er32(SCC);

   371

	er32(ECOL);

   372

	er32(MCC);

   373

	er32(LATECOL);

   374

	er32(COLC);

   375

	er32(DC);

   376

	er32(SEC);

   377

	er32(RLEC);

   378

	er32(XONRXC);

   379

	er32(XONTXC);

   380

	er32(XOFFRXC);

   381

	er32(XOFFTXC);

   382

	er32(FCRUC);

   383

	er32(GPRC);

   384

	er32(BPRC);

   385

	er32(MPRC);

   386

	er32(GPTC);

   387

	er32(GORCL);

   388

	er32(GORCH);

   389

	er32(GOTCL);

   390

	er32(GOTCH);

   391

	er32(RNBC);

   392

	er32(RUC);

   393

	er32(RFC);

   394

	er32(ROC);

   395

	er32(RJC);

   396

	er32(TORL);

   397

	er32(TORH);

   398

	er32(TOTL);

   399

	er32(TOTH);

   400

	er32(TPR);

   401

	er32(TPT);

   402

	er32(MPTC);

   403

	er32(BPTC);

   404

}

   405

   406

/**

   407

 *  e1000e_check_for_copper_link - Check for link (Copper)

   408

 *  @hw: pointer to the HW structure

   409

 *

   410

 *  Checks to see of the link status of the hardware has changed.  If a

   411

 *  change in link status has been detected, then we read the PHY registers

   412

 *  to get the current speed/duplex if link exists.

   413

 **/

   414

s32 e1000e_check_for_copper_link(struct e1000_hw *hw)

   415

{

   416

	struct e1000_mac_info *mac = &hw->mac;

   417

	s32 ret_val;

   418

	bool link;

   419

   420

	/* We only want to go out to the PHY registers to see if Auto-Neg

   421

	 * has completed and/or if our link status has changed.  The

   422

	 * get_link_status flag is set upon receiving a Link Status

   423

	 * Change or Rx Sequence Error interrupt.

   424

	 */

   425

	if (!mac->get_link_status)

   426

		return 0;

   427

   428

	/* First we want to see if the MII Status Register reports

   429

	 * link.  If so, then we want to get the current speed/duplex

   430

	 * of the PHY.

   431

	 */

   432

	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   433

	if (ret_val)

   434

		return ret_val;

   435

   436

	if (!link)

   437

		return 0;	/* No link detected */

   438

   439

	mac->get_link_status = false;

   440

   441

	/* Check if there was DownShift, must be checked

   442

	 * immediately after link-up

   443

	 */

   444

	e1000e_check_downshift(hw);

   445

   446

	/* If we are forcing speed/duplex, then we simply return since

   447

	 * we have already determined whether we have link or not.

   448

	 */

   449

	if (!mac->autoneg)

   450

		return -E1000_ERR_CONFIG;

   451

   452

	/* Auto-Neg is enabled.  Auto Speed Detection takes care

   453

	 * of MAC speed/duplex configuration.  So we only need to

   454

	 * configure Collision Distance in the MAC.

   455

	 */

   456

	mac->ops.config_collision_dist(hw);

   457

   458

	/* Configure Flow Control now that Auto-Neg has completed.

   459

	 * First, we need to restore the desired flow control

   460

	 * settings because we may have had to re-autoneg with a

   461

	 * different link partner.

   462

	 */

   463

	ret_val = e1000e_config_fc_after_link_up(hw);

   464

	if (ret_val)

   465

		e_dbg("Error configuring flow control\n");

   466

   467

	return ret_val;

   468

}

   469

   470

/**

   471

 *  e1000e_check_for_fiber_link - Check for link (Fiber)

   472

 *  @hw: pointer to the HW structure

   473

 *

   474

 *  Checks for link up on the hardware.  If link is not up and we have

   475

 *  a signal, then we need to force link up.

   476

 **/

   477

s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)

   478

{

   479

	struct e1000_mac_info *mac = &hw->mac;

   480

	u32 rxcw;

   481

	u32 ctrl;

   482

	u32 status;

   483

	s32 ret_val;

   484

   485

	ctrl = er32(CTRL);

   486

	status = er32(STATUS);

   487

	rxcw = er32(RXCW);

   488

   489

	/* If we don't have link (auto-negotiation failed or link partner

   490

	 * cannot auto-negotiate), the cable is plugged in (we have signal),

   491

	 * and our link partner is not trying to auto-negotiate with us (we

   492

	 * are receiving idles or data), we need to force link up. We also

   493

	 * need to give auto-negotiation time to complete, in case the cable

   494

	 * was just plugged in. The autoneg_failed flag does this.

   495

	 */

   496

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   497

	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&

   498

	    !(rxcw & E1000_RXCW_C)) {

   499

		if (!mac->autoneg_failed) {

   500

			mac->autoneg_failed = true;

   501

			return 0;

   502

		}

   503

		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");

   504

   505

		/* Disable auto-negotiation in the TXCW register */

   506

		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   507

   508

		/* Force link-up and also force full-duplex. */

   509

		ctrl = er32(CTRL);

   510

		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   511

		ew32(CTRL, ctrl);

   512

   513

		/* Configure Flow Control after forcing link up. */

   514

		ret_val = e1000e_config_fc_after_link_up(hw);

   515

		if (ret_val) {

   516

			e_dbg("Error configuring flow control\n");

   517

			return ret_val;

   518

		}

   519

	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

   520

		/* If we are forcing link and we are receiving /C/ ordered

   521

		 * sets, re-enable auto-negotiation in the TXCW register

   522

		 * and disable forced link in the Device Control register

   523

		 * in an attempt to auto-negotiate with our link partner.

   524

		 */

   525

		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");

   526

		ew32(TXCW, mac->txcw);

   527

		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

   528

   529

		mac->serdes_has_link = true;