1

/* Intel PRO/1000 Linux driver

     2

 * Copyright(c) 1999 - 2014 Intel Corporation.

     3

 *

     4

 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

     8

 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

    13

 * The full GNU General Public License is included in this distribution in

    14

 * the file called "COPYING".

    15

 *

    16

 * Contact Information:

    17

 * Linux NICS <linux.nics@intel.com>

    18

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    19

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    20

 */

    21

    22

/* 82562G 10/100 Network Connection

    23

 * 82562G-2 10/100 Network Connection

    24

 * 82562GT 10/100 Network Connection

    25

 * 82562GT-2 10/100 Network Connection

    26

 * 82562V 10/100 Network Connection

    27

 * 82562V-2 10/100 Network Connection

    28

 * 82566DC-2 Gigabit Network Connection

    29

 * 82566DC Gigabit Network Connection

    30

 * 82566DM-2 Gigabit Network Connection

    31

 * 82566DM Gigabit Network Connection

    32

 * 82566MC Gigabit Network Connection

    33

 * 82566MM Gigabit Network Connection

    34

 * 82567LM Gigabit Network Connection

    35

 * 82567LF Gigabit Network Connection

    36

 * 82567V Gigabit Network Connection

    37

 * 82567LM-2 Gigabit Network Connection

    38

 * 82567LF-2 Gigabit Network Connection

    39

 * 82567V-2 Gigabit Network Connection

    40

 * 82567LF-3 Gigabit Network Connection

    41

 * 82567LM-3 Gigabit Network Connection

    42

 * 82567LM-4 Gigabit Network Connection

    43

 * 82577LM Gigabit Network Connection

    44

 * 82577LC Gigabit Network Connection

    45

 * 82578DM Gigabit Network Connection

    46

 * 82578DC Gigabit Network Connection

    47

 * 82579LM Gigabit Network Connection

    48

 * 82579V Gigabit Network Connection

    49

 * Ethernet Connection I217-LM

    50

 * Ethernet Connection I217-V

    51

 * Ethernet Connection I218-V

    52

 * Ethernet Connection I218-LM

    53

 * Ethernet Connection (2) I218-LM

    54

 * Ethernet Connection (2) I218-V

    55

 * Ethernet Connection (3) I218-LM

    56

 * Ethernet Connection (3) I218-V

    57

 */

    58

    59

#include "e1000.h"

    60

    61

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

    62

/* Offset 04h HSFSTS */

    63

union ich8_hws_flash_status {

    64

	struct ich8_hsfsts {

    65

		u16 flcdone:1;	/* bit 0 Flash Cycle Done */

    66

		u16 flcerr:1;	/* bit 1 Flash Cycle Error */

    67

		u16 dael:1;	/* bit 2 Direct Access error Log */

    68

		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */

    69

		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */

    70

		u16 reserved1:2;	/* bit 13:6 Reserved */

    71

		u16 reserved2:6;	/* bit 13:6 Reserved */

    72

		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */

    73

		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */

    74

	} hsf_status;

    75

	u16 regval;

    76

};

    77

    78

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

    79

/* Offset 06h FLCTL */

    80

union ich8_hws_flash_ctrl {

    81

	struct ich8_hsflctl {

    82

		u16 flcgo:1;	/* 0 Flash Cycle Go */

    83

		u16 flcycle:2;	/* 2:1 Flash Cycle */

    84

		u16 reserved:5;	/* 7:3 Reserved  */

    85

		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */

    86

		u16 flockdn:6;	/* 15:10 Reserved */

    87

	} hsf_ctrl;

    88

	u16 regval;

    89

};

    90

    91

/* ICH Flash Region Access Permissions */

    92

union ich8_hws_flash_regacc {

    93

	struct ich8_flracc {

    94

		u32 grra:8;	/* 0:7 GbE region Read Access */

    95

		u32 grwa:8;	/* 8:15 GbE region Write Access */

    96

		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */

    97

		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */

    98

	} hsf_flregacc;

    99

	u16 regval;

   100

};

   101

   102

/* ICH Flash Protected Region */

   103

union ich8_flash_protected_range {

   104

	struct ich8_pr {

   105

		u32 base:13;	/* 0:12 Protected Range Base */

   106

		u32 reserved1:2;	/* 13:14 Reserved */

   107

		u32 rpe:1;	/* 15 Read Protection Enable */

   108

		u32 limit:13;	/* 16:28 Protected Range Limit */

   109

		u32 reserved2:2;	/* 29:30 Reserved */

   110

		u32 wpe:1;	/* 31 Write Protection Enable */

   111

	} range;

   112

	u32 regval;

   113

};

   114

   115

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   116

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   117

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   118

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   119

						u32 offset, u8 byte);

   120

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   121

					 u8 *data);

   122

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   123

					 u16 *data);

   124

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   125

					 u8 size, u16 *data);

   126

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   127

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   128

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   129

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   130

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   131

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   132

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   133

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   134

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   135

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   136

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   137

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   138

static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   139

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   140

static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   141

static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   142

static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

   143

static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

   144

static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);

   145

static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   146

static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   147

static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);

   148

static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);

   149

static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);

   150

   151

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   152

{

   153

	return readw(hw->flash_address + reg);

   154

}

   155

   156

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   157

{

   158

	return readl(hw->flash_address + reg);

   159

}

   160

   161

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   162

{

   163

	writew(val, hw->flash_address + reg);

   164

}

   165

   166

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   167

{

   168

	writel(val, hw->flash_address + reg);

   169

}

   170

   171

#define er16flash(reg)		__er16flash(hw, (reg))

   172

#define er32flash(reg)		__er32flash(hw, (reg))

   173

#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

   174

#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   175

   176

/**

   177

 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers

   178

 *  @hw: pointer to the HW structure

   179

 *

   180

 *  Test access to the PHY registers by reading the PHY ID registers.  If

   181

 *  the PHY ID is already known (e.g. resume path) compare it with known ID,

   182

 *  otherwise assume the read PHY ID is correct if it is valid.

   183

 *

   184

 *  Assumes the sw/fw/hw semaphore is already acquired.

   185

 **/

   186

static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)

   187

{

   188

	u16 phy_reg = 0;

   189

	u32 phy_id = 0;

   190

	s32 ret_val = 0;

   191

	u16 retry_count;

   192

	u32 mac_reg = 0;

   193

   194

	for (retry_count = 0; retry_count < 2; retry_count++) {

   195

		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);

   196

		if (ret_val || (phy_reg == 0xFFFF))

   197

			continue;

   198

		phy_id = (u32)(phy_reg << 16);

   199

   200

		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);

   201

		if (ret_val || (phy_reg == 0xFFFF)) {

   202

			phy_id = 0;

   203

			continue;

   204

		}

   205

		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

   206

		break;

   207

	}

   208

   209

	if (hw->phy.id) {

   210

		if (hw->phy.id == phy_id)

   211

			goto out;

   212

	} else if (phy_id) {

   213

		hw->phy.id = phy_id;

   214

		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

   215

		goto out;

   216

	}

   217

   218

	/* In case the PHY needs to be in mdio slow mode,

   219

	 * set slow mode and try to get the PHY id again.

   220

	 */

   221

	if (hw->mac.type < e1000_pch_lpt) {

   222

		hw->phy.ops.release(hw);

   223

		ret_val = e1000_set_mdio_slow_mode_hv(hw);

   224

		if (!ret_val)

   225

			ret_val = e1000e_get_phy_id(hw);

   226

		hw->phy.ops.acquire(hw);

   227

	}

   228

   229

	if (ret_val)

   230

		return false;

   231

out:

   232

	if (hw->mac.type == e1000_pch_lpt) {

   233

		/* Unforce SMBus mode in PHY */

   234

		e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);

   235

		phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;

   236

		e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

   237

   238

		/* Unforce SMBus mode in MAC */

   239

		mac_reg = er32(CTRL_EXT);

   240

		mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   241

		ew32(CTRL_EXT, mac_reg);

   242

	}

   243

   244

	return true;

   245

}

   246

   247

/**

   248

 *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value

   249

 *  @hw: pointer to the HW structure

   250

 *

   251

 *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is

   252

 *  used to reset the PHY to a quiescent state when necessary.

   253

 **/

   254

static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)

   255

{

   256

	u32 mac_reg;

   257

   258

	/* Set Phy Config Counter to 50msec */

   259

	mac_reg = er32(FEXTNVM3);

   260

	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

   261

	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

   262

	ew32(FEXTNVM3, mac_reg);

   263

   264

	/* Toggle LANPHYPC Value bit */

   265

	mac_reg = er32(CTRL);

   266

	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;

   267

	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

   268

	ew32(CTRL, mac_reg);

   269

	e1e_flush();

   270

	usleep_range(10, 20);

   271

	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   272

	ew32(CTRL, mac_reg);

   273

	e1e_flush();

   274

   275

	if (hw->mac.type < e1000_pch_lpt) {

   276

		msleep(50);

   277

	} else {

   278

		u16 count = 20;

   279

   280

		do {

   281

			usleep_range(5000, 10000);

   282

		} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);

   283

   284

		msleep(30);

   285

	}

   286

}

   287

   288

/**

   289

 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds

   290

 *  @hw: pointer to the HW structure

   291

 *

   292

 *  Workarounds/flow necessary for PHY initialization during driver load

   293

 *  and resume paths.

   294

 **/

   295

static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

   296

{

   297

	struct e1000_adapter *adapter = hw->adapter;

   298

	u32 mac_reg, fwsm = er32(FWSM);

   299

	s32 ret_val;

   300

   301

	/* Gate automatic PHY configuration by hardware on managed and

   302

	 * non-managed 82579 and newer adapters.

   303

	 */

   304

	e1000_gate_hw_phy_config_ich8lan(hw, true);

   305

   306

	/* It is not possible to be certain of the current state of ULP

   307

	 * so forcibly disable it.

   308

	 */

   309

	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;

   310

	e1000_disable_ulp_lpt_lp(hw, true);

   311

   312

	ret_val = hw->phy.ops.acquire(hw);

   313

	if (ret_val) {

   314

		e_dbg("Failed to initialize PHY flow\n");

   315

		goto out;

   316

	}

   317

   318

	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is

   319

	 * inaccessible and resetting the PHY is not blocked, toggle the

   320

	 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   321

	 */

   322

	switch (hw->mac.type) {

   323

	case e1000_pch_lpt:

   324

		if (e1000_phy_is_accessible_pchlan(hw))

   325

			break;

   326

   327

		/* Before toggling LANPHYPC, see if PHY is accessible by

   328

		 * forcing MAC to SMBus mode first.

   329

		 */

   330

		mac_reg = er32(CTRL_EXT);

   331

		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

   332

		ew32(CTRL_EXT, mac_reg);

   333

   334

		/* Wait 50 milliseconds for MAC to finish any retries

   335

		 * that it might be trying to perform from previous

   336

		 * attempts to acknowledge any phy read requests.

   337

		 */

   338

		msleep(50);

   339

   340

		/* fall-through */

   341

	case e1000_pch2lan:

   342

		if (e1000_phy_is_accessible_pchlan(hw))

   343

			break;

   344

   345

		/* fall-through */

   346

	case e1000_pchlan:

   347

		if ((hw->mac.type == e1000_pchlan) &&

   348

		    (fwsm & E1000_ICH_FWSM_FW_VALID))

   349

			break;

   350

   351

		if (hw->phy.ops.check_reset_block(hw)) {

   352

			e_dbg("Required LANPHYPC toggle blocked by ME\n");

   353

			ret_val = -E1000_ERR_PHY;

   354

			break;

   355

		}

   356

   357

		/* Toggle LANPHYPC Value bit */

   358

		e1000_toggle_lanphypc_pch_lpt(hw);

   359

		if (hw->mac.type >= e1000_pch_lpt) {

   360

			if (e1000_phy_is_accessible_pchlan(hw))

   361

				break;

   362

   363

			/* Toggling LANPHYPC brings the PHY out of SMBus mode

   364

			 * so ensure that the MAC is also out of SMBus mode

   365

			 */

   366

			mac_reg = er32(CTRL_EXT);

   367

			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   368

			ew32(CTRL_EXT, mac_reg);

   369

   370

			if (e1000_phy_is_accessible_pchlan(hw))

   371

				break;

   372

   373

			ret_val = -E1000_ERR_PHY;

   374

		}

   375

		break;

   376

	default:

   377

		break;

   378

	}

   379

   380

	hw->phy.ops.release(hw);

   381

	if (!ret_val) {

   382

   383

		/* Check to see if able to reset PHY.  Print error if not */

   384

		if (hw->phy.ops.check_reset_block(hw)) {

   385

			e_err("Reset blocked by ME\n");

   386

			goto out;

   387

		}

   388

   389

		/* Reset the PHY before any access to it.  Doing so, ensures

   390

		 * that the PHY is in a known good state before we read/write

   391

		 * PHY registers.  The generic reset is sufficient here,

   392

		 * because we haven't determined the PHY type yet.

   393

		 */

   394

		ret_val = e1000e_phy_hw_reset_generic(hw);

   395

		if (ret_val)

   396

			goto out;

   397

   398

		/* On a successful reset, possibly need to wait for the PHY

   399

		 * to quiesce to an accessible state before returning control

   400

		 * to the calling function.  If the PHY does not quiesce, then

   401

		 * return E1000E_BLK_PHY_RESET, as this is the condition that

   402

		 *  the PHY is in.

   403

		 */

   404

		ret_val = hw->phy.ops.check_reset_block(hw);

   405

		if (ret_val)

   406

			e_err("ME blocked access to PHY after reset\n");

   407

	}

   408

   409

out:

   410

	/* Ungate automatic PHY configuration on non-managed 82579 */

   411

	if ((hw->mac.type == e1000_pch2lan) &&

   412

	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   413

		usleep_range(10000, 20000);

   414

		e1000_gate_hw_phy_config_ich8lan(hw, false);

   415

	}

   416

   417

	return ret_val;

   418

}

   419

   420

/**

   421

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   422

 *  @hw: pointer to the HW structure

   423

 *

   424

 *  Initialize family-specific PHY parameters and function pointers.

   425

 **/

   426

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   427

{

   428

	struct e1000_phy_info *phy = &hw->phy;

   429

	s32 ret_val;

   430

   431

	phy->addr = 1;

   432

	phy->reset_delay_us = 100;

   433

   434

	phy->ops.set_page = e1000_set_page_igp;

   435

	phy->ops.read_reg = e1000_read_phy_reg_hv;

   436

	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;

   437

	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;

   438

	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;

   439

	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;

   440

	phy->ops.write_reg = e1000_write_phy_reg_hv;

   441

	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;

   442

	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;

   443

	phy->ops.power_up = e1000_power_up_phy_copper;

   444

	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

   445

	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   446

   447

	phy->id = e1000_phy_unknown;

   448

   449

	ret_val = e1000_init_phy_workarounds_pchlan(hw);

   450

	if (ret_val)

   451

		return ret_val;

   452

   453

	if (phy->id == e1000_phy_unknown)

   454

		switch (hw->mac.type) {

   455

		default:

   456

			ret_val = e1000e_get_phy_id(hw);

   457

			if (ret_val)

   458

				return ret_val;

   459

			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   460

				break;

   461

			/* fall-through */

   462

		case e1000_pch2lan:

   463

		case e1000_pch_lpt:

   464

			/* In case the PHY needs to be in mdio slow mode,

   465

			 * set slow mode and try to get the PHY id again.

   466

			 */

   467

			ret_val = e1000_set_mdio_slow_mode_hv(hw);

   468

			if (ret_val)

   469

				return ret_val;

   470

			ret_val = e1000e_get_phy_id(hw);

   471

			if (ret_val)

   472

				return ret_val;

   473

			break;

   474

		}

   475

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   476

   477

	switch (phy->type) {

   478

	case e1000_phy_82577:

   479

	case e1000_phy_82579:

   480

	case e1000_phy_i217:

   481

		phy->ops.check_polarity = e1000_check_polarity_82577;

   482

		phy->ops.force_speed_duplex =

   483

		    e1000_phy_force_speed_duplex_82577;

   484

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   485

		phy->ops.get_info = e1000_get_phy_info_82577;

   486

		phy->ops.commit = e1000e_phy_sw_reset;

   487

		break;

   488

	case e1000_phy_82578:

   489

		phy->ops.check_polarity = e1000_check_polarity_m88;

   490

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   491

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   492

		phy->ops.get_info = e1000e_get_phy_info_m88;

   493

		break;

   494

	default:

   495

		ret_val = -E1000_ERR_PHY;

   496

		break;

   497

	}

   498

   499

	return ret_val;

   500

}

   501

   502

/**

   503

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   504

 *  @hw: pointer to the HW structure

   505

 *

   506

 *  Initialize family-specific PHY parameters and function pointers.

   507

 **/

   508

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   509

{

   510

	struct e1000_phy_info *phy = &hw->phy;

   511

	s32 ret_val;

   512

	u16 i = 0;

   513

   514

	phy->addr = 1;

   515

	phy->reset_delay_us = 100;

   516

   517

	phy->ops.power_up = e1000_power_up_phy_copper;

   518

	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

   519

   520

	/* We may need to do this twice - once for IGP and if that fails,

   521

	 * we'll set BM func pointers and try again

   522

	 */

   523

	ret_val = e1000e_determine_phy_address(hw);

   524

	if (ret_val) {

   525

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   526

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   527

		ret_val = e1000e_determine_phy_address(hw);

   528

		if (ret_val) {

   529

			e_dbg("Cannot determine PHY addr. Erroring out\n");