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/*******************************************************************************

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     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2013 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

/* 82562G 10/100 Network Connection

    30

 * 82562G-2 10/100 Network Connection

    31

 * 82562GT 10/100 Network Connection

    32

 * 82562GT-2 10/100 Network Connection

    33

 * 82562V 10/100 Network Connection

    34

 * 82562V-2 10/100 Network Connection

    35

 * 82566DC-2 Gigabit Network Connection

    36

 * 82566DC Gigabit Network Connection

    37

 * 82566DM-2 Gigabit Network Connection

    38

 * 82566DM Gigabit Network Connection

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 * 82566MC Gigabit Network Connection

    40

 * 82566MM Gigabit Network Connection

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 * 82567LM Gigabit Network Connection

    42

 * 82567LF Gigabit Network Connection

    43

 * 82567V Gigabit Network Connection

    44

 * 82567LM-2 Gigabit Network Connection

    45

 * 82567LF-2 Gigabit Network Connection

    46

 * 82567V-2 Gigabit Network Connection

    47

 * 82567LF-3 Gigabit Network Connection

    48

 * 82567LM-3 Gigabit Network Connection

    49

 * 82567LM-4 Gigabit Network Connection

    50

 * 82577LM Gigabit Network Connection

    51

 * 82577LC Gigabit Network Connection

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 * 82578DM Gigabit Network Connection

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 * 82578DC Gigabit Network Connection

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 * 82579LM Gigabit Network Connection

    55

 * 82579V Gigabit Network Connection

    56

 */

    57

    58

#include "e1000-3.12-ethercat.h"

    59

    60

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

    61

/* Offset 04h HSFSTS */

    62

union ich8_hws_flash_status {

    63

	struct ich8_hsfsts {

    64

		u16 flcdone:1;	/* bit 0 Flash Cycle Done */

    65

		u16 flcerr:1;	/* bit 1 Flash Cycle Error */

    66

		u16 dael:1;	/* bit 2 Direct Access error Log */

    67

		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */

    68

		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */

    69

		u16 reserved1:2;	/* bit 13:6 Reserved */

    70

		u16 reserved2:6;	/* bit 13:6 Reserved */

    71

		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */

    72

		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */

    73

	} hsf_status;

    74

	u16 regval;

    75

};

    76

    77

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

    78

/* Offset 06h FLCTL */

    79

union ich8_hws_flash_ctrl {

    80

	struct ich8_hsflctl {

    81

		u16 flcgo:1;	/* 0 Flash Cycle Go */

    82

		u16 flcycle:2;	/* 2:1 Flash Cycle */

    83

		u16 reserved:5;	/* 7:3 Reserved  */

    84

		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */

    85

		u16 flockdn:6;	/* 15:10 Reserved */

    86

	} hsf_ctrl;

    87

	u16 regval;

    88

};

    89

    90

/* ICH Flash Region Access Permissions */

    91

union ich8_hws_flash_regacc {

    92

	struct ich8_flracc {

    93

		u32 grra:8;	/* 0:7 GbE region Read Access */

    94

		u32 grwa:8;	/* 8:15 GbE region Write Access */

    95

		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */

    96

		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */

    97

	} hsf_flregacc;

    98

	u16 regval;

    99

};

   100

   101

/* ICH Flash Protected Region */

   102

union ich8_flash_protected_range {

   103

	struct ich8_pr {

   104

		u32 base:13;	/* 0:12 Protected Range Base */

   105

		u32 reserved1:2;	/* 13:14 Reserved */

   106

		u32 rpe:1;	/* 15 Read Protection Enable */

   107

		u32 limit:13;	/* 16:28 Protected Range Limit */

   108

		u32 reserved2:2;	/* 29:30 Reserved */

   109

		u32 wpe:1;	/* 31 Write Protection Enable */

   110

	} range;

   111

	u32 regval;

   112

};

   113

   114

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   115

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   116

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   117

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   118

						u32 offset, u8 byte);

   119

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   120

					 u8 *data);

   121

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   122

					 u16 *data);

   123

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   124

					 u8 size, u16 *data);

   125

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   126

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   127

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   128

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   129

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   130

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   131

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   132

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   133

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   134

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   135

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   136

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   137

static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   138

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   139

static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   140

static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   141

static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

   142

static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

   143

static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   144

static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   145

static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);

   146

   147

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   148

{

   149

	return readw(hw->flash_address + reg);

   150

}

   151

   152

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   153

{

   154

	return readl(hw->flash_address + reg);

   155

}

   156

   157

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   158

{

   159

	writew(val, hw->flash_address + reg);

   160

}

   161

   162

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   163

{

   164

	writel(val, hw->flash_address + reg);

   165

}

   166

   167

#define er16flash(reg)		__er16flash(hw, (reg))

   168

#define er32flash(reg)		__er32flash(hw, (reg))

   169

#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

   170

#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   171

   172

/**

   173

 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers

   174

 *  @hw: pointer to the HW structure

   175

 *

   176

 *  Test access to the PHY registers by reading the PHY ID registers.  If

   177

 *  the PHY ID is already known (e.g. resume path) compare it with known ID,

   178

 *  otherwise assume the read PHY ID is correct if it is valid.

   179

 *

   180

 *  Assumes the sw/fw/hw semaphore is already acquired.

   181

 **/

   182

static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)

   183

{

   184

	u16 phy_reg = 0;

   185

	u32 phy_id = 0;

   186

	s32 ret_val;

   187

	u16 retry_count;

   188

	u32 mac_reg = 0;

   189

   190

	for (retry_count = 0; retry_count < 2; retry_count++) {

   191

		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);

   192

		if (ret_val || (phy_reg == 0xFFFF))

   193

			continue;

   194

		phy_id = (u32)(phy_reg << 16);

   195

   196

		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);

   197

		if (ret_val || (phy_reg == 0xFFFF)) {

   198

			phy_id = 0;

   199

			continue;

   200

		}

   201

		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);

   202

		break;

   203

	}

   204

   205

	if (hw->phy.id) {

   206

		if (hw->phy.id == phy_id)

   207

			goto out;

   208

	} else if (phy_id) {

   209

		hw->phy.id = phy_id;

   210

		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);

   211

		goto out;

   212

	}

   213

   214

	/* In case the PHY needs to be in mdio slow mode,

   215

	 * set slow mode and try to get the PHY id again.

   216

	 */

   217

	hw->phy.ops.release(hw);

   218

	ret_val = e1000_set_mdio_slow_mode_hv(hw);

   219

	if (!ret_val)

   220

		ret_val = e1000e_get_phy_id(hw);

   221

	hw->phy.ops.acquire(hw);

   222

   223

	if (ret_val)

   224

		return false;

   225

out:

   226

	if (hw->mac.type == e1000_pch_lpt) {

   227

		/* Unforce SMBus mode in PHY */

   228

		e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);

   229

		phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;

   230

		e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

   231

   232

		/* Unforce SMBus mode in MAC */

   233

		mac_reg = er32(CTRL_EXT);

   234

		mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   235

		ew32(CTRL_EXT, mac_reg);

   236

	}

   237

   238

	return true;

   239

}

   240

   241

/**

   242

 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds

   243

 *  @hw: pointer to the HW structure

   244

 *

   245

 *  Workarounds/flow necessary for PHY initialization during driver load

   246

 *  and resume paths.

   247

 **/

   248

static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)

   249

{

   250

	u32 mac_reg, fwsm = er32(FWSM);

   251

	s32 ret_val;

   252

   253

	/* Gate automatic PHY configuration by hardware on managed and

   254

	 * non-managed 82579 and newer adapters.

   255

	 */

   256

	e1000_gate_hw_phy_config_ich8lan(hw, true);

   257

   258

	ret_val = hw->phy.ops.acquire(hw);

   259

	if (ret_val) {

   260

		e_dbg("Failed to initialize PHY flow\n");

   261

		goto out;

   262

	}

   263

   264

	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is

   265

	 * inaccessible and resetting the PHY is not blocked, toggle the

   266

	 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   267

	 */

   268

	switch (hw->mac.type) {

   269

	case e1000_pch_lpt:

   270

		if (e1000_phy_is_accessible_pchlan(hw))

   271

			break;

   272

   273

		/* Before toggling LANPHYPC, see if PHY is accessible by

   274

		 * forcing MAC to SMBus mode first.

   275

		 */

   276

		mac_reg = er32(CTRL_EXT);

   277

		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;

   278

		ew32(CTRL_EXT, mac_reg);

   279

   280

		/* Wait 50 milliseconds for MAC to finish any retries

   281

		 * that it might be trying to perform from previous

   282

		 * attempts to acknowledge any phy read requests.

   283

		 */

   284

		msleep(50);

   285

   286

		/* fall-through */

   287

	case e1000_pch2lan:

   288

		if (e1000_phy_is_accessible_pchlan(hw))

   289

			break;

   290

   291

		/* fall-through */

   292

	case e1000_pchlan:

   293

		if ((hw->mac.type == e1000_pchlan) &&

   294

		    (fwsm & E1000_ICH_FWSM_FW_VALID))

   295

			break;

   296

   297

		if (hw->phy.ops.check_reset_block(hw)) {

   298

			e_dbg("Required LANPHYPC toggle blocked by ME\n");

   299

			ret_val = -E1000_ERR_PHY;

   300

			break;

   301

		}

   302

   303

		e_dbg("Toggling LANPHYPC\n");

   304

   305

		/* Set Phy Config Counter to 50msec */

   306

		mac_reg = er32(FEXTNVM3);

   307

		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

   308

		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

   309

		ew32(FEXTNVM3, mac_reg);

   310

   311

		/* Toggle LANPHYPC Value bit */

   312

		mac_reg = er32(CTRL);

   313

		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;

   314

		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

   315

		ew32(CTRL, mac_reg);

   316

		e1e_flush();

   317

		usleep_range(10, 20);

   318

		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   319

		ew32(CTRL, mac_reg);

   320

		e1e_flush();

   321

		if (hw->mac.type < e1000_pch_lpt) {

   322

			msleep(50);

   323

		} else {

   324

			u16 count = 20;

   325

			do {

   326

				usleep_range(5000, 10000);

   327

			} while (!(er32(CTRL_EXT) &

   328

				   E1000_CTRL_EXT_LPCD) && count--);

   329

			usleep_range(30000, 60000);

   330

			if (e1000_phy_is_accessible_pchlan(hw))

   331

				break;

   332

   333

			/* Toggling LANPHYPC brings the PHY out of SMBus mode

   334

			 * so ensure that the MAC is also out of SMBus mode

   335

			 */

   336

			mac_reg = er32(CTRL_EXT);

   337

			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;

   338

			ew32(CTRL_EXT, mac_reg);

   339

   340

			if (e1000_phy_is_accessible_pchlan(hw))

   341

				break;

   342

   343

			ret_val = -E1000_ERR_PHY;

   344

		}

   345

		break;

   346

	default:

   347

		break;

   348

	}

   349

   350

	hw->phy.ops.release(hw);

   351

	if (!ret_val) {

   352

		/* Reset the PHY before any access to it.  Doing so, ensures

   353

		 * that the PHY is in a known good state before we read/write

   354

		 * PHY registers.  The generic reset is sufficient here,

   355

		 * because we haven't determined the PHY type yet.

   356

		 */

   357

		ret_val = e1000e_phy_hw_reset_generic(hw);

   358

	}

   359

   360

out:

   361

	/* Ungate automatic PHY configuration on non-managed 82579 */

   362

	if ((hw->mac.type == e1000_pch2lan) &&

   363

	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   364

		usleep_range(10000, 20000);

   365

		e1000_gate_hw_phy_config_ich8lan(hw, false);

   366

	}

   367

   368

	return ret_val;

   369

}

   370

   371

/**

   372

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   373

 *  @hw: pointer to the HW structure

   374

 *

   375

 *  Initialize family-specific PHY parameters and function pointers.

   376

 **/

   377

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   378

{

   379

	struct e1000_phy_info *phy = &hw->phy;

   380

	s32 ret_val;

   381

   382

	phy->addr = 1;

   383

	phy->reset_delay_us = 100;

   384

   385

	phy->ops.set_page = e1000_set_page_igp;

   386

	phy->ops.read_reg = e1000_read_phy_reg_hv;

   387

	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;

   388

	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;

   389

	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;

   390

	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;

   391

	phy->ops.write_reg = e1000_write_phy_reg_hv;

   392

	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;

   393

	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;

   394

	phy->ops.power_up = e1000_power_up_phy_copper;

   395

	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

   396

	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   397

   398

	phy->id = e1000_phy_unknown;

   399

   400

	ret_val = e1000_init_phy_workarounds_pchlan(hw);

   401

	if (ret_val)

   402

		return ret_val;

   403

   404

	if (phy->id == e1000_phy_unknown)

   405

		switch (hw->mac.type) {

   406

		default:

   407

			ret_val = e1000e_get_phy_id(hw);

   408

			if (ret_val)

   409

				return ret_val;

   410

			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   411

				break;

   412

			/* fall-through */

   413

		case e1000_pch2lan:

   414

		case e1000_pch_lpt:

   415

			/* In case the PHY needs to be in mdio slow mode,

   416

			 * set slow mode and try to get the PHY id again.

   417

			 */

   418

			ret_val = e1000_set_mdio_slow_mode_hv(hw);

   419

			if (ret_val)

   420

				return ret_val;

   421

			ret_val = e1000e_get_phy_id(hw);

   422

			if (ret_val)

   423

				return ret_val;

   424

			break;

   425

		}

   426

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   427

   428

	switch (phy->type) {

   429

	case e1000_phy_82577:

   430

	case e1000_phy_82579:

   431

	case e1000_phy_i217:

   432

		phy->ops.check_polarity = e1000_check_polarity_82577;

   433

		phy->ops.force_speed_duplex =

   434

		    e1000_phy_force_speed_duplex_82577;

   435

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   436

		phy->ops.get_info = e1000_get_phy_info_82577;

   437

		phy->ops.commit = e1000e_phy_sw_reset;

   438

		break;

   439

	case e1000_phy_82578:

   440

		phy->ops.check_polarity = e1000_check_polarity_m88;

   441

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   442

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   443

		phy->ops.get_info = e1000e_get_phy_info_m88;

   444

		break;

   445

	default:

   446

		ret_val = -E1000_ERR_PHY;

   447

		break;

   448

	}

   449

   450

	return ret_val;

   451

}

   452

   453

/**

   454

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   455

 *  @hw: pointer to the HW structure

   456

 *

   457

 *  Initialize family-specific PHY parameters and function pointers.

   458

 **/

   459

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   460

{

   461

	struct e1000_phy_info *phy = &hw->phy;

   462

	s32 ret_val;

   463

	u16 i = 0;

   464

   465

	phy->addr = 1;

   466

	phy->reset_delay_us = 100;

   467

   468

	phy->ops.power_up = e1000_power_up_phy_copper;

   469

	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

   470

   471

	/* We may need to do this twice - once for IGP and if that fails,

   472

	 * we'll set BM func pointers and try again

   473

	 */

   474

	ret_val = e1000e_determine_phy_address(hw);

   475

	if (ret_val) {

   476

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   477

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   478

		ret_val = e1000e_determine_phy_address(hw);

   479

		if (ret_val) {

   480

			e_dbg("Cannot determine PHY addr. Erroring out\n");

   481

			return ret_val;

   482

		}

   483

	}

   484

   485

	phy->id = 0;

   486

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   487

	       (i++ < 100)) {

   488

		usleep_range(1000, 2000);

   489

		ret_val = e1000e_get_phy_id(hw);

   490

		if (ret_val)

   491

			return ret_val;

   492

	}

   493

   494

	/* Verify phy id */

   495

	switch (phy->id) {

   496

	case IGP03E1000_E_PHY_ID:

   497

		phy->type = e1000_phy_igp_3;

   498

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   499

		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   500

		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   501

		phy->ops.get_info = e1000e_get_phy_info_igp;

   502

		phy->ops.check_polarity = e1000_check_polarity_igp;

   503

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   504

		break;

   505

	case IFE_E_PHY_ID:

   506

	case IFE_PLUS_E_PHY_ID:

   507

	case IFE_C_E_PHY_ID:

   508

		phy->type = e1000_phy_ife;

   509

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   510

		phy->ops.get_info = e1000_get_phy_info_ife;

   511

		phy->ops.check_polarity = e1000_check_polarity_ife;

   512

		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   513

		break;

   514

	case BME1000_E_PHY_ID:

   515

		phy->type = e1000_phy_bm;

   516

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   517

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   518

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   519

		phy->ops.commit = e1000e_phy_sw_reset;

   520

		phy->ops.get_info = e1000e_get_phy_info_m88;

   521

		phy->ops.check_polarity = e1000_check_polarity_m88;

   522

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   523

		break;

   524

	default:

   525

		return -E1000_ERR_PHY;

   526

		break;

   527

	}

   528

   529

	return 0;