1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2009 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

/*

    30

 * 82562G 10/100 Network Connection

    31

 * 82562G-2 10/100 Network Connection

    32

 * 82562GT 10/100 Network Connection

    33

 * 82562GT-2 10/100 Network Connection

    34

 * 82562V 10/100 Network Connection

    35

 * 82562V-2 10/100 Network Connection

    36

 * 82566DC-2 Gigabit Network Connection

    37

 * 82566DC Gigabit Network Connection

    38

 * 82566DM-2 Gigabit Network Connection

    39

 * 82566DM Gigabit Network Connection

    40

 * 82566MC Gigabit Network Connection

    41

 * 82566MM Gigabit Network Connection

    42

 * 82567LM Gigabit Network Connection

    43

 * 82567LF Gigabit Network Connection

    44

 * 82567V Gigabit Network Connection

    45

 * 82567LM-2 Gigabit Network Connection

    46

 * 82567LF-2 Gigabit Network Connection

    47

 * 82567V-2 Gigabit Network Connection

    48

 * 82567LF-3 Gigabit Network Connection

    49

 * 82567LM-3 Gigabit Network Connection

    50

 * 82567LM-4 Gigabit Network Connection

    51

 * 82577LM Gigabit Network Connection

    52

 * 82577LC Gigabit Network Connection

    53

 * 82578DM Gigabit Network Connection

    54

 * 82578DC Gigabit Network Connection

    55

 */

    56

    57

#include "e1000.h"

    58

    59

#define ICH_FLASH_GFPREG		0x0000

    60

#define ICH_FLASH_HSFSTS		0x0004

    61

#define ICH_FLASH_HSFCTL		0x0006

    62

#define ICH_FLASH_FADDR			0x0008

    63

#define ICH_FLASH_FDATA0		0x0010

    64

#define ICH_FLASH_PR0			0x0074

    65

    66

#define ICH_FLASH_READ_COMMAND_TIMEOUT	500

    67

#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500

    68

#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000

    69

#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

    70

#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

    71

    72

#define ICH_CYCLE_READ			0

    73

#define ICH_CYCLE_WRITE			2

    74

#define ICH_CYCLE_ERASE			3

    75

    76

#define FLASH_GFPREG_BASE_MASK		0x1FFF

    77

#define FLASH_SECTOR_ADDR_SHIFT		12

    78

    79

#define ICH_FLASH_SEG_SIZE_256		256

    80

#define ICH_FLASH_SEG_SIZE_4K		4096

    81

#define ICH_FLASH_SEG_SIZE_8K		8192

    82

#define ICH_FLASH_SEG_SIZE_64K		65536

    83

    84

    85

#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */

    86

    87

#define E1000_ICH_MNG_IAMT_MODE		0x2

    88

    89

#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \

    90

				 (ID_LED_DEF1_OFF2 <<  8) | \

    91

				 (ID_LED_DEF1_ON2  <<  4) | \

    92

				 (ID_LED_DEF1_DEF2))

    93

    94

#define E1000_ICH_NVM_SIG_WORD		0x13

    95

#define E1000_ICH_NVM_SIG_MASK		0xC000

    96

#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0

    97

#define E1000_ICH_NVM_SIG_VALUE         0x80

    98

    99

#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

   100

   101

#define E1000_FEXTNVM_SW_CONFIG		1

   102

#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

   103

   104

#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL

   105

   106

#define E1000_ICH_RAR_ENTRIES		7

   107

   108

#define PHY_PAGE_SHIFT 5

   109

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

   110

			   ((reg) & MAX_PHY_REG_ADDRESS))

   111

#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */

   112

#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */

   113

   114

#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002

   115

#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

   116

#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200

   117

   118

#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */

   119

   120

#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */

   121

   122

/* SMBus Address Phy Register */

   123

#define HV_SMB_ADDR            PHY_REG(768, 26)

   124

#define HV_SMB_ADDR_PEC_EN     0x0200

   125

#define HV_SMB_ADDR_VALID      0x0080

   126

   127

/* Strapping Option Register - RO */

   128

#define E1000_STRAP                     0x0000C

   129

#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

   130

#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

   131

   132

/* OEM Bits Phy Register */

   133

#define HV_OEM_BITS            PHY_REG(768, 25)

   134

#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */

   135

#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */

   136

#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */

   137

   138

#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */

   139

#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */

   140

   141

/* KMRN Mode Control */

   142

#define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)

   143

#define HV_KMRN_MDIO_SLOW      0x0400

   144

   145

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

   146

/* Offset 04h HSFSTS */

   147

union ich8_hws_flash_status {

   148

	struct ich8_hsfsts {

   149

		u16 flcdone    :1; /* bit 0 Flash Cycle Done */

   150

		u16 flcerr     :1; /* bit 1 Flash Cycle Error */

   151

		u16 dael       :1; /* bit 2 Direct Access error Log */

   152

		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */

   153

		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */

   154

		u16 reserved1  :2; /* bit 13:6 Reserved */

   155

		u16 reserved2  :6; /* bit 13:6 Reserved */

   156

		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */

   157

		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */

   158

	} hsf_status;

   159

	u16 regval;

   160

};

   161

   162

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

   163

/* Offset 06h FLCTL */

   164

union ich8_hws_flash_ctrl {

   165

	struct ich8_hsflctl {

   166

		u16 flcgo      :1;   /* 0 Flash Cycle Go */

   167

		u16 flcycle    :2;   /* 2:1 Flash Cycle */

   168

		u16 reserved   :5;   /* 7:3 Reserved  */

   169

		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */

   170

		u16 flockdn    :6;   /* 15:10 Reserved */

   171

	} hsf_ctrl;

   172

	u16 regval;

   173

};

   174

   175

/* ICH Flash Region Access Permissions */

   176

union ich8_hws_flash_regacc {

   177

	struct ich8_flracc {

   178

		u32 grra      :8; /* 0:7 GbE region Read Access */

   179

		u32 grwa      :8; /* 8:15 GbE region Write Access */

   180

		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */

   181

		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */

   182

	} hsf_flregacc;

   183

	u16 regval;

   184

};

   185

   186

/* ICH Flash Protected Region */

   187

union ich8_flash_protected_range {

   188

	struct ich8_pr {

   189

		u32 base:13;     /* 0:12 Protected Range Base */

   190

		u32 reserved1:2; /* 13:14 Reserved */

   191

		u32 rpe:1;       /* 15 Read Protection Enable */

   192

		u32 limit:13;    /* 16:28 Protected Range Limit */

   193

		u32 reserved2:2; /* 29:30 Reserved */

   194

		u32 wpe:1;       /* 31 Write Protection Enable */

   195

	} range;

   196

	u32 regval;

   197

};

   198

   199

static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);

   200

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   201

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   202

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   203

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   204

						u32 offset, u8 byte);

   205

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   206

					 u8 *data);

   207

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   208

					 u16 *data);

   209

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   210

					 u8 size, u16 *data);

   211

static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

   212

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   213

static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);

   214

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   215

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   216

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   217

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   218

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   219

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   220

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   221

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   222

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   223

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   224

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   225

static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   226

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   227

   228

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   229

{

   230

	return readw(hw->flash_address + reg);

   231

}

   232

   233

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   234

{

   235

	return readl(hw->flash_address + reg);

   236

}

   237

   238

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   239

{

   240

	writew(val, hw->flash_address + reg);

   241

}

   242

   243

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   244

{

   245

	writel(val, hw->flash_address + reg);

   246

}

   247

   248

#define er16flash(reg)		__er16flash(hw, (reg))

   249

#define er32flash(reg)		__er32flash(hw, (reg))

   250

#define ew16flash(reg,val)	__ew16flash(hw, (reg), (val))

   251

#define ew32flash(reg,val)	__ew32flash(hw, (reg), (val))

   252

   253

/**

   254

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   255

 *  @hw: pointer to the HW structure

   256

 *

   257

 *  Initialize family-specific PHY parameters and function pointers.

   258

 **/

   259

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   260

{

   261

	struct e1000_phy_info *phy = &hw->phy;

   262

	s32 ret_val = 0;

   263

   264

	phy->addr                     = 1;

   265

	phy->reset_delay_us           = 100;

   266

   267

	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   268

	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   269

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   270

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   271

	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   272

	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   273

	phy->ops.power_up             = e1000_power_up_phy_copper;

   274

	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   275

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   276

   277

	phy->id = e1000_phy_unknown;

   278

	ret_val = e1000e_get_phy_id(hw);

   279

	if (ret_val)

   280

		goto out;

   281

	if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {

   282

		/*

   283

		 * In case the PHY needs to be in mdio slow mode (eg. 82577),

   284

		 * set slow mode and try to get the PHY id again.

   285

		 */

   286

		ret_val = e1000_set_mdio_slow_mode_hv(hw);

   287

		if (ret_val)

   288

			goto out;

   289

		ret_val = e1000e_get_phy_id(hw);

   290

		if (ret_val)

   291

			goto out;

   292

	}

   293

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   294

   295

	switch (phy->type) {

   296

	case e1000_phy_82577:

   297

		phy->ops.check_polarity = e1000_check_polarity_82577;

   298

		phy->ops.force_speed_duplex =

   299

			e1000_phy_force_speed_duplex_82577;

   300

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   301

		phy->ops.get_info = e1000_get_phy_info_82577;

   302

		phy->ops.commit = e1000e_phy_sw_reset;

   303

	case e1000_phy_82578:

   304

		phy->ops.check_polarity = e1000_check_polarity_m88;

   305

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   306

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   307

		phy->ops.get_info = e1000e_get_phy_info_m88;

   308

		break;

   309

	default:

   310

		ret_val = -E1000_ERR_PHY;

   311

		break;

   312

	}

   313

   314

out:

   315

	return ret_val;

   316

}

   317

   318

/**

   319

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   320

 *  @hw: pointer to the HW structure

   321

 *

   322

 *  Initialize family-specific PHY parameters and function pointers.

   323

 **/

   324

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   325

{

   326

	struct e1000_phy_info *phy = &hw->phy;

   327

	s32 ret_val;

   328

	u16 i = 0;

   329

   330

	phy->addr			= 1;

   331

	phy->reset_delay_us		= 100;

   332

   333

	phy->ops.power_up               = e1000_power_up_phy_copper;

   334

	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

   335

   336

	/*

   337

	 * We may need to do this twice - once for IGP and if that fails,

   338

	 * we'll set BM func pointers and try again

   339

	 */

   340

	ret_val = e1000e_determine_phy_address(hw);

   341

	if (ret_val) {

   342

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   343

		phy->ops.read_reg  = e1000e_read_phy_reg_bm;

   344

		ret_val = e1000e_determine_phy_address(hw);

   345

		if (ret_val) {

   346

			e_dbg("Cannot determine PHY addr. Erroring out\n");

   347

			return ret_val;

   348

		}

   349

	}

   350

   351

	phy->id = 0;

   352

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   353

	       (i++ < 100)) {

   354

		msleep(1);

   355

		ret_val = e1000e_get_phy_id(hw);

   356

		if (ret_val)

   357

			return ret_val;

   358

	}

   359

   360

	/* Verify phy id */

   361

	switch (phy->id) {

   362

	case IGP03E1000_E_PHY_ID:

   363

		phy->type = e1000_phy_igp_3;

   364

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   365

		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   366

		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   367

		phy->ops.get_info = e1000e_get_phy_info_igp;

   368

		phy->ops.check_polarity = e1000_check_polarity_igp;

   369

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   370

		break;

   371

	case IFE_E_PHY_ID:

   372

	case IFE_PLUS_E_PHY_ID:

   373

	case IFE_C_E_PHY_ID:

   374

		phy->type = e1000_phy_ife;

   375

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   376

		phy->ops.get_info = e1000_get_phy_info_ife;

   377

		phy->ops.check_polarity = e1000_check_polarity_ife;

   378

		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   379

		break;

   380

	case BME1000_E_PHY_ID:

   381

		phy->type = e1000_phy_bm;

   382

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   383

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   384

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   385

		phy->ops.commit = e1000e_phy_sw_reset;

   386

		phy->ops.get_info = e1000e_get_phy_info_m88;

   387

		phy->ops.check_polarity = e1000_check_polarity_m88;

   388

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   389

		break;

   390

	default:

   391

		return -E1000_ERR_PHY;

   392

		break;

   393

	}

   394

   395

	return 0;

   396

}

   397

   398

/**

   399

 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   400

 *  @hw: pointer to the HW structure

   401

 *

   402

 *  Initialize family-specific NVM parameters and function

   403

 *  pointers.

   404

 **/

   405

static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   406

{

   407

	struct e1000_nvm_info *nvm = &hw->nvm;

   408

	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   409

	u32 gfpreg, sector_base_addr, sector_end_addr;

   410

	u16 i;

   411

   412

	/* Can't read flash registers if the register set isn't mapped. */

   413

	if (!hw->flash_address) {

   414

		e_dbg("ERROR: Flash registers not mapped\n");

   415

		return -E1000_ERR_CONFIG;

   416

	}

   417

   418

	nvm->type = e1000_nvm_flash_sw;

   419

   420

	gfpreg = er32flash(ICH_FLASH_GFPREG);

   421

   422

	/*

   423

	 * sector_X_addr is a "sector"-aligned address (4096 bytes)

   424

	 * Add 1 to sector_end_addr since this sector is included in

   425

	 * the overall size.

   426

	 */

   427

	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   428

	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   429

   430

	/* flash_base_addr is byte-aligned */

   431

	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   432

   433

	/*

   434

	 * find total size of the NVM, then cut in half since the total

   435

	 * size represents two separate NVM banks.

   436

	 */

   437

	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)

   438

				<< FLASH_SECTOR_ADDR_SHIFT;

   439

	nvm->flash_bank_size /= 2;

   440

	/* Adjust to word count */

   441

	nvm->flash_bank_size /= sizeof(u16);

   442

   443

	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;

   444

   445

	/* Clear shadow ram */

   446

	for (i = 0; i < nvm->word_size; i++) {

   447

		dev_spec->shadow_ram[i].modified = false;

   448

		dev_spec->shadow_ram[i].value    = 0xFFFF;

   449

	}

   450

   451

	return 0;

   452

}

   453

   454

/**

   455

 *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers

   456

 *  @hw: pointer to the HW structure

   457

 *

   458

 *  Initialize family-specific MAC parameters and function

   459

 *  pointers.

   460

 **/

   461

static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)

   462

{

   463

	struct e1000_hw *hw = &adapter->hw;

   464

	struct e1000_mac_info *mac = &hw->mac;

   465

   466

	/* Set media type function pointer */

   467

	hw->phy.media_type = e1000_media_type_copper;

   468

   469

	/* Set mta register count */

   470

	mac->mta_reg_count = 32;

   471

	/* Set rar entry count */

   472

	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;

   473

	if (mac->type == e1000_ich8lan)

   474

		mac->rar_entry_count--;

   475

	/* Set if manageability features are enabled. */

   476

	mac->arc_subsystem_valid = true;

   477

	/* Adaptive IFS supported */

   478

	mac->adaptive_ifs = true;

   479

   480

	/* LED operations */

   481

	switch (mac->type) {

   482

	case e1000_ich8lan:

   483

	case e1000_ich9lan:

   484

	case e1000_ich10lan:

   485

		/* ID LED init */

   486

		mac->ops.id_led_init = e1000e_id_led_init;

   487

		/* setup LED */

   488

		mac->ops.setup_led = e1000e_setup_led_generic;

   489

		/* cleanup LED */

   490

		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;

   491

		/* turn on/off LED */

   492

		mac->ops.led_on = e1000_led_on_ich8lan;

   493

		mac->ops.led_off = e1000_led_off_ich8lan;

   494

		break;

   495

	case e1000_pchlan:

   496

		/* ID LED init */

   497

		mac->ops.id_led_init = e1000_id_led_init_pchlan;

   498

		/* setup LED */

   499

		mac->ops.setup_led = e1000_setup_led_pchlan;

   500

		/* cleanup LED */

   501

		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;

   502

		/* turn on/off LED */

   503

		mac->ops.led_on = e1000_led_on_pchlan;

   504

		mac->ops.led_off = e1000_led_off_pchlan;

   505

		break;

   506

	default:

   507

		break;

   508

	}

   509

   510

	/* Enable PCS Lock-loss workaround for ICH8 */

   511

	if (mac->type == e1000_ich8lan)

   512

		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);

   513

   514

	return 0;

   515

}

   516

   517

/**

   518

 *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)

   519

 *  @hw: pointer to the HW structure

   520

 *

   521

 *  Checks to see of the link status of the hardware has changed.  If a

   522

 *  change in link status has been detected, then we read the PHY registers

   523

 *  to get the current speed/duplex if link exists.

   524

 **/

   525

static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)

   526

{

   527

	struct e1000_mac_info *mac = &hw->mac;

   528

	s32 ret_val;

   529

	bool link;