1

/* Intel PRO/1000 Linux driver

     2

 * Copyright(c) 1999 - 2014 Intel Corporation.

     3

 *

     4

 * This program is free software; you can redistribute it and/or modify it

     5

 * under the terms and conditions of the GNU General Public License,

     6

 * version 2, as published by the Free Software Foundation.

     7

 *

     8

 * This program is distributed in the hope it will be useful, but WITHOUT

     9

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11

 * more details.

    12

 *

    13

 * The full GNU General Public License is included in this distribution in

    14

 * the file called "COPYING".

    15

 *

    16

 * Contact Information:

    17

 * Linux NICS <linux.nics@intel.com>

    18

 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    19

 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    20

 */

    21

    22

/* 80003ES2LAN Gigabit Ethernet Controller (Copper)

    23

 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)

    24

 */

    25

    26

#include "e1000.h"

    27

    28

/* A table for the GG82563 cable length where the range is defined

    29

 * with a lower bound at "index" and the upper bound at

    30

 * "index + 5".

    31

 */

    32

static const u16 e1000_gg82563_cable_length_table[] = {

    33

	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF

    34

};

    35

    36

#define GG82563_CABLE_LENGTH_TABLE_SIZE \

    37

		ARRAY_SIZE(e1000_gg82563_cable_length_table)

    38

    39

static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);

    40

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

    41

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);

    42

static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);

    43

static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);

    44

static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);

    45

static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);

    46

static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

    47

					   u16 *data);

    48

static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,

    49

					    u16 data);

    50

static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);

    51

    52

/**

    53

 *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.

    54

 *  @hw: pointer to the HW structure

    55

 **/

    56

static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)

    57

{

    58

	struct e1000_phy_info *phy = &hw->phy;

    59

	s32 ret_val;

    60

    61

	if (hw->phy.media_type != e1000_media_type_copper) {

    62

		phy->type = e1000_phy_none;

    63

		return 0;

    64

	} else {

    65

		phy->ops.power_up = e1000_power_up_phy_copper;

    66

		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;

    67

	}

    68

    69

	phy->addr = 1;

    70

	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

    71

	phy->reset_delay_us = 100;

    72

	phy->type = e1000_phy_gg82563;

    73

    74

	/* This can only be done after all function pointers are setup. */

    75

	ret_val = e1000e_get_phy_id(hw);

    76

    77

	/* Verify phy id */

    78

	if (phy->id != GG82563_E_PHY_ID)

    79

		return -E1000_ERR_PHY;

    80

    81

	return ret_val;

    82

}

    83

    84

/**

    85

 *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.

    86

 *  @hw: pointer to the HW structure

    87

 **/

    88

static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)

    89

{

    90

	struct e1000_nvm_info *nvm = &hw->nvm;

    91

	u32 eecd = er32(EECD);

    92

	u16 size;

    93

    94

	nvm->opcode_bits = 8;

    95

	nvm->delay_usec = 1;

    96

	switch (nvm->override) {

    97

	case e1000_nvm_override_spi_large:

    98

		nvm->page_size = 32;

    99

		nvm->address_bits = 16;

   100

		break;

   101

	case e1000_nvm_override_spi_small:

   102

		nvm->page_size = 8;

   103

		nvm->address_bits = 8;

   104

		break;

   105

	default:

   106

		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   107

		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   108

		break;

   109

	}

   110

   111

	nvm->type = e1000_nvm_eeprom_spi;

   112

   113

	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   114

		     E1000_EECD_SIZE_EX_SHIFT);

   115

   116

	/* Added to a constant, "size" becomes the left-shift value

   117

	 * for setting word_size.

   118

	 */

   119

	size += NVM_WORD_SIZE_BASE_SHIFT;

   120

   121

	/* EEPROM access above 16k is unsupported */

   122

	if (size > 14)

   123

		size = 14;

   124

	nvm->word_size = 1 << size;

   125

   126

	return 0;

   127

}

   128

   129

/**

   130

 *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.

   131

 *  @hw: pointer to the HW structure

   132

 **/

   133

static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)

   134

{

   135

	struct e1000_mac_info *mac = &hw->mac;

   136

   137

	/* Set media type and media-dependent function pointers */

   138

	switch (hw->adapter->pdev->device) {

   139

	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   140

		hw->phy.media_type = e1000_media_type_internal_serdes;

   141

		mac->ops.check_for_link = e1000e_check_for_serdes_link;

   142

		mac->ops.setup_physical_interface =

   143

		    e1000e_setup_fiber_serdes_link;

   144

		break;

   145

	default:

   146

		hw->phy.media_type = e1000_media_type_copper;

   147

		mac->ops.check_for_link = e1000e_check_for_copper_link;

   148

		mac->ops.setup_physical_interface =

   149

		    e1000_setup_copper_link_80003es2lan;

   150

		break;

   151

	}

   152

   153

	/* Set mta register count */

   154

	mac->mta_reg_count = 128;

   155

	/* Set rar entry count */

   156

	mac->rar_entry_count = E1000_RAR_ENTRIES;

   157

	/* FWSM register */

   158

	mac->has_fwsm = true;

   159

	/* ARC supported; valid only if manageability features are enabled. */

   160

	mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);

   161

	/* Adaptive IFS not supported */

   162

	mac->adaptive_ifs = false;

   163

   164

	/* set lan id for port to determine which phy lock to use */

   165

	hw->mac.ops.set_lan_id(hw);

   166

   167

	return 0;

   168

}

   169

   170

static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)

   171

{

   172

	struct e1000_hw *hw = &adapter->hw;

   173

	s32 rc;

   174

   175

	rc = e1000_init_mac_params_80003es2lan(hw);

   176

	if (rc)

   177

		return rc;

   178

   179

	rc = e1000_init_nvm_params_80003es2lan(hw);

   180

	if (rc)

   181

		return rc;

   182

   183

	rc = e1000_init_phy_params_80003es2lan(hw);

   184

	if (rc)

   185

		return rc;

   186

   187

	return 0;

   188

}

   189

   190

/**

   191

 *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY

   192

 *  @hw: pointer to the HW structure

   193

 *

   194

 *  A wrapper to acquire access rights to the correct PHY.

   195

 **/

   196

static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)

   197

{

   198

	u16 mask;

   199

   200

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   201

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   202

}

   203

   204

/**

   205

 *  e1000_release_phy_80003es2lan - Release rights to access PHY

   206

 *  @hw: pointer to the HW structure

   207

 *

   208

 *  A wrapper to release access rights to the correct PHY.

   209

 **/

   210

static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)

   211

{

   212

	u16 mask;

   213

   214

	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;

   215

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   216

}

   217

   218

/**

   219

 *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register

   220

 *  @hw: pointer to the HW structure

   221

 *

   222

 *  Acquire the semaphore to access the Kumeran interface.

   223

 *

   224

 **/

   225

static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

   226

{

   227

	u16 mask;

   228

   229

	mask = E1000_SWFW_CSR_SM;

   230

   231

	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);

   232

}

   233

   234

/**

   235

 *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register

   236

 *  @hw: pointer to the HW structure

   237

 *

   238

 *  Release the semaphore used to access the Kumeran interface

   239

 **/

   240

static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)

   241

{

   242

	u16 mask;

   243

   244

	mask = E1000_SWFW_CSR_SM;

   245

   246

	e1000_release_swfw_sync_80003es2lan(hw, mask);

   247

}

   248

   249

/**

   250

 *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM

   251

 *  @hw: pointer to the HW structure

   252

 *

   253

 *  Acquire the semaphore to access the EEPROM.

   254

 **/

   255

static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)

   256

{

   257

	s32 ret_val;

   258

   259

	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   260

	if (ret_val)

   261

		return ret_val;

   262

   263

	ret_val = e1000e_acquire_nvm(hw);

   264

   265

	if (ret_val)

   266

		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   267

   268

	return ret_val;

   269

}

   270

   271

/**

   272

 *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM

   273

 *  @hw: pointer to the HW structure

   274

 *

   275

 *  Release the semaphore used to access the EEPROM.

   276

 **/

   277

static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)

   278

{

   279

	e1000e_release_nvm(hw);

   280

	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);

   281

}

   282

   283

/**

   284

 *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore

   285

 *  @hw: pointer to the HW structure

   286

 *  @mask: specifies which semaphore to acquire

   287

 *

   288

 *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask

   289

 *  will also specify which port we're acquiring the lock for.

   290

 **/

   291

static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   292

{

   293

	u32 swfw_sync;

   294

	u32 swmask = mask;

   295

	u32 fwmask = mask << 16;

   296

	s32 i = 0;

   297

	s32 timeout = 50;

   298

   299

	while (i < timeout) {

   300

		if (e1000e_get_hw_semaphore(hw))

   301

			return -E1000_ERR_SWFW_SYNC;

   302

   303

		swfw_sync = er32(SW_FW_SYNC);

   304

		if (!(swfw_sync & (fwmask | swmask)))

   305

			break;

   306

   307

		/* Firmware currently using resource (fwmask)

   308

		 * or other software thread using resource (swmask)

   309

		 */

   310

		e1000e_put_hw_semaphore(hw);

   311

		mdelay(5);

   312

		i++;

   313

	}

   314

   315

	if (i == timeout) {

   316

		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");

   317

		return -E1000_ERR_SWFW_SYNC;

   318

	}

   319

   320

	swfw_sync |= swmask;

   321

	ew32(SW_FW_SYNC, swfw_sync);

   322

   323

	e1000e_put_hw_semaphore(hw);

   324

   325

	return 0;

   326

}

   327

   328

/**

   329

 *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore

   330

 *  @hw: pointer to the HW structure

   331

 *  @mask: specifies which semaphore to acquire

   332

 *

   333

 *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask

   334

 *  will also specify which port we're releasing the lock for.

   335

 **/

   336

static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)

   337

{

   338

	u32 swfw_sync;

   339

   340

	while (e1000e_get_hw_semaphore(hw) != 0)

   341

		; /* Empty */

   342

   343

	swfw_sync = er32(SW_FW_SYNC);

   344

	swfw_sync &= ~mask;

   345

	ew32(SW_FW_SYNC, swfw_sync);

   346

   347

	e1000e_put_hw_semaphore(hw);

   348

}

   349

   350

/**

   351

 *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register

   352

 *  @hw: pointer to the HW structure

   353

 *  @offset: offset of the register to read

   354

 *  @data: pointer to the data returned from the operation

   355

 *

   356

 *  Read the GG82563 PHY register.

   357

 **/

   358

static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   359

						  u32 offset, u16 *data)

   360

{

   361

	s32 ret_val;

   362

	u32 page_select;

   363

	u16 temp;

   364

   365

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   366

	if (ret_val)

   367

		return ret_val;

   368

   369

	/* Select Configuration Page */

   370

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   371

		page_select = GG82563_PHY_PAGE_SELECT;

   372

	} else {

   373

		/* Use Alternative Page Select register to access

   374

		 * registers 30 and 31

   375

		 */

   376

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   377

	}

   378

   379

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   380

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   381

	if (ret_val) {

   382

		e1000_release_phy_80003es2lan(hw);

   383

		return ret_val;

   384

	}

   385

   386

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   387

		/* The "ready" bit in the MDIC register may be incorrectly set

   388

		 * before the device has completed the "Page Select" MDI

   389

		 * transaction.  So we wait 200us after each MDI command...

   390

		 */

   391

		usleep_range(200, 400);

   392

   393

		/* ...and verify the command was successful. */

   394

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   395

   396

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   397

			e1000_release_phy_80003es2lan(hw);

   398

			return -E1000_ERR_PHY;

   399

		}

   400

   401

		usleep_range(200, 400);

   402

   403

		ret_val = e1000e_read_phy_reg_mdic(hw,

   404

						   MAX_PHY_REG_ADDRESS & offset,

   405

						   data);

   406

   407

		usleep_range(200, 400);

   408

	} else {

   409

		ret_val = e1000e_read_phy_reg_mdic(hw,

   410

						   MAX_PHY_REG_ADDRESS & offset,

   411

						   data);

   412

	}

   413

   414

	e1000_release_phy_80003es2lan(hw);

   415

   416

	return ret_val;

   417

}

   418

   419

/**

   420

 *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

   421

 *  @hw: pointer to the HW structure

   422

 *  @offset: offset of the register to read

   423

 *  @data: value to write to the register

   424

 *

   425

 *  Write to the GG82563 PHY register.

   426

 **/

   427

static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,

   428

						   u32 offset, u16 data)

   429

{

   430

	s32 ret_val;

   431

	u32 page_select;

   432

	u16 temp;

   433

   434

	ret_val = e1000_acquire_phy_80003es2lan(hw);

   435

	if (ret_val)

   436

		return ret_val;

   437

   438

	/* Select Configuration Page */

   439

	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {

   440

		page_select = GG82563_PHY_PAGE_SELECT;

   441

	} else {

   442

		/* Use Alternative Page Select register to access

   443

		 * registers 30 and 31

   444

		 */

   445

		page_select = GG82563_PHY_PAGE_SELECT_ALT;

   446

	}

   447

   448

	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);

   449

	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);

   450

	if (ret_val) {

   451

		e1000_release_phy_80003es2lan(hw);

   452

		return ret_val;

   453

	}

   454

   455

	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {

   456

		/* The "ready" bit in the MDIC register may be incorrectly set

   457

		 * before the device has completed the "Page Select" MDI

   458

		 * transaction.  So we wait 200us after each MDI command...

   459

		 */

   460

		usleep_range(200, 400);

   461

   462

		/* ...and verify the command was successful. */

   463

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);

   464

   465

		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {

   466

			e1000_release_phy_80003es2lan(hw);

   467

			return -E1000_ERR_PHY;

   468

		}

   469

   470

		usleep_range(200, 400);

   471

   472

		ret_val = e1000e_write_phy_reg_mdic(hw,

   473

						    MAX_PHY_REG_ADDRESS &

   474

						    offset, data);

   475

   476

		usleep_range(200, 400);

   477

	} else {

   478

		ret_val = e1000e_write_phy_reg_mdic(hw,

   479

						    MAX_PHY_REG_ADDRESS &

   480

						    offset, data);

   481

	}

   482

   483

	e1000_release_phy_80003es2lan(hw);

   484

   485

	return ret_val;

   486

}

   487

   488

/**

   489

 *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM

   490

 *  @hw: pointer to the HW structure

   491

 *  @offset: offset of the register to read

   492

 *  @words: number of words to write

   493

 *  @data: buffer of data to write to the NVM

   494

 *

   495

 *  Write "words" of data to the ESB2 NVM.

   496

 **/

   497

static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,

   498

				       u16 words, u16 *data)

   499

{

   500

	return e1000e_write_nvm_spi(hw, offset, words, data);

   501

}

   502

   503

/**

   504

 *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete

   505

 *  @hw: pointer to the HW structure

   506

 *

   507

 *  Wait a specific amount of time for manageability processes to complete.

   508

 *  This is a function pointer entry point called by the phy module.

   509

 **/

   510

static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)

   511

{

   512

	s32 timeout = PHY_CFG_TIMEOUT;

   513

	u32 mask = E1000_NVM_CFG_DONE_PORT_0;

   514

   515

	if (hw->bus.func == 1)

   516

		mask = E1000_NVM_CFG_DONE_PORT_1;

   517

   518

	while (timeout) {

   519

		if (er32(EEMNGCTL) & mask)

   520

			break;

   521

		usleep_range(1000, 2000);

   522

		timeout--;

   523

	}

   524

	if (!timeout) {

   525

		e_dbg("MNG configuration cycle has not completed.\n");

   526

		return -E1000_ERR_RESET;

   527

	}

   528

   529

	return 0;