1

/*******************************************************************************

     2

     3

     4

  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.

     5

     6

  This program is free software; you can redistribute it and/or modify it 

     7

  under the terms of the GNU General Public License as published by the Free 

     8

  Software Foundation; either version 2 of the License, or (at your option) 

     9

  any later version.

    10

    11

  This program is distributed in the hope that it will be useful, but WITHOUT 

    12

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 

    13

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 

    14

  more details.

    15

    16

  You should have received a copy of the GNU General Public License along with

    17

  this program; if not, write to the Free Software Foundation, Inc., 59 

    18

  Temple Place - Suite 330, Boston, MA  02111-1307, USA.

    19

    20

  The full GNU General Public License is included in this distribution in the

    21

  file called LICENSE.

    22

    23

  Contact Information:

    24

  Linux NICS <linux.nics@intel.com>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

/* e1000_hw.c

    30

 * Shared functions for accessing and configuring the MAC

    31

 */

    32

    33

#include "e1000_hw-2.6.13-ethercat.h"

    34

    35

static int32_t e1000_set_phy_type(struct e1000_hw *hw);

    36

static void e1000_phy_init_script(struct e1000_hw *hw);

    37

static int32_t e1000_setup_copper_link(struct e1000_hw *hw);

    38

static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    39

static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    40

static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    41

static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);

    42

static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);

    43

static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);

    44

static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,

    45

                                     uint16_t count);

    46

static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    47

static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);

    48

static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,

    49

                                      uint16_t words, uint16_t *data);

    50

static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,

    51

                                            uint16_t offset, uint16_t words,

    52

                                            uint16_t *data);

    53

static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);

    54

static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);

    55

static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);

    56

static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,

    57

                                    uint16_t count);

    58

static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,

    59

                                      uint16_t phy_data);

    60

static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,

    61

                                     uint16_t *phy_data);

    62

static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);

    63

static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);

    64

static void e1000_release_eeprom(struct e1000_hw *hw);

    65

static void e1000_standby_eeprom(struct e1000_hw *hw);

    66

static int32_t e1000_set_vco_speed(struct e1000_hw *hw);

    67

static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    68

static int32_t e1000_set_phy_mode(struct e1000_hw *hw);

    69

static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);

    70

static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);

    71

    72

/* IGP cable length table */

    73

static const

    74

uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =

    75

    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    76

      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    77

      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    78

      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

    79

      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

    80

      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,

    81

      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

    82

      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};

    83

    84

static const

    85

uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =

    86

    { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,

    87

      22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,

    88

      32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,

    89

      43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,

    90

      57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,

    91

      73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,

    92

      91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,

    93

      108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};

    94

    95

    96

/******************************************************************************

    97

 * Set the phy type member in the hw struct.

    98

 *

    99

 * hw - Struct containing variables accessed by shared code

   100

 *****************************************************************************/

   101

int32_t

   102

e1000_set_phy_type(struct e1000_hw *hw)

   103

{

   104

    DEBUGFUNC("e1000_set_phy_type");

   105

   106

    if(hw->mac_type == e1000_undefined)

   107

        return -E1000_ERR_PHY_TYPE;

   108

   109

    switch(hw->phy_id) {

   110

    case M88E1000_E_PHY_ID:

   111

    case M88E1000_I_PHY_ID:

   112

    case M88E1011_I_PHY_ID:

   113

    case M88E1111_I_PHY_ID:

   114

        hw->phy_type = e1000_phy_m88;

   115

        break;

   116

    case IGP01E1000_I_PHY_ID:

   117

        if(hw->mac_type == e1000_82541 ||

   118

           hw->mac_type == e1000_82541_rev_2 ||

   119

           hw->mac_type == e1000_82547 ||

   120

           hw->mac_type == e1000_82547_rev_2) {

   121

            hw->phy_type = e1000_phy_igp;

   122

            break;

   123

        }

   124

        /* Fall Through */

   125

    default:

   126

        /* Should never have loaded on this device */

   127

        hw->phy_type = e1000_phy_undefined;

   128

        return -E1000_ERR_PHY_TYPE;

   129

    }

   130

   131

    return E1000_SUCCESS;

   132

}

   133

   134

/******************************************************************************

   135

 * IGP phy init script - initializes the GbE PHY

   136

 *

   137

 * hw - Struct containing variables accessed by shared code

   138

 *****************************************************************************/

   139

static void

   140

e1000_phy_init_script(struct e1000_hw *hw)

   141

{

   142

    uint32_t ret_val;

   143

    uint16_t phy_saved_data;

   144

   145

    DEBUGFUNC("e1000_phy_init_script");

   146

   147

    if(hw->phy_init_script) {

   148

        msec_delay(20);

   149

   150

        /* Save off the current value of register 0x2F5B to be restored at

   151

         * the end of this routine. */

   152

        ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   153

   154

        /* Disabled the PHY transmitter */

   155

        e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   156

   157

        msec_delay(20);

   158

   159

        e1000_write_phy_reg(hw,0x0000,0x0140);

   160

   161

        msec_delay(5);

   162

   163

        switch(hw->mac_type) {

   164

        case e1000_82541:

   165

        case e1000_82547:

   166

            e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   167

   168

            e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   169

   170

            e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   171

   172

            e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   173

   174

            e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   175

   176

            e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   177

   178

            e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   179

   180

            e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   181

   182

            e1000_write_phy_reg(hw, 0x2010, 0x0008);

   183

            break;

   184

   185

        case e1000_82541_rev_2:

   186

        case e1000_82547_rev_2:

   187

            e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   188

            break;

   189

        default:

   190

            break;

   191

        }

   192

   193

        e1000_write_phy_reg(hw, 0x0000, 0x3300);

   194

   195

        msec_delay(20);

   196

   197

        /* Now enable the transmitter */

   198

        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   199

   200

        if(hw->mac_type == e1000_82547) {

   201

            uint16_t fused, fine, coarse;

   202

   203

            /* Move to analog registers page */

   204

            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);

   205

   206

            if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   207

                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);

   208

   209

                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   210

                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   211

   212

                if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   213

                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;

   214

                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   215

                } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   216

                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   217

   218

                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   219

                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   220

                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   221

   222

                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);

   223

                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,

   224

                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   225

            }

   226

        }

   227

    }

   228

}

   229

   230

/******************************************************************************

   231

 * Set the mac type member in the hw struct.

   232

 *

   233

 * hw - Struct containing variables accessed by shared code

   234

 *****************************************************************************/

   235

int32_t

   236

e1000_set_mac_type(struct e1000_hw *hw)

   237

{

   238

    DEBUGFUNC("e1000_set_mac_type");

   239

   240

    switch (hw->device_id) {

   241

    case E1000_DEV_ID_82542:

   242

        switch (hw->revision_id) {

   243

        case E1000_82542_2_0_REV_ID:

   244

            hw->mac_type = e1000_82542_rev2_0;

   245

            break;

   246

        case E1000_82542_2_1_REV_ID:

   247

            hw->mac_type = e1000_82542_rev2_1;

   248

            break;

   249

        default:

   250

            /* Invalid 82542 revision ID */

   251

            return -E1000_ERR_MAC_TYPE;

   252

        }

   253

        break;

   254

    case E1000_DEV_ID_82543GC_FIBER:

   255

    case E1000_DEV_ID_82543GC_COPPER:

   256

        hw->mac_type = e1000_82543;

   257

        break;

   258

    case E1000_DEV_ID_82544EI_COPPER:

   259

    case E1000_DEV_ID_82544EI_FIBER:

   260

    case E1000_DEV_ID_82544GC_COPPER:

   261

    case E1000_DEV_ID_82544GC_LOM:

   262

        hw->mac_type = e1000_82544;

   263

        break;

   264

    case E1000_DEV_ID_82540EM:

   265

    case E1000_DEV_ID_82540EM_LOM:

   266

    case E1000_DEV_ID_82540EP:

   267

    case E1000_DEV_ID_82540EP_LOM:

   268

    case E1000_DEV_ID_82540EP_LP:

   269

        hw->mac_type = e1000_82540;

   270

        break;

   271

    case E1000_DEV_ID_82545EM_COPPER:

   272

    case E1000_DEV_ID_82545EM_FIBER:

   273

        hw->mac_type = e1000_82545;

   274

        break;

   275

    case E1000_DEV_ID_82545GM_COPPER:

   276

    case E1000_DEV_ID_82545GM_FIBER:

   277

    case E1000_DEV_ID_82545GM_SERDES:

   278

        hw->mac_type = e1000_82545_rev_3;

   279

        break;

   280

    case E1000_DEV_ID_82546EB_COPPER:

   281

    case E1000_DEV_ID_82546EB_FIBER:

   282

    case E1000_DEV_ID_82546EB_QUAD_COPPER:

   283

        hw->mac_type = e1000_82546;

   284

        break;

   285

    case E1000_DEV_ID_82546GB_COPPER:

   286

    case E1000_DEV_ID_82546GB_FIBER:

   287

    case E1000_DEV_ID_82546GB_SERDES:

   288

    case E1000_DEV_ID_82546GB_PCIE:

   289

    case E1000_DEV_ID_82546GB_QUAD_COPPER:

   290

        hw->mac_type = e1000_82546_rev_3;

   291

        break;

   292

    case E1000_DEV_ID_82541EI:

   293

    case E1000_DEV_ID_82541EI_MOBILE:

   294

        hw->mac_type = e1000_82541;

   295

        break;

   296

    case E1000_DEV_ID_82541ER:

   297

    case E1000_DEV_ID_82541GI:

   298

    case E1000_DEV_ID_82541GI_LF:

   299

    case E1000_DEV_ID_82541GI_MOBILE:

   300

        hw->mac_type = e1000_82541_rev_2;

   301

        break;

   302

    case E1000_DEV_ID_82547EI:

   303

        hw->mac_type = e1000_82547;

   304

        break;

   305

    case E1000_DEV_ID_82547GI:

   306

        hw->mac_type = e1000_82547_rev_2;

   307

        break;

   308

    case E1000_DEV_ID_82573E:

   309

    case E1000_DEV_ID_82573E_IAMT:

   310

        hw->mac_type = e1000_82573;

   311

        break;

   312

    default:

   313

        /* Should never have loaded on this device */

   314

        return -E1000_ERR_MAC_TYPE;

   315

    }

   316

   317

    switch(hw->mac_type) {

   318

    case e1000_82573:

   319

        hw->eeprom_semaphore_present = TRUE;

   320

        /* fall through */

   321

    case e1000_82541:

   322

    case e1000_82547:

   323

    case e1000_82541_rev_2:

   324

    case e1000_82547_rev_2:

   325

        hw->asf_firmware_present = TRUE;

   326

        break;

   327

    default:

   328

        break;

   329

    }

   330

   331

    return E1000_SUCCESS;

   332

}

   333

   334

/*****************************************************************************

   335

 * Set media type and TBI compatibility.

   336

 *

   337

 * hw - Struct containing variables accessed by shared code

   338

 * **************************************************************************/

   339

void

   340

e1000_set_media_type(struct e1000_hw *hw)

   341

{

   342

    uint32_t status;

   343

   344

    DEBUGFUNC("e1000_set_media_type");

   345

   346

    if(hw->mac_type != e1000_82543) {

   347

        /* tbi_compatibility is only valid on 82543 */

   348

        hw->tbi_compatibility_en = FALSE;

   349

    }

   350

   351

    switch (hw->device_id) {

   352

    case E1000_DEV_ID_82545GM_SERDES:

   353

    case E1000_DEV_ID_82546GB_SERDES:

   354

        hw->media_type = e1000_media_type_internal_serdes;

   355

        break;

   356

    default:

   357

        switch (hw->mac_type) {

   358

        case e1000_82542_rev2_0:

   359

        case e1000_82542_rev2_1:

   360

            hw->media_type = e1000_media_type_fiber;

   361

            break;

   362

        case e1000_82573:

   363

            /* The STATUS_TBIMODE bit is reserved or reused for the this

   364

             * device.

   365

             */

   366

            hw->media_type = e1000_media_type_copper;

   367

            break;

   368

        default:

   369

            status = E1000_READ_REG(hw, STATUS);

   370

            if (status & E1000_STATUS_TBIMODE) {

   371

                hw->media_type = e1000_media_type_fiber;

   372

                /* tbi_compatibility not valid on fiber */

   373

                hw->tbi_compatibility_en = FALSE;

   374

            } else {

   375

                hw->media_type = e1000_media_type_copper;

   376

            }

   377

            break;

   378

        }

   379

    }

   380

}

   381

   382

/******************************************************************************

   383

 * Reset the transmit and receive units; mask and clear all interrupts.

   384

 *

   385

 * hw - Struct containing variables accessed by shared code

   386

 *****************************************************************************/

   387

int32_t

   388

e1000_reset_hw(struct e1000_hw *hw)

   389

{

   390

    uint32_t ctrl;

   391

    uint32_t ctrl_ext;

   392

    uint32_t icr;

   393

    uint32_t manc;

   394

    uint32_t led_ctrl;

   395

    uint32_t timeout;

   396

    uint32_t extcnf_ctrl;

   397

    int32_t ret_val;

   398

   399

    DEBUGFUNC("e1000_reset_hw");

   400

   401

    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   402

    if(hw->mac_type == e1000_82542_rev2_0) {

   403

        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   404

        e1000_pci_clear_mwi(hw);

   405

    }

   406

   407

    if(hw->bus_type == e1000_bus_type_pci_express) {

   408

        /* Prevent the PCI-E bus from sticking if there is no TLP connection

   409

         * on the last TLP read/write transaction when MAC is reset.

   410

         */

   411

        if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {

   412

            DEBUGOUT("PCI-E Master disable polling has failed.\n");

   413

        }

   414

    }

   415

   416

    /* Clear interrupt mask to stop board from generating interrupts */

   417

    DEBUGOUT("Masking off all interrupts\n");

   418

    E1000_WRITE_REG(hw, IMC, 0xffffffff);

   419

   420

    /* Disable the Transmit and Receive units.  Then delay to allow

   421

     * any pending transactions to complete before we hit the MAC with

   422

     * the global reset.

   423

     */

   424

    E1000_WRITE_REG(hw, RCTL, 0);

   425

    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);

   426

    E1000_WRITE_FLUSH(hw);

   427

   428

    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   429

    hw->tbi_compatibility_on = FALSE;

   430

   431

    /* Delay to allow any outstanding PCI transactions to complete before

   432

     * resetting the device

   433

     */

   434

    msec_delay(10);

   435

   436

    ctrl = E1000_READ_REG(hw, CTRL);

   437

   438

    /* Must reset the PHY before resetting the MAC */

   439

    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   440

        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));

   441

        msec_delay(5);

   442

    }

   443

   444

    /* Must acquire the MDIO ownership before MAC reset.

   445

     * Ownership defaults to firmware after a reset. */

   446

    if(hw->mac_type == e1000_82573) {

   447

        timeout = 10;

   448

   449

        extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   450

        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   451

   452

        do {

   453

            E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);

   454

            extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   455

   456

            if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   457

                break;

   458

            else

   459

                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   460

   461

            msec_delay(2);

   462

            timeout--;

   463

        } while(timeout);

   464

    }

   465

   466

    /* Issue a global reset to the MAC.  This will reset the chip's

   467

     * transmit, receive, DMA, and link units.  It will not effect

   468

     * the current PCI configuration.  The global reset bit is self-

   469

     * clearing, and should clear within a microsecond.

   470

     */

   471

    DEBUGOUT("Issuing a global reset to MAC\n");

   472

   473

    switch(hw->mac_type) {

   474

        case e1000_82544:

   475

        case e1000_82540:

   476

        case e1000_82545:

   477

        case e1000_82546:

   478

        case e1000_82541:

   479

        case e1000_82541_rev_2:

   480

            /* These controllers can't ack the 64-bit write when issuing the

   481

             * reset, so use IO-mapping as a workaround to issue the reset */

   482

            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   483

            break;

   484

        case e1000_82545_rev_3:

   485

        case e1000_82546_rev_3:

   486

            /* Reset is performed on a shadow of the control register */

   487

            E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));

   488

            break;

   489

        default:

   490

            E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

   491

            break;

   492

    }

   493

   494

    /* After MAC reset, force reload of EEPROM to restore power-on settings to

   495

     * device.  Later controllers reload the EEPROM automatically, so just wait

   496

     * for reload to complete.

   497

     */

   498

    switch(hw->mac_type) {

   499

        case e1000_82542_rev2_0:

   500

        case e1000_82542_rev2_1:

   501

        case e1000_82543:

   502

        case e1000_82544:

   503

            /* Wait for reset to complete */

   504

            udelay(10);

   505

            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   506

            ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   507

            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   508

            E1000_WRITE_FLUSH(hw);

   509

            /* Wait for EEPROM reload */

   510

            msec_delay(2);

   511

            break;

   512

        case e1000_82541:

   513

        case e1000_82541_rev_2:

   514

        case e1000_82547:

   515

        case e1000_82547_rev_2:

   516

            /* Wait for EEPROM reload */

   517

            msec_delay(20);

   518

            break;

   519

        case e1000_82573:

   520

            udelay(10);

   521

            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   522

            ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   523

            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   524

            E1000_WRITE_FLUSH(hw);

   525

            /* fall through */

   526

            ret_val = e1000_get_auto_rd_done(hw);

   527

            if(ret_val)

   528

                /* We don't want to continue accessing MAC registers. */

   529

                return ret_val;

   530