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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2013 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

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  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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*******************************************************************************/

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#ifndef _E1000E_ICH8LAN_H_

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#define _E1000E_ICH8LAN_H_

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#define ICH_FLASH_GFPREG		0x0000

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#define ICH_FLASH_HSFSTS		0x0004

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#define ICH_FLASH_HSFCTL		0x0006

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#define ICH_FLASH_FADDR			0x0008

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#define ICH_FLASH_FDATA0		0x0010

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#define ICH_FLASH_PR0			0x0074

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/* Requires up to 10 seconds when MNG might be accessing part. */

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#define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000

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#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000

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#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000

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#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

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#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

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#define ICH_CYCLE_READ			0

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#define ICH_CYCLE_WRITE			2

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#define ICH_CYCLE_ERASE			3

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#define FLASH_GFPREG_BASE_MASK		0x1FFF

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#define FLASH_SECTOR_ADDR_SHIFT		12

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#define ICH_FLASH_SEG_SIZE_256		256

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#define ICH_FLASH_SEG_SIZE_4K		4096

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#define ICH_FLASH_SEG_SIZE_8K		8192

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#define ICH_FLASH_SEG_SIZE_64K		65536

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#define E1000_ICH_FWSM_RSPCIPHY	0x00000040	/* Reset PHY on PCI Reset */

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/* FW established a valid mode */

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#define E1000_ICH_FWSM_FW_VALID	0x00008000

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#define E1000_ICH_FWSM_PCIM2PCI	0x01000000	/* ME PCIm-to-PCI active */

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#define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000

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#define E1000_ICH_MNG_IAMT_MODE		0x2

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#define E1000_FWSM_WLOCK_MAC_MASK	0x0380

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#define E1000_FWSM_WLOCK_MAC_SHIFT	7

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/* Shared Receive Address Registers */

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#define E1000_SHRAL_PCH_LPT(_i)		(0x05408 + ((_i) * 8))

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#define E1000_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))

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#define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \

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				 (ID_LED_OFF1_OFF2 <<  8) | \

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				 (ID_LED_OFF1_ON2  <<  4) | \

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				 (ID_LED_DEF1_DEF2))

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#define E1000_ICH_NVM_SIG_WORD		0x13

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#define E1000_ICH_NVM_SIG_MASK		0xC000

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#define E1000_ICH_NVM_VALID_SIG_MASK	0xC0

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#define E1000_ICH_NVM_SIG_VALUE		0x80

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#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

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#define E1000_FEXTNVM_SW_CONFIG		1

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#define E1000_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27)	/* different on ICH8M */

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#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK	0x0C000000

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#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC	0x08000000

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#define E1000_FEXTNVM4_BEACON_DURATION_MASK	0x7

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#define E1000_FEXTNVM4_BEACON_DURATION_8USEC	0x7

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#define E1000_FEXTNVM4_BEACON_DURATION_16USEC	0x3

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#define E1000_FEXTNVM6_REQ_PLL_CLK	0x00000100

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#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200

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#define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL

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#define E1000_ICH_RAR_ENTRIES	7

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#define E1000_PCH2_RAR_ENTRIES	11      /* RAR[0-6], SHRA[0-3] */

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#define E1000_PCH_LPT_RAR_ENTRIES	12	/* RAR[0], SHRA[0-10] */

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#define PHY_PAGE_SHIFT		5

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#define PHY_REG(page, reg)	(((page) << PHY_PAGE_SHIFT) | \

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				 ((reg) & MAX_PHY_REG_ADDRESS))

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#define IGP3_KMRN_DIAG	PHY_REG(770, 19)	/* KMRN Diagnostic */

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#define IGP3_VR_CTRL	PHY_REG(776, 18)	/* Voltage Regulator Control */

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#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS		0x0002

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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK	0x0300

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#define IGP3_VR_CTRL_MODE_SHUTDOWN		0x0200

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/* PHY Wakeup Registers and defines */

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#define BM_PORT_GEN_CFG		PHY_REG(BM_PORT_CTRL_PAGE, 17)

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#define BM_RCTL			PHY_REG(BM_WUC_PAGE, 0)

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#define BM_WUC			PHY_REG(BM_WUC_PAGE, 1)

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#define BM_WUFC			PHY_REG(BM_WUC_PAGE, 2)

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#define BM_WUS			PHY_REG(BM_WUC_PAGE, 3)

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#define BM_RAR_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))

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#define BM_RAR_M(_i)		(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))

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#define BM_RAR_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))

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#define BM_RAR_CTRL(_i)		(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))

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#define BM_MTA(_i)		(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))

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#define BM_RCTL_UPE		0x0001	/* Unicast Promiscuous Mode */

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#define BM_RCTL_MPE		0x0002	/* Multicast Promiscuous Mode */

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#define BM_RCTL_MO_SHIFT	3	/* Multicast Offset Shift */

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#define BM_RCTL_MO_MASK		(3 << 3)	/* Multicast Offset Mask */

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#define BM_RCTL_BAM		0x0020	/* Broadcast Accept Mode */

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#define BM_RCTL_PMCF		0x0040	/* Pass MAC Control Frames */

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#define BM_RCTL_RFCE		0x0080	/* Rx Flow Control Enable */

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#define HV_LED_CONFIG		PHY_REG(768, 30)	/* LED Configuration */

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#define HV_MUX_DATA_CTRL	PHY_REG(776, 16)

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#define HV_MUX_DATA_CTRL_GEN_TO_MAC	0x0400

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#define HV_MUX_DATA_CTRL_FORCE_SPEED	0x0004

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#define HV_STATS_PAGE	778

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/* Half-duplex collision counts */

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#define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16)	/* Single Collision */

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#define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)

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#define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18)	/* Excessive Coll. */

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#define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)

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#define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20)	/* Multiple Collision */

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#define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)

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#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23)	/* Late Collision */

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#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)

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#define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25)	/* Collision */

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#define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)

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#define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27)	/* Defer Count */

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#define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)

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#define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29)	/* Tx with no CRS */

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#define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)

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#define E1000_FCRTV_PCH	0x05F40	/* PCH Flow Control Refresh Timer Value */

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#define E1000_NVM_K1_CONFIG	0x1B	/* NVM K1 Config Word */

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#define E1000_NVM_K1_ENABLE	0x1	/* NVM Enable K1 bit */

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/* SMBus Control Phy Register */

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#define CV_SMB_CTRL		PHY_REG(769, 23)

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#define CV_SMB_CTRL_FORCE_SMBUS	0x0001

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/* SMBus Address Phy Register */

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#define HV_SMB_ADDR		PHY_REG(768, 26)

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#define HV_SMB_ADDR_MASK	0x007F

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#define HV_SMB_ADDR_PEC_EN	0x0200

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#define HV_SMB_ADDR_VALID	0x0080

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#define HV_SMB_ADDR_FREQ_MASK		0x1100

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#define HV_SMB_ADDR_FREQ_LOW_SHIFT	8

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#define HV_SMB_ADDR_FREQ_HIGH_SHIFT	12

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/* Strapping Option Register - RO */

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#define E1000_STRAP			0x0000C

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#define E1000_STRAP_SMBUS_ADDRESS_MASK	0x00FE0000

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#define E1000_STRAP_SMBUS_ADDRESS_SHIFT	17

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#define E1000_STRAP_SMT_FREQ_MASK	0x00003000

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#define E1000_STRAP_SMT_FREQ_SHIFT	12

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/* OEM Bits Phy Register */

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#define HV_OEM_BITS		PHY_REG(768, 25)

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#define HV_OEM_BITS_LPLU	0x0004	/* Low Power Link Up */

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#define HV_OEM_BITS_GBE_DIS	0x0040	/* Gigabit Disable */

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#define HV_OEM_BITS_RESTART_AN	0x0400	/* Restart Auto-negotiation */

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/* KMRN Mode Control */

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#define HV_KMRN_MODE_CTRL	PHY_REG(769, 16)

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#define HV_KMRN_MDIO_SLOW	0x0400

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/* KMRN FIFO Control and Status */

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#define HV_KMRN_FIFO_CTRLSTA			PHY_REG(770, 16)

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#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK	0x7000

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#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT	12

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/* PHY Power Management Control */

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#define HV_PM_CTRL		PHY_REG(770, 17)

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#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA	0x100

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#define SW_FLAG_TIMEOUT		1000	/* SW Semaphore flag timeout in ms */

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/* Inband Control */

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#define I217_INBAND_CTRL				PHY_REG(770, 18)

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#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK	0x3F00

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#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT	8

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/* PHY Low Power Idle Control */

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#define I82579_LPI_CTRL				PHY_REG(772, 20)

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#define I82579_LPI_CTRL_100_ENABLE		0x2000

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#define I82579_LPI_CTRL_1000_ENABLE		0x4000

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#define I82579_LPI_CTRL_ENABLE_MASK		0x6000

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#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80

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/* Extended Management Interface (EMI) Registers */

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#define I82579_EMI_ADDR		0x10

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#define I82579_EMI_DATA		0x11

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#define I82579_LPI_UPDATE_TIMER	0x4805	/* in 40ns units + 40 ns base value */

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#define I82579_MSE_THRESHOLD	0x084F	/* 82579 Mean Square Error Threshold */

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#define I82577_MSE_THRESHOLD	0x0887	/* 82577 Mean Square Error Threshold */

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#define I82579_MSE_LINK_DOWN	0x2411	/* MSE count before dropping link */

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#define I82579_RX_CONFIG		0x3412	/* Receive configuration */

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#define I82579_EEE_PCS_STATUS		0x182E	/* IEEE MMD Register 3.1 >> 8 */

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#define I82579_EEE_CAPABILITY		0x0410	/* IEEE MMD Register 3.20 */

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#define I82579_EEE_ADVERTISEMENT	0x040E	/* IEEE MMD Register 7.60 */

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#define I82579_EEE_LP_ABILITY		0x040F	/* IEEE MMD Register 7.61 */

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#define I82579_EEE_100_SUPPORTED	(1 << 1)	/* 100BaseTx EEE */

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#define I82579_EEE_1000_SUPPORTED	(1 << 2)	/* 1000BaseTx EEE */

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#define I217_EEE_PCS_STATUS	0x9401	/* IEEE MMD Register 3.1 */

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#define I217_EEE_CAPABILITY	0x8000	/* IEEE MMD Register 3.20 */

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#define I217_EEE_ADVERTISEMENT	0x8001	/* IEEE MMD Register 7.60 */

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#define I217_EEE_LP_ABILITY	0x8002	/* IEEE MMD Register 7.61 */

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#define E1000_EEE_RX_LPI_RCVD	0x0400	/* Tx LP idle received */

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#define E1000_EEE_TX_LPI_RCVD	0x0800	/* Rx LP idle received */

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/* Intel Rapid Start Technology Support */

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#define I217_PROXY_CTRL		BM_PHY_REG(BM_WUC_PAGE, 70)

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#define I217_PROXY_CTRL_AUTO_DISABLE	0x0080

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#define I217_SxCTRL			PHY_REG(BM_PORT_CTRL_PAGE, 28)

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#define I217_SxCTRL_ENABLE_LPI_RESET	0x1000

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#define I217_CGFREG			PHY_REG(772, 29)

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#define I217_CGFREG_ENABLE_MTA_RESET	0x0002

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#define I217_MEMPWR			PHY_REG(772, 26)

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#define I217_MEMPWR_DISABLE_SMB_RELEASE	0x0010

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/* Receive Address Initial CRC Calculation */

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#define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))

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/* Latency Tolerance Reporting */

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#define E1000_LTRV			0x000F8

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#define E1000_LTRV_SCALE_MAX		5

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#define E1000_LTRV_SCALE_FACTOR		5

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#define E1000_LTRV_REQ_SHIFT		15

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#define E1000_LTRV_NOSNOOP_SHIFT	16

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#define E1000_LTRV_SEND			(1 << 30)

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/* Proprietary Latency Tolerance Reporting PCI Capability */

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#define E1000_PCI_LTR_CAP_LPT		0xA8

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void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);

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void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,

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						  bool state);

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void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);

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void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);

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void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);

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void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);

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s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);

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void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);

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s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);

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s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);

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s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);

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#endif /* _E1000E_ICH8LAN_H_ */