1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2012 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

#include "e1000.h"

    30

    31

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    32

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    33

static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);

    34

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    35

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);

    36

static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,

    37

					  u16 *data, bool read, bool page_set);

    38

static u32 e1000_get_phy_addr_for_hv_page(u32 page);

    39

static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,

    40

                                          u16 *data, bool read);

    41

    42

/* Cable length tables */

    43

static const u16 e1000_m88_cable_length_table[] = {

    44

	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };

    45

#define M88E1000_CABLE_LENGTH_TABLE_SIZE \

    46

		ARRAY_SIZE(e1000_m88_cable_length_table)

    47

    48

static const u16 e1000_igp_2_cable_length_table[] = {

    49

	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,

    50

	6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,

    51

	26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,

    52

	44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,

    53

	66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,

    54

	87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,

    55

	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,

    56

	124};

    57

#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \

    58

		ARRAY_SIZE(e1000_igp_2_cable_length_table)

    59

    60

#define BM_PHY_REG_PAGE(offset) \

    61

	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))

    62

#define BM_PHY_REG_NUM(offset) \

    63

	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\

    64

	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\

    65

		~MAX_PHY_REG_ADDRESS)))

    66

    67

#define HV_INTC_FC_PAGE_START             768

    68

#define I82578_ADDR_REG                   29

    69

#define I82577_ADDR_REG                   16

    70

#define I82577_CFG_REG                    22

    71

#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)

    72

#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */

    73

#define I82577_CTRL_REG                   23

    74

    75

/* 82577 specific PHY registers */

    76

#define I82577_PHY_CTRL_2            18

    77

#define I82577_PHY_STATUS_2          26

    78

#define I82577_PHY_DIAG_STATUS       31

    79

    80

/* I82577 PHY Status 2 */

    81

#define I82577_PHY_STATUS2_REV_POLARITY   0x0400

    82

#define I82577_PHY_STATUS2_MDIX           0x0800

    83

#define I82577_PHY_STATUS2_SPEED_MASK     0x0300

    84

#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200

    85

    86

/* I82577 PHY Control 2 */

    87

#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400

    88

#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200

    89

    90

/* I82577 PHY Diagnostics Status */

    91

#define I82577_DSTATUS_CABLE_LENGTH       0x03FC

    92

#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2

    93

    94

/* BM PHY Copper Specific Control 1 */

    95

#define BM_CS_CTRL1                       16

    96

    97

#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)

    98

#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400

    99

#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004

   100

   101

/**

   102

 *  e1000e_check_reset_block_generic - Check if PHY reset is blocked

   103

 *  @hw: pointer to the HW structure

   104

 *

   105

 *  Read the PHY management control register and check whether a PHY reset

   106

 *  is blocked.  If a reset is not blocked return 0, otherwise

   107

 *  return E1000_BLK_PHY_RESET (12).

   108

 **/

   109

s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)

   110

{

   111

	u32 manc;

   112

   113

	manc = er32(MANC);

   114

   115

	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?

   116

	       E1000_BLK_PHY_RESET : 0;

   117

}

   118

   119

/**

   120

 *  e1000e_get_phy_id - Retrieve the PHY ID and revision

   121

 *  @hw: pointer to the HW structure

   122

 *

   123

 *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   124

 *  revision in the hardware structure.

   125

 **/

   126

s32 e1000e_get_phy_id(struct e1000_hw *hw)

   127

{

   128

	struct e1000_phy_info *phy = &hw->phy;

   129

	s32 ret_val = 0;

   130

	u16 phy_id;

   131

	u16 retry_count = 0;

   132

   133

	if (!phy->ops.read_reg)

   134

		return 0;

   135

   136

	while (retry_count < 2) {

   137

		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   138

		if (ret_val)

   139

			return ret_val;

   140

   141

		phy->id = (u32)(phy_id << 16);

   142

		udelay(20);

   143

		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   144

		if (ret_val)

   145

			return ret_val;

   146

   147

		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

   148

		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   149

   150

		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)

   151

			return 0;

   152

   153

		retry_count++;

   154

	}

   155

   156

	return 0;

   157

}

   158

   159

/**

   160

 *  e1000e_phy_reset_dsp - Reset PHY DSP

   161

 *  @hw: pointer to the HW structure

   162

 *

   163

 *  Reset the digital signal processor.

   164

 **/

   165

s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)

   166

{

   167

	s32 ret_val;

   168

   169

	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

   170

	if (ret_val)

   171

		return ret_val;

   172

   173

	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);

   174

}

   175

   176

/**

   177

 *  e1000e_read_phy_reg_mdic - Read MDI control register

   178

 *  @hw: pointer to the HW structure

   179

 *  @offset: register offset to be read

   180

 *  @data: pointer to the read data

   181

 *

   182

 *  Reads the MDI control register in the PHY at offset and stores the

   183

 *  information read to data.

   184

 **/

   185

s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)

   186

{

   187

	struct e1000_phy_info *phy = &hw->phy;

   188

	u32 i, mdic = 0;

   189

   190

	if (offset > MAX_PHY_REG_ADDRESS) {

   191

		e_dbg("PHY Address %d is out of range\n", offset);

   192

		return -E1000_ERR_PARAM;

   193

	}

   194

   195

	/*

   196

	 * Set up Op-code, Phy Address, and register offset in the MDI

   197

	 * Control register.  The MAC will take care of interfacing with the

   198

	 * PHY to retrieve the desired data.

   199

	 */

   200

	mdic = ((offset << E1000_MDIC_REG_SHIFT) |

   201

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   202

		(E1000_MDIC_OP_READ));

   203

   204

	ew32(MDIC, mdic);

   205

   206

	/*

   207

	 * Poll the ready bit to see if the MDI read completed

   208

	 * Increasing the time out as testing showed failures with

   209

	 * the lower time out

   210

	 */

   211

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   212

		udelay(50);

   213

		mdic = er32(MDIC);

   214

		if (mdic & E1000_MDIC_READY)

   215

			break;

   216

	}

   217

	if (!(mdic & E1000_MDIC_READY)) {

   218

		e_dbg("MDI Read did not complete\n");

   219

		return -E1000_ERR_PHY;

   220

	}

   221

	if (mdic & E1000_MDIC_ERROR) {

   222

		e_dbg("MDI Error\n");

   223

		return -E1000_ERR_PHY;

   224

	}

   225

	*data = (u16) mdic;

   226

   227

	/*

   228

	 * Allow some time after each MDIC transaction to avoid

   229

	 * reading duplicate data in the next MDIC transaction.

   230

	 */

   231

	if (hw->mac.type == e1000_pch2lan)

   232

		udelay(100);

   233

   234

	return 0;

   235

}

   236

   237

/**

   238

 *  e1000e_write_phy_reg_mdic - Write MDI control register

   239

 *  @hw: pointer to the HW structure

   240

 *  @offset: register offset to write to

   241

 *  @data: data to write to register at offset

   242

 *

   243

 *  Writes data to MDI control register in the PHY at offset.

   244

 **/

   245

s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)

   246

{

   247

	struct e1000_phy_info *phy = &hw->phy;

   248

	u32 i, mdic = 0;

   249

   250

	if (offset > MAX_PHY_REG_ADDRESS) {

   251

		e_dbg("PHY Address %d is out of range\n", offset);

   252

		return -E1000_ERR_PARAM;

   253

	}

   254

   255

	/*

   256

	 * Set up Op-code, Phy Address, and register offset in the MDI

   257

	 * Control register.  The MAC will take care of interfacing with the

   258

	 * PHY to retrieve the desired data.

   259

	 */

   260

	mdic = (((u32)data) |

   261

		(offset << E1000_MDIC_REG_SHIFT) |

   262

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   263

		(E1000_MDIC_OP_WRITE));

   264

   265

	ew32(MDIC, mdic);

   266

   267

	/*

   268

	 * Poll the ready bit to see if the MDI read completed

   269

	 * Increasing the time out as testing showed failures with

   270

	 * the lower time out

   271

	 */

   272

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   273

		udelay(50);

   274

		mdic = er32(MDIC);

   275

		if (mdic & E1000_MDIC_READY)

   276

			break;

   277

	}

   278

	if (!(mdic & E1000_MDIC_READY)) {

   279

		e_dbg("MDI Write did not complete\n");

   280

		return -E1000_ERR_PHY;

   281

	}

   282

	if (mdic & E1000_MDIC_ERROR) {

   283

		e_dbg("MDI Error\n");

   284

		return -E1000_ERR_PHY;

   285

	}

   286

   287

	/*

   288

	 * Allow some time after each MDIC transaction to avoid

   289

	 * reading duplicate data in the next MDIC transaction.

   290

	 */

   291

	if (hw->mac.type == e1000_pch2lan)

   292

		udelay(100);

   293

   294

	return 0;

   295

}

   296

   297

/**

   298

 *  e1000e_read_phy_reg_m88 - Read m88 PHY register

   299

 *  @hw: pointer to the HW structure

   300

 *  @offset: register offset to be read

   301

 *  @data: pointer to the read data

   302

 *

   303

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   304

 *  and storing the retrieved information in data.  Release any acquired

   305

 *  semaphores before exiting.

   306

 **/

   307

s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)

   308

{

   309

	s32 ret_val;

   310

   311

	ret_val = hw->phy.ops.acquire(hw);

   312

	if (ret_val)

   313

		return ret_val;

   314

   315

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   316

					   data);

   317

   318

	hw->phy.ops.release(hw);

   319

   320

	return ret_val;

   321

}

   322

   323

/**

   324

 *  e1000e_write_phy_reg_m88 - Write m88 PHY register

   325

 *  @hw: pointer to the HW structure

   326

 *  @offset: register offset to write to

   327

 *  @data: data to write at register offset

   328

 *

   329

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   330

 *  at the offset.  Release any acquired semaphores before exiting.

   331

 **/

   332

s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)

   333

{

   334

	s32 ret_val;

   335

   336

	ret_val = hw->phy.ops.acquire(hw);

   337

	if (ret_val)

   338

		return ret_val;

   339

   340

	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   341

					    data);

   342

   343

	hw->phy.ops.release(hw);

   344

   345

	return ret_val;

   346

}

   347

   348

/**

   349

 *  e1000_set_page_igp - Set page as on IGP-like PHY(s)

   350

 *  @hw: pointer to the HW structure

   351

 *  @page: page to set (shifted left when necessary)

   352

 *

   353

 *  Sets PHY page required for PHY register access.  Assumes semaphore is

   354

 *  already acquired.  Note, this function sets phy.addr to 1 so the caller

   355

 *  must set it appropriately (if necessary) after this function returns.

   356

 **/

   357

s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)

   358

{

   359

	e_dbg("Setting page 0x%x\n", page);

   360

   361

	hw->phy.addr = 1;

   362

   363

	return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);

   364

}

   365

   366

/**

   367

 *  __e1000e_read_phy_reg_igp - Read igp PHY register

   368

 *  @hw: pointer to the HW structure

   369

 *  @offset: register offset to be read

   370

 *  @data: pointer to the read data

   371

 *  @locked: semaphore has already been acquired or not

   372

 *

   373

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   374

 *  and stores the retrieved information in data.  Release any acquired

   375

 *  semaphores before exiting.

   376

 **/

   377

static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,

   378

                                    bool locked)

   379

{

   380

	s32 ret_val = 0;

   381

   382

	if (!locked) {

   383

		if (!hw->phy.ops.acquire)

   384

			return 0;

   385

   386

		ret_val = hw->phy.ops.acquire(hw);

   387

		if (ret_val)

   388

			return ret_val;

   389

	}

   390

   391

	if (offset > MAX_PHY_MULTI_PAGE_REG)

   392

		ret_val = e1000e_write_phy_reg_mdic(hw,

   393

						    IGP01E1000_PHY_PAGE_SELECT,

   394

						    (u16)offset);

   395

	if (!ret_val)

   396

		ret_val = e1000e_read_phy_reg_mdic(hw,

   397

						   MAX_PHY_REG_ADDRESS & offset,

   398

						   data);

   399

	if (!locked)

   400

		hw->phy.ops.release(hw);

   401

   402

	return ret_val;

   403

}

   404

   405

/**

   406

 *  e1000e_read_phy_reg_igp - Read igp PHY register

   407

 *  @hw: pointer to the HW structure

   408

 *  @offset: register offset to be read

   409

 *  @data: pointer to the read data

   410

 *

   411

 *  Acquires semaphore then reads the PHY register at offset and stores the

   412

 *  retrieved information in data.

   413

 *  Release the acquired semaphore before exiting.

   414

 **/

   415

s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)

   416

{

   417

	return __e1000e_read_phy_reg_igp(hw, offset, data, false);

   418

}

   419

   420

/**

   421

 *  e1000e_read_phy_reg_igp_locked - Read igp PHY register

   422

 *  @hw: pointer to the HW structure

   423

 *  @offset: register offset to be read

   424

 *  @data: pointer to the read data

   425

 *

   426

 *  Reads the PHY register at offset and stores the retrieved information

   427

 *  in data.  Assumes semaphore already acquired.

   428

 **/

   429

s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)

   430

{

   431

	return __e1000e_read_phy_reg_igp(hw, offset, data, true);

   432

}

   433

   434

/**

   435

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   436

 *  @hw: pointer to the HW structure

   437

 *  @offset: register offset to write to

   438

 *  @data: data to write at register offset

   439

 *  @locked: semaphore has already been acquired or not

   440

 *

   441

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   442

 *  at the offset.  Release any acquired semaphores before exiting.

   443

 **/

   444

static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,

   445

                                     bool locked)

   446

{

   447

	s32 ret_val = 0;

   448

   449

	if (!locked) {

   450

		if (!hw->phy.ops.acquire)

   451

			return 0;

   452

   453

		ret_val = hw->phy.ops.acquire(hw);

   454

		if (ret_val)

   455

			return ret_val;

   456

	}

   457

   458

	if (offset > MAX_PHY_MULTI_PAGE_REG)

   459

		ret_val = e1000e_write_phy_reg_mdic(hw,

   460

						    IGP01E1000_PHY_PAGE_SELECT,

   461

						    (u16)offset);

   462

	if (!ret_val)

   463

		ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &

   464

							offset,

   465

						    data);

   466

	if (!locked)

   467

		hw->phy.ops.release(hw);

   468

   469

	return ret_val;

   470

}

   471

   472

/**

   473

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   474

 *  @hw: pointer to the HW structure

   475

 *  @offset: register offset to write to

   476

 *  @data: data to write at register offset

   477

 *

   478

 *  Acquires semaphore then writes the data to PHY register

   479

 *  at the offset.  Release any acquired semaphores before exiting.

   480

 **/

   481

s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)

   482

{

   483

	return __e1000e_write_phy_reg_igp(hw, offset, data, false);

   484

}

   485

   486

/**

   487

 *  e1000e_write_phy_reg_igp_locked - Write igp PHY register

   488

 *  @hw: pointer to the HW structure

   489

 *  @offset: register offset to write to

   490

 *  @data: data to write at register offset

   491

 *

   492

 *  Writes the data to PHY register at the offset.

   493

 *  Assumes semaphore already acquired.

   494

 **/

   495

s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)

   496

{

   497

	return __e1000e_write_phy_reg_igp(hw, offset, data, true);

   498

}

   499

   500

/**

   501

 *  __e1000_read_kmrn_reg - Read kumeran register

   502

 *  @hw: pointer to the HW structure

   503

 *  @offset: register offset to be read

   504

 *  @data: pointer to the read data

   505

 *  @locked: semaphore has already been acquired or not

   506

 *

   507

 *  Acquires semaphore, if necessary.  Then reads the PHY register at offset

   508

 *  using the kumeran interface.  The information retrieved is stored in data.

   509

 *  Release any acquired semaphores before exiting.

   510

 **/

   511

static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,

   512

                                 bool locked)

   513

{

   514

	u32 kmrnctrlsta;

   515

   516

	if (!locked) {

   517

		s32 ret_val = 0;

   518

   519

		if (!hw->phy.ops.acquire)

   520

			return 0;

   521

   522

		ret_val = hw->phy.ops.acquire(hw);

   523

		if (ret_val)

   524

			return ret_val;

   525

	}

   526

   527

	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &

   528

		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;

   529

	ew32(KMRNCTRLSTA, kmrnctrlsta);