1

/*

     2

     3

	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

     4

     5

	Maintained by Jeff Garzik <jgarzik@pobox.com>

     6

	Copyright 2000-2002 Jeff Garzik

     7

     8

	Much code comes from Donald Becker's rtl8139.c driver,

     9

	versions 1.13 and older.  This driver was originally based

    10

	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    11

    12

	-----<snip>-----

    13

    14

        	Written 1997-2001 by Donald Becker.

    15

		This software may be used and distributed according to the

    16

		terms of the GNU General Public License (GPL), incorporated

    17

		herein by reference.  Drivers based on or derived from this

    18

		code fall under the GPL and must retain the authorship,

    19

		copyright and license notice.  This file is not a complete

    20

		program and may only be used when the entire operating

    21

		system is licensed under the GPL.

    22

    23

		This driver is for boards based on the RTL8129 and RTL8139

    24

		PCI ethernet chips.

    25

    26

		The author may be reached as becker@scyld.com, or C/O Scyld

    27

		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    28

		MD 21403

    29

    30

		Support and updates available at

    31

		http://www.scyld.com/network/rtl8139.html

    32

    33

		Twister-tuning table provided by Kinston

    34

		<shangh@realtek.com.tw>.

    35

    36

	-----<snip>-----

    37

    38

	This software may be used and distributed according to the terms

    39

	of the GNU General Public License, incorporated herein by reference.

    40

    41

	Contributors:

    42

    43

		Donald Becker - he wrote the original driver, kudos to him!

    44

		(but please don't e-mail him for support, this isn't his driver)

    45

    46

		Tigran Aivazian - bug fixes, skbuff free cleanup

    47

    48

		Martin Mares - suggestions for PCI cleanup

    49

    50

		David S. Miller - PCI DMA and softnet updates

    51

    52

		Ernst Gill - fixes ported from BSD driver

    53

    54

		Daniel Kobras - identified specific locations of

    55

			posted MMIO write bugginess

    56

    57

		Gerard Sharp - bug fix, testing and feedback

    58

    59

		David Ford - Rx ring wrap fix

    60

    61

		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    62

		to find and fix a crucial bug on older chipsets.

    63

    64

		Donald Becker/Chris Butterworth/Marcus Westergren -

    65

		Noticed various Rx packet size-related buglets.

    66

    67

		Santiago Garcia Mantinan - testing and feedback

    68

    69

		Jens David - 2.2.x kernel backports

    70

    71

		Martin Dennett - incredibly helpful insight on undocumented

    72

		features of the 8139 chips

    73

    74

		Jean-Jacques Michel - bug fix

    75

    76

		Tobias Ringström - Rx interrupt status checking suggestion

    77

    78

		Andrew Morton - Clear blocked signals, avoid

    79

		buffer overrun setting current->comm.

    80

    81

		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

    82

    83

		Robert Kuebel - Save kernel thread from dying on any signal.

    84

    85

	Submitting bug reports:

    86

    87

		"rtl8139-diag -mmmaaavvveefN" output

    88

		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

    89

    90

*/

    91

    92

#define DRV_NAME	"8139too"

    93

#define DRV_VERSION	"0.9.28"

    94

    95

    96

#include <linux/module.h>

    97

#include <linux/kernel.h>

    98

#include <linux/compiler.h>

    99

#include <linux/pci.h>

   100

#include <linux/init.h>

   101

#include <linux/ioport.h>

   102

#include <linux/netdevice.h>

   103

#include <linux/etherdevice.h>

   104

#include <linux/rtnetlink.h>

   105

#include <linux/delay.h>

   106

#include <linux/ethtool.h>

   107

#include <linux/mii.h>

   108

#include <linux/completion.h>

   109

#include <linux/crc32.h>

   110

#include <asm/io.h>

   111

#include <asm/uaccess.h>

   112

#include <asm/irq.h>

   113

   114

#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   115

#define PFX DRV_NAME ": "

   116

   117

/* Default Message level */

   118

#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   119

                                 NETIF_MSG_PROBE  | \

   120

                                 NETIF_MSG_LINK)

   121

   122

   123

/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   124

#ifdef CONFIG_8139TOO_PIO

   125

#define USE_IO_OPS 1

   126

#endif

   127

   128

/* define to 1, 2 or 3 to enable copious debugging info */

   129

#define RTL8139_DEBUG 0

   130

   131

/* define to 1 to disable lightweight runtime debugging checks */

   132

#undef RTL8139_NDEBUG

   133

   134

   135

#if RTL8139_DEBUG

   136

/* note: prints function name for you */

   137

#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   138

#else

   139

#  define DPRINTK(fmt, args...)

   140

#endif

   141

   142

#ifdef RTL8139_NDEBUG

   143

#  define assert(expr) do {} while (0)

   144

#else

   145

#  define assert(expr) \

   146

        if(unlikely(!(expr))) {				        \

   147

        printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   148

        #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   149

        }

   150

#endif

   151

   152

   153

/* A few user-configurable values. */

   154

/* media options */

   155

#define MAX_UNITS 8

   156

static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   157

static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   158

   159

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   160

   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   161

static int multicast_filter_limit = 32;

   162

   163

/* bitmapped message enable number */

   164

static int debug = -1;

   165

   166

/*

   167

 * Receive ring size

   168

 * Warning: 64K ring has hardware issues and may lock up.

   169

 */

   170

#if defined(CONFIG_SH_DREAMCAST)

   171

#define RX_BUF_IDX 0	/* 8K ring */

   172

#else

   173

#define RX_BUF_IDX	2	/* 32K ring */

   174

#endif

   175

#define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   176

#define RX_BUF_PAD	16

   177

#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   178

   179

#if RX_BUF_LEN == 65536

   180

#define RX_BUF_TOT_LEN	RX_BUF_LEN

   181

#else

   182

#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   183

#endif

   184

   185

/* Number of Tx descriptor registers. */

   186

#define NUM_TX_DESC	4

   187

   188

/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   189

#define MAX_ETH_FRAME_SIZE	1536

   190

   191

/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   192

#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   193

#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   194

   195

/* PCI Tuning Parameters

   196

   Threshold is bytes transferred to chip before transmission starts. */

   197

#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   198

   199

/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   200

#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   201

#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   202

#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   203

#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   204

   205

/* Operational parameters that usually are not changed. */

   206

/* Time in jiffies before concluding the transmitter is hung. */

   207

#define TX_TIMEOUT  (6*HZ)

   208

   209

   210

enum {

   211

	HAS_MII_XCVR = 0x010000,

   212

	HAS_CHIP_XCVR = 0x020000,

   213

	HAS_LNK_CHNG = 0x040000,

   214

};

   215

   216

#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   217

#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   218

#define RTL_MIN_IO_SIZE 0x80

   219

#define RTL8139B_IO_SIZE 256

   220

   221

#define RTL8129_CAPS	HAS_MII_XCVR

   222

#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   223

   224

typedef enum {

   225

	RTL8139 = 0,

   226

	RTL8129,

   227

} board_t;

   228

   229

   230

/* indexed by board_t, above */

   231

static const struct {

   232

	const char *name;

   233

	u32 hw_flags;

   234

} board_info[] __devinitdata = {

   235

	{ "RealTek RTL8139", RTL8139_CAPS },

   236

	{ "RealTek RTL8129", RTL8129_CAPS },

   237

};

   238

   239

   240

static struct pci_device_id rtl8139_pci_tbl[] = {

   241

	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   242

	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   243

	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   244

	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   245

	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   246

	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   247

	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   248

	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   249

	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   250

	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   251

	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   252

	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   253

	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   254

	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   255

	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   256

	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   257

	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   258

	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   259

	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   260

   261

#ifdef CONFIG_SH_SECUREEDGE5410

   262

	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   263

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   264

#endif

   265

#ifdef CONFIG_8139TOO_8129

   266

	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   267

#endif

   268

   269

	/* some crazy cards report invalid vendor ids like

   270

	 * 0x0001 here.  The other ids are valid and constant,

   271

	 * so we simply don't match on the main vendor id.

   272

	 */

   273

	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   274

	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   275

	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   276

   277

	{0,}

   278

};

   279

MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   280

   281

static struct {

   282

	const char str[ETH_GSTRING_LEN];

   283

} ethtool_stats_keys[] = {

   284

	{ "early_rx" },

   285

	{ "tx_buf_mapped" },

   286

	{ "tx_timeouts" },

   287

	{ "rx_lost_in_ring" },

   288

};

   289

   290

/* The rest of these values should never change. */

   291

   292

/* Symbolic offsets to registers. */

   293

enum RTL8139_registers {

   294

	MAC0		= 0,	 /* Ethernet hardware address. */

   295

	MAR0		= 8,	 /* Multicast filter. */

   296

	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   297

	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   298

	RxBuf		= 0x30,

   299

	ChipCmd		= 0x37,

   300

	RxBufPtr	= 0x38,

   301

	RxBufAddr	= 0x3A,

   302

	IntrMask	= 0x3C,

   303

	IntrStatus	= 0x3E,

   304

	TxConfig	= 0x40,

   305

	RxConfig	= 0x44,

   306

	Timer		= 0x48,	 /* A general-purpose counter. */

   307

	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   308

	Cfg9346		= 0x50,

   309

	Config0		= 0x51,

   310

	Config1		= 0x52,

   311

	FlashReg	= 0x54,

   312

	MediaStatus	= 0x58,

   313

	Config3		= 0x59,

   314

	Config4		= 0x5A,	 /* absent on RTL-8139A */

   315

	HltClk		= 0x5B,

   316

	MultiIntr	= 0x5C,

   317

	TxSummary	= 0x60,

   318

	BasicModeCtrl	= 0x62,

   319

	BasicModeStatus	= 0x64,

   320

	NWayAdvert	= 0x66,

   321

	NWayLPAR	= 0x68,

   322

	NWayExpansion	= 0x6A,

   323

	/* Undocumented registers, but required for proper operation. */

   324

	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   325

	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   326

	PARA78		= 0x78,

   327

	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   328

	Config5		= 0xD8,	 /* absent on RTL-8139A */

   329

};

   330

   331

enum ClearBitMasks {

   332

	MultiIntrClear	= 0xF000,

   333

	ChipCmdClear	= 0xE2,

   334

	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   335

};

   336

   337

enum ChipCmdBits {

   338

	CmdReset	= 0x10,

   339

	CmdRxEnb	= 0x08,

   340

	CmdTxEnb	= 0x04,

   341

	RxBufEmpty	= 0x01,

   342

};

   343

   344

/* Interrupt register bits, using my own meaningful names. */

   345

enum IntrStatusBits {

   346

	PCIErr		= 0x8000,

   347

	PCSTimeout	= 0x4000,

   348

	RxFIFOOver	= 0x40,

   349

	RxUnderrun	= 0x20,

   350

	RxOverflow	= 0x10,

   351

	TxErr		= 0x08,

   352

	TxOK		= 0x04,

   353

	RxErr		= 0x02,

   354

	RxOK		= 0x01,

   355

   356

	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   357

};

   358

   359

enum TxStatusBits {

   360

	TxHostOwns	= 0x2000,

   361

	TxUnderrun	= 0x4000,

   362

	TxStatOK	= 0x8000,

   363

	TxOutOfWindow	= 0x20000000,

   364

	TxAborted	= 0x40000000,

   365

	TxCarrierLost	= 0x80000000,

   366

};

   367

enum RxStatusBits {

   368

	RxMulticast	= 0x8000,

   369

	RxPhysical	= 0x4000,

   370

	RxBroadcast	= 0x2000,

   371

	RxBadSymbol	= 0x0020,

   372

	RxRunt		= 0x0010,

   373

	RxTooLong	= 0x0008,

   374

	RxCRCErr	= 0x0004,

   375

	RxBadAlign	= 0x0002,

   376

	RxStatusOK	= 0x0001,

   377

};

   378

   379

/* Bits in RxConfig. */

   380

enum rx_mode_bits {

   381

	AcceptErr	= 0x20,

   382

	AcceptRunt	= 0x10,

   383

	AcceptBroadcast	= 0x08,

   384

	AcceptMulticast	= 0x04,

   385

	AcceptMyPhys	= 0x02,

   386

	AcceptAllPhys	= 0x01,

   387

};

   388

   389

/* Bits in TxConfig. */

   390

enum tx_config_bits {

   391

        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   392

        TxIFGShift	= 24,

   393

        TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   394

        TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   395

        TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   396

        TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   397

   398

	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   399

	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   400

	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   401

	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   402

	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   403

   404

	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   405

};

   406

   407

/* Bits in Config1 */

   408

enum Config1Bits {

   409

	Cfg1_PM_Enable	= 0x01,

   410

	Cfg1_VPD_Enable	= 0x02,

   411

	Cfg1_PIO	= 0x04,

   412

	Cfg1_MMIO	= 0x08,

   413

	LWAKE		= 0x10,		/* not on 8139, 8139A */

   414

	Cfg1_Driver_Load = 0x20,

   415

	Cfg1_LED0	= 0x40,

   416

	Cfg1_LED1	= 0x80,

   417

	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   418

	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   419

};

   420

   421

/* Bits in Config3 */

   422

enum Config3Bits {

   423

	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   424

	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   425

	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   426

	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   427

	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   428

	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   429

	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   430

	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   431

};

   432

   433

/* Bits in Config4 */

   434

enum Config4Bits {

   435

	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   436

};

   437

   438

/* Bits in Config5 */

   439

enum Config5Bits {

   440

	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   441

	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   442

	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   443

	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   444

	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   445

	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   446

	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   447

};

   448

   449

enum RxConfigBits {

   450

	/* rx fifo threshold */

   451

	RxCfgFIFOShift	= 13,

   452

	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   453

   454

	/* Max DMA burst */

   455

	RxCfgDMAShift	= 8,

   456

	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   457

   458

	/* rx ring buffer length */

   459

	RxCfgRcv8K	= 0,

   460

	RxCfgRcv16K	= (1 << 11),

   461

	RxCfgRcv32K	= (1 << 12),

   462

	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   463

   464

	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   465

	RxNoWrap	= (1 << 7),

   466

};

   467

   468

/* Twister tuning parameters from RealTek.

   469

   Completely undocumented, but required to tune bad links on some boards. */

   470

enum CSCRBits {

   471

	CSCR_LinkOKBit		= 0x0400,

   472

	CSCR_LinkChangeBit	= 0x0800,

   473

	CSCR_LinkStatusBits	= 0x0f000,

   474

	CSCR_LinkDownOffCmd	= 0x003c0,

   475

	CSCR_LinkDownCmd	= 0x0f3c0,

   476

};

   477

   478

enum Cfg9346Bits {

   479

	Cfg9346_Lock	= 0x00,

   480

	Cfg9346_Unlock	= 0xC0,

   481

};

   482

   483

typedef enum {

   484

	CH_8139	= 0,

   485

	CH_8139_K,

   486

	CH_8139A,

   487

	CH_8139A_G,

   488

	CH_8139B,

   489

	CH_8130,

   490

	CH_8139C,

   491

	CH_8100,

   492

	CH_8100B_8139D,

   493

	CH_8101,

   494

} chip_t;

   495

   496

enum chip_flags {

   497

	HasHltClk	= (1 << 0),

   498

	HasLWake	= (1 << 1),

   499

};

   500

   501

#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   502

	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   503

#define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   504

   505

/* directly indexed by chip_t, above */

   506

static const struct {

   507

	const char *name;

   508

	u32 version; /* from RTL8139C/RTL8139D docs */

   509

	u32 flags;

   510

} rtl_chip_info[] = {

   511

	{ "RTL-8139",

   512

	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   513

	  HasHltClk,

   514

	},

   515

   516

	{ "RTL-8139 rev K",

   517

	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   518

	  HasHltClk,

   519

	},

   520

   521

	{ "RTL-8139A",

   522

	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   523

	  HasHltClk, /* XXX undocumented? */

   524

	},

   525

   526

	{ "RTL-8139A rev G",

   527

	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   528

	  HasHltClk, /* XXX undocumented? */

   529

	},