1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2009 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

#include "e1000-2.6.33-ethercat.h"

    30

    31

enum e1000_mng_mode {

    32

	e1000_mng_mode_none = 0,

    33

	e1000_mng_mode_asf,

    34

	e1000_mng_mode_pt,

    35

	e1000_mng_mode_ipmi,

    36

	e1000_mng_mode_host_if_only

    37

};

    38

    39

#define E1000_FACTPS_MNGCG		0x20000000

    40

    41

/* Intel(R) Active Management Technology signature */

    42

#define E1000_IAMT_SIGNATURE		0x544D4149

    43

    44

/**

    45

 *  e1000e_get_bus_info_pcie - Get PCIe bus information

    46

 *  @hw: pointer to the HW structure

    47

 *

    48

 *  Determines and stores the system bus information for a particular

    49

 *  network interface.  The following bus information is determined and stored:

    50

 *  bus speed, bus width, type (PCIe), and PCIe function.

    51

 **/

    52

s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)

    53

{

    54

	struct e1000_bus_info *bus = &hw->bus;

    55

	struct e1000_adapter *adapter = hw->adapter;

    56

	u32 status;

    57

	u16 pcie_link_status, pci_header_type, cap_offset;

    58

    59

	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);

    60

	if (!cap_offset) {

    61

		bus->width = e1000_bus_width_unknown;

    62

	} else {

    63

		pci_read_config_word(adapter->pdev,

    64

				     cap_offset + PCIE_LINK_STATUS,

    65

				     &pcie_link_status);

    66

		bus->width = (enum e1000_bus_width)((pcie_link_status &

    67

						     PCIE_LINK_WIDTH_MASK) >>

    68

						    PCIE_LINK_WIDTH_SHIFT);

    69

	}

    70

    71

	pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,

    72

			     &pci_header_type);

    73

	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {

    74

		status = er32(STATUS);

    75

		bus->func = (status & E1000_STATUS_FUNC_MASK)

    76

			    >> E1000_STATUS_FUNC_SHIFT;

    77

	} else {

    78

		bus->func = 0;

    79

	}

    80

    81

	return 0;

    82

}

    83

    84

/**

    85

 *  e1000_clear_vfta_generic - Clear VLAN filter table

    86

 *  @hw: pointer to the HW structure

    87

 *

    88

 *  Clears the register array which contains the VLAN filter table by

    89

 *  setting all the values to 0.

    90

 **/

    91

void e1000_clear_vfta_generic(struct e1000_hw *hw)

    92

{

    93

	u32 offset;

    94

    95

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

    96

		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);

    97

		e1e_flush();

    98

	}

    99

}

   100

   101

/**

   102

 *  e1000_write_vfta_generic - Write value to VLAN filter table

   103

 *  @hw: pointer to the HW structure

   104

 *  @offset: register offset in VLAN filter table

   105

 *  @value: register value written to VLAN filter table

   106

 *

   107

 *  Writes value at the given offset in the register array which stores

   108

 *  the VLAN filter table.

   109

 **/

   110

void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)

   111

{

   112

	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);

   113

	e1e_flush();

   114

}

   115

   116

/**

   117

 *  e1000e_init_rx_addrs - Initialize receive address's

   118

 *  @hw: pointer to the HW structure

   119

 *  @rar_count: receive address registers

   120

 *

   121

 *  Setups the receive address registers by setting the base receive address

   122

 *  register to the devices MAC address and clearing all the other receive

   123

 *  address registers to 0.

   124

 **/

   125

void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   126

{

   127

	u32 i;

   128

	u8 mac_addr[ETH_ALEN] = {0};

   129

   130

	/* Setup the receive address */

   131

	e_dbg("Programming MAC Address into RAR[0]\n");

   132

   133

	e1000e_rar_set(hw, hw->mac.addr, 0);

   134

   135

	/* Zero out the other (rar_entry_count - 1) receive addresses */

   136

	e_dbg("Clearing RAR[1-%u]\n", rar_count-1);

   137

	for (i = 1; i < rar_count; i++)

   138

		e1000e_rar_set(hw, mac_addr, i);

   139

}

   140

   141

/**

   142

 *  e1000e_rar_set - Set receive address register

   143

 *  @hw: pointer to the HW structure

   144

 *  @addr: pointer to the receive address

   145

 *  @index: receive address array register

   146

 *

   147

 *  Sets the receive address array register at index to the address passed

   148

 *  in by addr.

   149

 **/

   150

void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)

   151

{

   152

	u32 rar_low, rar_high;

   153

   154

	/*

   155

	 * HW expects these in little endian so we reverse the byte order

   156

	 * from network order (big endian) to little endian

   157

	 */

   158

	rar_low = ((u32) addr[0] |

   159

		   ((u32) addr[1] << 8) |

   160

		    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));

   161

   162

	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

   163

   164

	/* If MAC address zero, no need to set the AV bit */

   165

	if (rar_low || rar_high)

   166

		rar_high |= E1000_RAH_AV;

   167

   168

	/*

   169

	 * Some bridges will combine consecutive 32-bit writes into

   170

	 * a single burst write, which will malfunction on some parts.

   171

	 * The flushes avoid this.

   172

	 */

   173

	ew32(RAL(index), rar_low);

   174

	e1e_flush();

   175

	ew32(RAH(index), rar_high);

   176

	e1e_flush();

   177

}

   178

   179

/**

   180

 *  e1000_hash_mc_addr - Generate a multicast hash value

   181

 *  @hw: pointer to the HW structure

   182

 *  @mc_addr: pointer to a multicast address

   183

 *

   184

 *  Generates a multicast address hash value which is used to determine

   185

 *  the multicast filter table array address and new table value.  See

   186

 *  e1000_mta_set_generic()

   187

 **/

   188

static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   189

{

   190

	u32 hash_value, hash_mask;

   191

	u8 bit_shift = 0;

   192

   193

	/* Register count multiplied by bits per register */

   194

	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   195

   196

	/*

   197

	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts

   198

	 * where 0xFF would still fall within the hash mask.

   199

	 */

   200

	while (hash_mask >> bit_shift != 0xFF)

   201

		bit_shift++;

   202

   203

	/*

   204

	 * The portion of the address that is used for the hash table

   205

	 * is determined by the mc_filter_type setting.

   206

	 * The algorithm is such that there is a total of 8 bits of shifting.

   207

	 * The bit_shift for a mc_filter_type of 0 represents the number of

   208

	 * left-shifts where the MSB of mc_addr[5] would still fall within

   209

	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   210

	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   211

	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   212

	 * cases are a variation of this algorithm...essentially raising the

   213

	 * number of bits to shift mc_addr[5] left, while still keeping the

   214

	 * 8-bit shifting total.

   215

	 *

   216

	 * For example, given the following Destination MAC Address and an

   217

	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   218

	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   219

	 * values resulting from each mc_filter_type...

   220

	 * [0] [1] [2] [3] [4] [5]

   221

	 * 01  AA  00  12  34  56

   222

	 * LSB		 MSB

   223

	 *

   224

	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   225

	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   226

	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   227

	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   228

	 */

   229

	switch (hw->mac.mc_filter_type) {

   230

	default:

   231

	case 0:

   232

		break;

   233

	case 1:

   234

		bit_shift += 1;

   235

		break;

   236

	case 2:

   237

		bit_shift += 2;

   238

		break;

   239

	case 3:

   240

		bit_shift += 4;

   241

		break;

   242

	}

   243

   244

	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   245

				  (((u16) mc_addr[5]) << bit_shift)));

   246

   247

	return hash_value;

   248

}

   249

   250

/**

   251

 *  e1000e_update_mc_addr_list_generic - Update Multicast addresses

   252

 *  @hw: pointer to the HW structure

   253

 *  @mc_addr_list: array of multicast addresses to program

   254

 *  @mc_addr_count: number of multicast addresses to program

   255

 *  @rar_used_count: the first RAR register free to program

   256

 *  @rar_count: total number of supported Receive Address Registers

   257

 *

   258

 *  Updates the Receive Address Registers and Multicast Table Array.

   259

 *  The caller must have a packed mc_addr_list of multicast addresses.

   260

 *  The parameter rar_count will usually be hw->mac.rar_entry_count

   261

 *  unless there are workarounds that change this.

   262

 **/

   263

void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,

   264

					u8 *mc_addr_list, u32 mc_addr_count,

   265

					u32 rar_used_count, u32 rar_count)

   266

{

   267

	u32 i;

   268

	u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);

   269

   270

	if (!mcarray) {

   271

		printk(KERN_ERR "multicast array memory allocation failed\n");

   272

		return;

   273

	}

   274

   275

	/*

   276

	 * Load the first set of multicast addresses into the exact

   277

	 * filters (RAR).  If there are not enough to fill the RAR

   278

	 * array, clear the filters.

   279

	 */

   280

	for (i = rar_used_count; i < rar_count; i++) {

   281

		if (mc_addr_count) {

   282

			e1000e_rar_set(hw, mc_addr_list, i);

   283

			mc_addr_count--;

   284

			mc_addr_list += ETH_ALEN;

   285

		} else {

   286

			E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);

   287

			e1e_flush();

   288

			E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);

   289

			e1e_flush();

   290

		}

   291

	}

   292

   293

	/* Load any remaining multicast addresses into the hash table. */

   294

	for (; mc_addr_count > 0; mc_addr_count--) {

   295

		u32 hash_value, hash_reg, hash_bit, mta;

   296

		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);

   297

		e_dbg("Hash value = 0x%03X\n", hash_value);

   298

		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   299

		hash_bit = hash_value & 0x1F;

   300

		mta = (1 << hash_bit);

   301

		mcarray[hash_reg] |= mta;

   302

		mc_addr_list += ETH_ALEN;

   303

	}

   304

   305

	/* write the hash table completely */

   306

	for (i = 0; i < hw->mac.mta_reg_count; i++)

   307

		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);

   308

   309

	e1e_flush();

   310

	kfree(mcarray);

   311

}

   312

   313

/**

   314

 *  e1000e_clear_hw_cntrs_base - Clear base hardware counters

   315

 *  @hw: pointer to the HW structure

   316

 *

   317

 *  Clears the base hardware counters by reading the counter registers.

   318

 **/

   319

void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)

   320

{

   321

	er32(CRCERRS);

   322

	er32(SYMERRS);

   323

	er32(MPC);

   324

	er32(SCC);

   325

	er32(ECOL);

   326

	er32(MCC);

   327

	er32(LATECOL);

   328

	er32(COLC);

   329

	er32(DC);

   330

	er32(SEC);

   331

	er32(RLEC);

   332

	er32(XONRXC);

   333

	er32(XONTXC);

   334

	er32(XOFFRXC);

   335

	er32(XOFFTXC);

   336

	er32(FCRUC);

   337

	er32(GPRC);

   338

	er32(BPRC);

   339

	er32(MPRC);

   340

	er32(GPTC);

   341

	er32(GORCL);

   342

	er32(GORCH);

   343

	er32(GOTCL);

   344

	er32(GOTCH);

   345

	er32(RNBC);

   346

	er32(RUC);

   347

	er32(RFC);

   348

	er32(ROC);

   349

	er32(RJC);

   350

	er32(TORL);

   351

	er32(TORH);

   352

	er32(TOTL);

   353

	er32(TOTH);

   354

	er32(TPR);

   355

	er32(TPT);

   356

	er32(MPTC);

   357

	er32(BPTC);

   358

}

   359

   360

/**

   361

 *  e1000e_check_for_copper_link - Check for link (Copper)

   362

 *  @hw: pointer to the HW structure

   363

 *

   364

 *  Checks to see of the link status of the hardware has changed.  If a

   365

 *  change in link status has been detected, then we read the PHY registers

   366

 *  to get the current speed/duplex if link exists.

   367

 **/

   368

s32 e1000e_check_for_copper_link(struct e1000_hw *hw)

   369

{

   370

	struct e1000_mac_info *mac = &hw->mac;

   371

	s32 ret_val;

   372

	bool link;

   373

   374

	/*

   375

	 * We only want to go out to the PHY registers to see if Auto-Neg

   376

	 * has completed and/or if our link status has changed.  The

   377

	 * get_link_status flag is set upon receiving a Link Status

   378

	 * Change or Rx Sequence Error interrupt.

   379

	 */

   380

	if (!mac->get_link_status)

   381

		return 0;

   382

   383

	/*

   384

	 * First we want to see if the MII Status Register reports

   385

	 * link.  If so, then we want to get the current speed/duplex

   386

	 * of the PHY.

   387

	 */

   388

	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   389

	if (ret_val)

   390

		return ret_val;

   391

   392

	if (!link)

   393

		return ret_val; /* No link detected */

   394

   395

	mac->get_link_status = false;

   396

   397

	/*

   398

	 * Check if there was DownShift, must be checked

   399

	 * immediately after link-up

   400

	 */

   401

	e1000e_check_downshift(hw);

   402

   403

	/*

   404

	 * If we are forcing speed/duplex, then we simply return since

   405

	 * we have already determined whether we have link or not.

   406

	 */

   407

	if (!mac->autoneg) {

   408

		ret_val = -E1000_ERR_CONFIG;

   409

		return ret_val;

   410

	}

   411

   412

	/*

   413

	 * Auto-Neg is enabled.  Auto Speed Detection takes care

   414

	 * of MAC speed/duplex configuration.  So we only need to

   415

	 * configure Collision Distance in the MAC.

   416

	 */

   417

	e1000e_config_collision_dist(hw);

   418

   419

	/*

   420

	 * Configure Flow Control now that Auto-Neg has completed.

   421

	 * First, we need to restore the desired flow control

   422

	 * settings because we may have had to re-autoneg with a

   423

	 * different link partner.

   424

	 */

   425

	ret_val = e1000e_config_fc_after_link_up(hw);

   426

	if (ret_val) {

   427

		e_dbg("Error configuring flow control\n");

   428

	}

   429

   430

	return ret_val;

   431

}

   432

   433

/**

   434

 *  e1000e_check_for_fiber_link - Check for link (Fiber)

   435

 *  @hw: pointer to the HW structure

   436

 *

   437

 *  Checks for link up on the hardware.  If link is not up and we have

   438

 *  a signal, then we need to force link up.

   439

 **/

   440

s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)

   441

{

   442

	struct e1000_mac_info *mac = &hw->mac;

   443

	u32 rxcw;

   444

	u32 ctrl;

   445

	u32 status;

   446

	s32 ret_val;

   447

   448

	ctrl = er32(CTRL);

   449

	status = er32(STATUS);

   450

	rxcw = er32(RXCW);

   451

   452

	/*

   453

	 * If we don't have link (auto-negotiation failed or link partner

   454

	 * cannot auto-negotiate), the cable is plugged in (we have signal),

   455

	 * and our link partner is not trying to auto-negotiate with us (we

   456

	 * are receiving idles or data), we need to force link up. We also

   457

	 * need to give auto-negotiation time to complete, in case the cable

   458

	 * was just plugged in. The autoneg_failed flag does this.

   459

	 */

   460

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   461

	if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&

   462

	    (!(rxcw & E1000_RXCW_C))) {

   463

		if (mac->autoneg_failed == 0) {

   464

			mac->autoneg_failed = 1;

   465

			return 0;

   466

		}

   467

		e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");

   468

   469

		/* Disable auto-negotiation in the TXCW register */

   470

		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   471

   472

		/* Force link-up and also force full-duplex. */

   473

		ctrl = er32(CTRL);

   474

		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   475

		ew32(CTRL, ctrl);

   476

   477

		/* Configure Flow Control after forcing link up. */

   478

		ret_val = e1000e_config_fc_after_link_up(hw);

   479

		if (ret_val) {

   480

			e_dbg("Error configuring flow control\n");

   481

			return ret_val;

   482

		}

   483

	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

   484

		/*

   485

		 * If we are forcing link and we are receiving /C/ ordered

   486

		 * sets, re-enable auto-negotiation in the TXCW register

   487

		 * and disable forced link in the Device Control register

   488

		 * in an attempt to auto-negotiate with our link partner.

   489

		 */

   490

		e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");

   491

		ew32(TXCW, mac->txcw);

   492

		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

   493

   494

		mac->serdes_has_link = true;

   495

	}

   496

   497

	return 0;

   498

}

   499

   500

/**

   501

 *  e1000e_check_for_serdes_link - Check for link (Serdes)

   502

 *  @hw: pointer to the HW structure

   503

 *

   504

 *  Checks for link up on the hardware.  If link is not up and we have

   505

 *  a signal, then we need to force link up.

   506

 **/

   507

s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)

   508

{

   509

	struct e1000_mac_info *mac = &hw->mac;

   510

	u32 rxcw;

   511

	u32 ctrl;

   512

	u32 status;

   513

	s32 ret_val;

   514

   515

	ctrl = er32(CTRL);

   516

	status = er32(STATUS);

   517

	rxcw = er32(RXCW);

   518

   519

	/*

   520

	 * If we don't have link (auto-negotiation failed or link partner

   521

	 * cannot auto-negotiate), and our link partner is not trying to

   522

	 * auto-negotiate with us (we are receiving idles or data),

   523

	 * we need to force link up. We also need to give auto-negotiation

   524

	 * time to complete.

   525

	 */

   526

	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   527

	if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {

   528

		if (mac->autoneg_failed == 0) {

   529

			mac->autoneg_failed = 1;

   530

			return 0;