devices/e1000e/phy-3.14-ethercat.h
author Dave Page <dave.page@gleeble.com>
Mon, 16 Dec 2013 14:18:30 -0500
changeset 2601 9b36a16271e6
parent 2589 2b9c78543663
permissions -rw-r--r--
Fix spurious FoE write timeout
2589
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/*******************************************************************************
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  Intel PRO/1000 Linux driver
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  Copyright(c) 1999 - 2013 Intel Corporation.
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  This program is free software; you can redistribute it and/or modify it
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  under the terms and conditions of the GNU General Public License,
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  version 2, as published by the Free Software Foundation.
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  This program is distributed in the hope it will be useful, but WITHOUT
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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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  more details.
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  You should have received a copy of the GNU General Public License along with
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  this program; if not, write to the Free Software Foundation, Inc.,
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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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  The full GNU General Public License is included in this distribution in
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  the file called "COPYING".
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  Contact Information:
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  Linux NICS <linux.nics@intel.com>
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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000E_PHY_H_
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#define _E1000E_PHY_H_
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s32 e1000e_check_downshift(struct e1000_hw *hw);
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s32 e1000_check_polarity_m88(struct e1000_hw *hw);
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s32 e1000_check_polarity_igp(struct e1000_hw *hw);
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s32 e1000_check_polarity_ife(struct e1000_hw *hw);
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s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
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s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
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s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
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s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
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s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
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s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
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s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
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s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
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s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
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s32 e1000e_get_phy_id(struct e1000_hw *hw);
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s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
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s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
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s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
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s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
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void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
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s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
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s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
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s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
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s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
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s32 e1000e_setup_copper_link(struct e1000_hw *hw);
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s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
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				u32 usec_interval, bool *success);
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s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
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enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
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s32 e1000e_determine_phy_address(struct e1000_hw *hw);
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s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
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s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
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s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
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void e1000_power_up_phy_copper(struct e1000_hw *hw);
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void e1000_power_down_phy_copper(struct e1000_hw *hw);
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s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
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s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
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s32 e1000_check_polarity_82577(struct e1000_hw *hw);
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s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
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s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
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s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
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#define E1000_MAX_PHY_ADDR		8
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/* IGP01E1000 Specific Registers */
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#define IGP01E1000_PHY_PORT_CONFIG	0x10	/* Port Config */
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#define IGP01E1000_PHY_PORT_STATUS	0x11	/* Status */
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#define IGP01E1000_PHY_PORT_CTRL	0x12	/* Control */
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#define IGP01E1000_PHY_LINK_HEALTH	0x13	/* PHY Link Health */
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#define IGP02E1000_PHY_POWER_MGMT	0x19	/* Power Management */
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#define IGP01E1000_PHY_PAGE_SELECT	0x1F	/* Page Select */
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#define BM_PHY_PAGE_SELECT		22	/* Page Select for BM */
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#define IGP_PAGE_SHIFT			5
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#define PHY_REG_MASK			0x1F
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/* BM/HV Specific Registers */
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#define BM_PORT_CTRL_PAGE		769
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#define BM_WUC_PAGE			800
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#define BM_WUC_ADDRESS_OPCODE		0x11
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#define BM_WUC_DATA_OPCODE		0x12
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#define BM_WUC_ENABLE_PAGE		BM_PORT_CTRL_PAGE
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#define BM_WUC_ENABLE_REG		17
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#define BM_WUC_ENABLE_BIT		(1 << 2)
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   115
#define BM_WUC_HOST_WU_BIT		(1 << 4)
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   116
#define BM_WUC_ME_WU_BIT		(1 << 5)
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   117
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   118
#define PHY_UPPER_SHIFT			21
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   119
#define BM_PHY_REG(page, reg) \
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	(((reg) & MAX_PHY_REG_ADDRESS) |\
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   121
	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
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   122
	 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
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   123
#define BM_PHY_REG_PAGE(offset) \
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   124
	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
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   125
#define BM_PHY_REG_NUM(offset) \
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   126
	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
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   127
	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
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   128
		~MAX_PHY_REG_ADDRESS)))
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   129
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   130
#define HV_INTC_FC_PAGE_START		768
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   131
#define I82578_ADDR_REG			29
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   132
#define I82577_ADDR_REG			16
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   133
#define I82577_CFG_REG			22
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   134
#define I82577_CFG_ASSERT_CRS_ON_TX	(1 << 15)
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   135
#define I82577_CFG_ENABLE_DOWNSHIFT	(3 << 10)	/* auto downshift */
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   136
#define I82577_CTRL_REG			23
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   137
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   138
/* 82577 specific PHY registers */
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   139
#define I82577_PHY_CTRL_2		18
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   140
#define I82577_PHY_LBK_CTRL		19
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   141
#define I82577_PHY_STATUS_2		26
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   142
#define I82577_PHY_DIAG_STATUS		31
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   143
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   144
/* I82577 PHY Status 2 */
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   145
#define I82577_PHY_STATUS2_REV_POLARITY		0x0400
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   146
#define I82577_PHY_STATUS2_MDIX			0x0800
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   147
#define I82577_PHY_STATUS2_SPEED_MASK		0x0300
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   148
#define I82577_PHY_STATUS2_SPEED_1000MBPS	0x0200
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   149
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   150
/* I82577 PHY Control 2 */
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   151
#define I82577_PHY_CTRL2_MANUAL_MDIX		0x0200
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   152
#define I82577_PHY_CTRL2_AUTO_MDI_MDIX		0x0400
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   153
#define I82577_PHY_CTRL2_MDIX_CFG_MASK		0x0600
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   154
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   155
/* I82577 PHY Diagnostics Status */
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   156
#define I82577_DSTATUS_CABLE_LENGTH		0x03FC
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   157
#define I82577_DSTATUS_CABLE_LENGTH_SHIFT	2
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   158
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   159
/* BM PHY Copper Specific Control 1 */
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   160
#define BM_CS_CTRL1			16
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   161
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   162
/* BM PHY Copper Specific Status */
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   163
#define BM_CS_STATUS			17
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   164
#define BM_CS_STATUS_LINK_UP		0x0400
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   165
#define BM_CS_STATUS_RESOLVED		0x0800
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   166
#define BM_CS_STATUS_SPEED_MASK		0xC000
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   167
#define BM_CS_STATUS_SPEED_1000		0x8000
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   168
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   169
/* 82577 Mobile Phy Status Register */
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   170
#define HV_M_STATUS			26
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   171
#define HV_M_STATUS_AUTONEG_COMPLETE	0x1000
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   172
#define HV_M_STATUS_SPEED_MASK		0x0300
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   173
#define HV_M_STATUS_SPEED_1000		0x0200
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   174
#define HV_M_STATUS_LINK_UP		0x0040
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   175
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   176
#define IGP01E1000_PHY_PCS_INIT_REG	0x00B4
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   177
#define IGP01E1000_PHY_POLARITY_MASK	0x0078
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   178
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   179
#define IGP01E1000_PSCR_AUTO_MDIX	0x1000
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   180
#define IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000	/* 0=MDI, 1=MDIX */
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   181
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   182
#define IGP01E1000_PSCFR_SMART_SPEED	0x0080
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   183
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   184
#define IGP02E1000_PM_SPD		0x0001	/* Smart Power Down */
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   185
#define IGP02E1000_PM_D0_LPLU		0x0002	/* For D0a states */
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   186
#define IGP02E1000_PM_D3_LPLU		0x0004	/* For all other states */
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   187
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   188
#define IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
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   189
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   190
#define IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
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   191
#define IGP01E1000_PSSR_MDIX		0x0800
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   192
#define IGP01E1000_PSSR_SPEED_MASK	0xC000
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   193
#define IGP01E1000_PSSR_SPEED_1000MBPS	0xC000
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   194
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   195
#define IGP02E1000_PHY_CHANNEL_NUM	4
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   196
#define IGP02E1000_PHY_AGC_A		0x11B1
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   197
#define IGP02E1000_PHY_AGC_B		0x12B1
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   198
#define IGP02E1000_PHY_AGC_C		0x14B1
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   199
#define IGP02E1000_PHY_AGC_D		0x18B1
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   200
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   201
#define IGP02E1000_AGC_LENGTH_SHIFT	9	/* Course=15:13, Fine=12:9 */
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   202
#define IGP02E1000_AGC_LENGTH_MASK	0x7F
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   203
#define IGP02E1000_AGC_RANGE		15
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   204
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   205
#define E1000_CABLE_LENGTH_UNDEFINED	0xFF
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   206
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   207
#define E1000_KMRNCTRLSTA_OFFSET	0x001F0000
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   208
#define E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
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   209
#define E1000_KMRNCTRLSTA_REN		0x00200000
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   210
#define E1000_KMRNCTRLSTA_CTRL_OFFSET	0x1	/* Kumeran Control */
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   211
#define E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3	/* Kumeran Diagnostic */
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   212
#define E1000_KMRNCTRLSTA_TIMEOUTS	0x4	/* Kumeran Timeouts */
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   213
#define E1000_KMRNCTRLSTA_INBAND_PARAM	0x9	/* Kumeran InBand Parameters */
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   214
#define E1000_KMRNCTRLSTA_IBIST_DISABLE	0x0200	/* Kumeran IBIST Disable */
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   215
#define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000	/* Nearend Loopback mode */
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   216
#define E1000_KMRNCTRLSTA_K1_CONFIG	0x7
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   217
#define E1000_KMRNCTRLSTA_K1_ENABLE	0x0002	/* enable K1 */
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   218
#define E1000_KMRNCTRLSTA_HD_CTRL	0x10	/* Kumeran HD Control */
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   219
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   220
#define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
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   221
#define IFE_PHY_SPECIAL_CONTROL		0x11	/* 100BaseTx PHY Special Ctrl */
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   222
#define IFE_PHY_SPECIAL_CONTROL_LED	0x1B	/* PHY Special and LED Ctrl */
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   223
#define IFE_PHY_MDIX_CONTROL		0x1C	/* MDI/MDI-X Control */
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   224
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   225
/* IFE PHY Extended Status Control */
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   226
#define IFE_PESC_POLARITY_REVERSED	0x0100
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   227
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   228
/* IFE PHY Special Control */
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   229
#define IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
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   230
#define IFE_PSC_FORCE_POLARITY		0x0020
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   231
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   232
/* IFE PHY Special Control and LED Control */
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   233
#define IFE_PSCL_PROBE_MODE		0x0020
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   234
#define IFE_PSCL_PROBE_LEDS_OFF		0x0006	/* Force LEDs 0 and 2 off */
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   235
#define IFE_PSCL_PROBE_LEDS_ON		0x0007	/* Force LEDs 0 and 2 on */
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/* IFE PHY MDIX Control */
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#define IFE_PMC_MDIX_STATUS		0x0020	/* 1=MDI-X, 0=MDI */
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#define IFE_PMC_FORCE_MDIX		0x0040	/* 1=force MDI-X, 0=force MDI */
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#define IFE_PMC_AUTO_MDIX		0x0080	/* 1=enable auto, 0=disable */
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#endif